ARM: OMAP2+: Add CTRL_MODULE_CORE as a master clock provider for DRA7

RFC New Archit Taneja 4 participants 21 messages Apr 16, 2014 – Jun 16, 2014

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Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +3 more subsystems

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Archit Taneja

author

2014-04-16 13:14 UTC #0 lore raw

RFC 1/4 ARM: OMAP2+: Add CTRL_MODULE_CORE as a master clock provider for DRA7

The control module isn't actually a clock management module, but there are a few register bits which perform gating and muxing of clocks.

Add CTRL_MODULE_CORE sub block as a clock provider for DRA7. The control module has 2 sub modules: CTRL_MODULE_CORE, and CTRL_MODULE_WKUP. Out of these, only the CORE sub module has clock related register fields. We ignore the WKUP sub module.

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/mach-omap2/prm_common.c | 1 +
 1 file changed, 1 insertion(+)

arch/arm/mach-omap2/prm_common.c +1 -0

index b4c4ab9..f86029a 100644
@@ -489,6 +489,7 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
 	{ .compatible = "ti,dra7-prm" },
 	{ .compatible = "ti,dra7-cm-core-aon" },
 	{ .compatible = "ti,dra7-cm-core" },
+	{ .compatible = "ti,dra7-ctrl-core" },
 	{ }
 };

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-04-16 13:14 UTC #1 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/boot/dts/dra7.dtsi +13 -0

index 1c0f8e1..58bbdf3 100644
@@ -148,6 +148,19 @@
 			};
 		};
 
+		ctrl_core: ctrl_core at 4a002000 {
+			compatible = "ti,dra7-ctrl-core";
+			reg = <0x4a002000 0x6d0>;
+
+			ctrl_core_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			ctrl_core_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x4ae04000 0x40>;

Signature · 1 line

1.8.3.2

Tony Lindgren

maintainer

2014-04-18 17:18 UTC #2 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Quoted 4 lines · Archit Taneja

Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.

Can you please check if this can just use the existing regmap syscon mapping:

syscon = <&dra7_ctrl_general>;

See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.

Depending what the range 0x4a002000 0x6d0 contains, you may want to set it up as another syscon area.

Regards,

Tony

Quoted 37 lines

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/boot/dts/dra7.dtsi +13 -0

index 1c0f8e1..58bbdf3 100644
@@ -148,6 +148,19 @@
 			};
 		};
 
+		ctrl_core: ctrl_core at 4a002000 {
+			compatible = "ti,dra7-ctrl-core";
+			reg = <0x4a002000 0x6d0>;
+
+			ctrl_core_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			ctrl_core_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter at 4ae04000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x4ae04000 0x40>;

Signature · 7 lines

1.8.3.2


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Archit Taneja

author

2014-04-21 05:15 UTC #3 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Hi,

Quoted 6 lines · Tony Lindgren

Quoted 4 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.

Quoted 8 lines

Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.

The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state.

I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us.

Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot?

Archit

Quoted 7 lines

Depending what the range 0x4a002000 0x6d0 contains, you may want to set it up as another syscon area.
Regards,
Tony

Tony Lindgren

maintainer

2014-04-21 15:10 UTC #4 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Quoted 22 lines · Archit Taneja

Hi,
Quoted 6 lines · Tony Lindgren
Quoted 4 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.
Quoted 8 lines
Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.
The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state.

Quoted 7 lines

I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us.
Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot?

It's best to move the reset and initialization of DSS happen later. I believe we already are resetting only some of the hwmods early on.

Regards,

Tony

Archit Taneja

author

2014-05-06 05:22 UTC #5 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Hi,

Quoted 28 lines · Tony Lindgren

Quoted 27 lines · Archit Taneja
Hi,
Quoted 6 lines · Tony Lindgren
Quoted 4 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.
Quoted 8 lines
Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.
The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state.
I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us.

Quoted 6 lines

Quoted 2 lines
Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot?
It's best to move the reset and initialization of DSS happen later. I believe we already are resetting only some of the hwmods early on.

I looked at this in some more detail. With the current hwmod flags(HWMOD_INIT_NO_RESET/NO_IDLE), we still try to enable the IP, it's just the reset part(ocp reset/custom reset and sysc register) or the disable part that is skipped. hwmod still tries to enable the IP.

This again results in the same issue.

One thing which wasn't clear was that why do we enable a hwmod in the first place, if we know that we are going to skip reset?

Archit

Tony Lindgren

maintainer

2014-05-06 14:26 UTC #6 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Quoted 43 lines · Archit Taneja

Hi,
Quoted 28 lines · Tony Lindgren
Quoted 27 lines · Archit Taneja
Hi,
Quoted 6 lines · Tony Lindgren
Quoted 4 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.
Quoted 8 lines
Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.
The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state.
I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us.
Quoted 6 lines
Quoted 2 lines
Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot?
It's best to move the reset and initialization of DSS happen later. I believe we already are resetting only some of the hwmods early on.
I looked at this in some more detail. With the current hwmod flags(HWMOD_INIT_NO_RESET/NO_IDLE), we still try to enable the IP, it's just the reset part(ocp reset/custom reset and sysc register) or the disable part that is skipped. hwmod still tries to enable the IP.

Quoted 4 lines

This again results in the same issue.
One thing which wasn't clear was that why do we enable a hwmod in the first place, if we know that we are going to skip reset?

Probably to configure the idle bits. In general, we should configure the modules lazily as the driver probes as requested, and then idle the unused modules with a late_initcall.

Regards,

Tony

Archit Taneja

author

2014-05-08 06:02 UTC #7 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Quoted 44 lines · Tony Lindgren

Quoted 43 lines · Archit Taneja
Hi,
Quoted 28 lines · Tony Lindgren
Quoted 27 lines · Archit Taneja
Hi,
Quoted 6 lines · Tony Lindgren
Quoted 4 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register fields which configure clocks. The remainder of the registers are related to pad configurations or cross-bar configurations, and therefore aren't mapped.
Quoted 8 lines
Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.
The thing is that this bit needs to be set before the the DSS hwmods are reset, and that happens very early. If we don't do this, DSS won't reset properly, and not get back to an idle state.
I am not sure where I can configure the syscon register early enough that it happens before the hwmods are reset. With a syscon mapping, I guess we would access the register when the DSS driver is probed. But that's too late for us.
Quoted 6 lines
Quoted 2 lines
Ideally, it would be much better to have a syscon mapping. Do you have any suggestions how this can be achieved very early in boot?
It's best to move the reset and initialization of DSS happen later. I believe we already are resetting only some of the hwmods early on.
I looked at this in some more detail. With the current hwmod flags(HWMOD_INIT_NO_RESET/NO_IDLE), we still try to enable the IP, it's just the reset part(ocp reset/custom reset and sysc register) or the disable part that is skipped. hwmod still tries to enable the IP.

Quoted 8 lines

Quoted 4 lines
This again results in the same issue.
One thing which wasn't clear was that why do we enable a hwmod in the first place, if we know that we are going to skip reset?
Probably to configure the idle bits. In general, we should configure the modules lazily as the driver probes as requested, and then idle the unused modules with a late_initcall.

Okay, we were thinking of changing the hwmod code to skip enable for hwmods(which have the HWMOD_INIT_NO_RESET flag) altogether. But that doesn't seem like a viable option.

I can't think of any other way of getting around this, besides making control module a clock provider.

Paul said that it's not that bad to make DRA7 CTRL module a clock provider, but outside of PRCM code. I guess that would involve having something along the lines of of_prcm_init() in mach-omap2/control.c

Archit

Tero Kristo

2014-05-08 07:53 UTC #8 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Quoted 72 lines · Archit Taneja

Quoted 59 lines · Tony Lindgren
Quoted 58 lines · Archit Taneja
Hi,
Quoted 37 lines · Tony Lindgren
Quoted 36 lines · Archit Taneja
Hi,
Quoted 10 lines · Tony Lindgren
Quoted 8 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the
CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register
fields which configure clocks. The remainder of the registers are related to
pad configurations or cross-bar configurations, and therefore aren't mapped.
Quoted 8 lines
Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.
The thing is that this bit needs to be set before the the DSS hwmods are
reset, and that happens very early. If we don't do this, DSS won't reset
properly, and not get back to an idle state.
I am not sure where I can configure the syscon register early enough that it
happens before the hwmods are reset. With a syscon mapping, I guess we would
access the register when the DSS driver is probed. But that's too late for
us.
Quoted 8 lines
Quoted 3 lines
Ideally, it would be much better to have a syscon mapping. Do you have any
suggestions how this can be achieved very early in boot?
It's best to move the reset and initialization of DSS happen later. I believe
we already are resetting only some of the hwmods early on.
I looked at this in some more detail. With the current hwmod flags(HWMOD_INIT_NO_RESET/NO_IDLE), we still try to enable the IP, it's just
the reset part(ocp reset/custom reset and sysc register) or the disable part
that is skipped. hwmod still tries to enable the IP.
This again results in the same issue.
Quoted 7 lines
Quoted 3 lines
One thing which wasn't clear was that why do we enable a hwmod in the first
place, if we know that we are going to skip reset?
Probably to configure the idle bits. In general, we should configure the modules lazily as the driver probes as requested, and then idle the unused modules with a late_initcall.
Okay, we were thinking of changing the hwmod code to skip enable for hwmods(which have the HWMOD_INIT_NO_RESET flag) altogether. But that doesn't seem like a viable option.

Quoted 6 lines

I can't think of any other way of getting around this, besides making control module a clock provider.
Paul said that it's not that bad to make DRA7 CTRL module a clock provider, but outside of PRCM code. I guess that would involve having something along the lines of of_prcm_init() in mach-omap2/control.c

That sounds like pretty much one of the things I have done here:

https://github.com/t-kristo/linux-pm/tree/3.14-rc4-cm-prm-driver-wip

The patches in their current form haven't been posted yet though, as they are waiting for some of the pre-reqs, but feel free to re-use something from here.

-Tero

Quoted 6 lines

Archit
Archit

Archit Taneja

author

2014-05-08 08:16 UTC #9 lore raw

RFC 2/4 ARM: dts: Add ctrl-core DT node for DRA7

Quoted 80 lines · Tero Kristo

Quoted 72 lines · Archit Taneja
Quoted 59 lines · Tony Lindgren
Quoted 58 lines · Archit Taneja
Hi,
Quoted 37 lines · Tony Lindgren
Quoted 36 lines · Archit Taneja
Hi,
Quoted 10 lines · Tony Lindgren
Quoted 8 lines · Archit Taneja
Add DT node for the ctrl-core sub module of the DRA7 control module. We map the
CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register
fields which configure clocks. The remainder of the registers are related to
pad configurations or cross-bar configurations, and therefore aren't mapped.
Quoted 8 lines
Can you please check if this can just use the existing regmap syscon mapping:
syscon = <&dra7_ctrl_general>;
See how the drivers/regulator/pbias-regulator.c is using the syscon to initialize a regulator and then omap_hsmmc.c just does the standard regulator calls.
The thing is that this bit needs to be set before the the DSS hwmods are
reset, and that happens very early. If we don't do this, DSS won't reset
properly, and not get back to an idle state.
I am not sure where I can configure the syscon register early enough that it
happens before the hwmods are reset. With a syscon mapping, I guess we would
access the register when the DSS driver is probed. But that's too late for
us.
Quoted 8 lines
Quoted 3 lines
Ideally, it would be much better to have a syscon mapping. Do you have any
suggestions how this can be achieved very early in boot?
It's best to move the reset and initialization of DSS happen later. I believe
we already are resetting only some of the hwmods early on.
I looked at this in some more detail. With the current hwmod flags(HWMOD_INIT_NO_RESET/NO_IDLE), we still try to enable the IP, it's just
the reset part(ocp reset/custom reset and sysc register) or the disable part
that is skipped. hwmod still tries to enable the IP.
This again results in the same issue.
Quoted 7 lines
Quoted 3 lines
One thing which wasn't clear was that why do we enable a hwmod in the first
place, if we know that we are going to skip reset?
Probably to configure the idle bits. In general, we should configure the modules lazily as the driver probes as requested, and then idle the unused modules with a late_initcall.
Okay, we were thinking of changing the hwmod code to skip enable for hwmods(which have the HWMOD_INIT_NO_RESET flag) altogether. But that doesn't seem like a viable option.
Quoted 6 lines
I can't think of any other way of getting around this, besides making control module a clock provider.
Paul said that it's not that bad to make DRA7 CTRL module a clock provider, but outside of PRCM code. I guess that would involve having something along the lines of of_prcm_init() in mach-omap2/control.c

Quoted 7 lines

That sounds like pretty much one of the things I have done here:
https://github.com/t-kristo/linux-pm/tree/3.14-rc4-cm-prm-driver-wip
The patches in their current form haven't been posted yet though, as they are waiting for some of the pre-reqs, but feel free to re-use something from here.

Ah nice, thanks!

Archit

Archit Taneja

author

2014-04-16 13:14 UTC #10 lore raw

RFC 3/4 ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core

In reply to Archit Taneja

The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state.

The DESHDCP clock is enabled/disabled at the DSS boundary by the bit DSS_DESHDCP_CLKEN in CTRL_CORE_CONTROL_IO_2.

Add dss_deshdcp gate-clock node under dra7-ctrl-core. There are separate bit fields for enabling and disabling the clock. We just map the enable bit since this clock doesn't cause any impact if left enabled.

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/boot/dts/dra7xx-clocks.dtsi +10 -0

index e96da9a..78d309c 100644
@@ -2007,6 +2007,16 @@
 	};
 };
 
+&ctrl_core_clocks {
+	dss_deshdcp_clk: dss_deshdcp_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_iclk_div>;
+		ti,bit-shift = <0>;
+		reg = <0x0558>;
+	};
+};
+
 &cm_core_clockdomains {
 	coreaon_clkdm: coreaon_clkdm {
 		compatible = "ti,clockdomain";

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-04-16 13:14 UTC #11 lore raw

RFC 4/4 CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init

In reply to Archit Taneja

The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state.

This is because the DSS IP is designed in such a way that if DES-HDCP block can't transition from idle state, the entire DSS clock domain also cannot transition from idle to enabled. DES-HDCP block needs the DESHDCP clock enabled to transition from idle successfully.

We enable the deshdcp clock in dra7xx_clk_init() which happens before omap hwmods are setup. This clock is effectively a gate clock with the parent as DSS_L3_GICLK. The parent is an automatically controlled clock by DSS clock domain and hence doesn't have a clock node associated to it. Since DSS_L3_GICLK is derived from the OCP clock, we set the dss_deshdcp_clk's parent as l3_iclk_div.

Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only a very few flops get this clock all the time. So there is negligible impact.

Signed-off-by Archit Taneja <[email protected]>

---
 drivers/clk/ti/clk-7xx.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

drivers/clk/ti/clk-7xx.c +7 -1

index f7e4073..3f73a02 100644
@@ -179,6 +179,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 	DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
 	DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
 	DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
+	DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
 	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
 	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
 	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),

@@ -306,7 +307,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 int __init dra7xx_dt_clk_init(void)
 {
 	int rc;
-	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
 
 	ti_dt_clocks_register(dra7xx_clks);

@@ -327,5 +328,10 @@ int __init dra7xx_dt_clk_init(void)
 	if (rc)
 		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
 
+	dss_deshdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+	rc = clk_prepare_enable(dss_deshdcp_ck);
+	if (rc)
+		pr_err("%s: failed to enable DESHDCP clock\n", __func__);
+
 	return rc;
 }

Signature · 1 line

1.8.3.2

Paul Walmsley

maintainer

2014-05-08 01:19 UTC #12 lore raw

RFC 1/4 ARM: OMAP2+: Add CTRL_MODULE_CORE as a master clock provider for DRA7

In reply to Archit Taneja

Quoted 18 lines · Archit Taneja

The control module isn't actually a clock management module, but there are a few register bits which perform gating and muxing of clocks.
Add CTRL_MODULE_CORE sub block as a clock provider for DRA7. The control module has 2 sub modules: CTRL_MODULE_CORE, and CTRL_MODULE_WKUP. Out of these, only the CORE sub module has clock related register fields. We ignore the WKUP sub module.
Signed-off-by Archit Taneja <[email protected]>
---
 arch/arm/mach-omap2/prm_common.c | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-omap2/prm_common.c +0 -0
index b4c4ab9..f86029a 100644

arch/arm/mach-omap2/prm_common.c static struct of_device_id omap_prcm_dt_match_table[] = { · line 494

Quoted 6 lines

arch/arm/mach-omap2/prm_common.c +1 -0

@@ -489,6 +489,7 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
 	{ .compatible = "ti,dra7-prm" },
 	{ .compatible = "ti,dra7-cm-core-aon" },
 	{ .compatible = "ti,dra7-cm-core" },
+	{ .compatible = "ti,dra7-ctrl-core" },
 	{ }
 };

So, based on a quick glance, and without the benefit of any documentation, it makes general sense to add the DRA7 CTRL module as a clock provider, but it does not make any sense to associate it with the PRCM. Please find a control module-specific piece of code to register as a clock provider, not prm_common.c.

- Paul

Archit Taneja

author

2014-05-28 10:52 UTC #13 lore raw

v2 cover ARM: dts: Add a new clk provider, and implement dss_deshdcp clock with it

In reply to Archit Taneja

This series tries to create CONTROL_MODULE_CORE as a new clock provider, and create a clock using it required by DSS on DRA7.

The previous revision of the series added the new clock provider within prcm driver code itself. Suggestions were made by Paul and Tero to move it to control module driver code.

I picked up 2 patches from Tero's WIP branch below, and added DRA7's control module core block as a clock provider. The DSS_DESHDCP clock is easy to implement after that.

https://github.com/t-kristo/linux-pm/tree/3.14-rc4-cm-prm-driver-wip

Archit Taneja (5):
ARM: PRCM: split PRCM module init to their own driver files
ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x
ARM: dts: Add ctrl-core DT node for DRA7
ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core
CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init

Tero Kristo (1):
CLK: TI: clockdomain: add support for retrying init

 arch/arm/boot/dts/dra7.dtsi          | 13 ++++++
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 10 +++++
 arch/arm/mach-omap2/cm_common.c      | 18 +++++++++
 arch/arm/mach-omap2/control.c        | 35 ++++++++++++++++
 arch/arm/mach-omap2/control.h        |  1 +
 arch/arm/mach-omap2/io.c             |  4 ++
 arch/arm/mach-omap2/prcm-common.h    |  5 +++
 arch/arm/mach-omap2/prm_common.c     | 55 +++++++++++++++-----------
 drivers/clk/ti/clk-7xx.c             |  8 +++-
 drivers/clk/ti/clockdomain.c         | 77 ++++++++++++++++++++++++++++++------
 include/linux/clk/ti.h               |  2 +-
 11 files changed, 192 insertions(+), 36 deletions(-)

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-05-28 10:52 UTC #14 lore raw

RFC v2 1/6 CLK: TI: clockdomain: add support for retrying init

From: Tero Kristo <[email protected]>

Retry init is needed if clockdomains are registered before the corresponding clocks are ready. In this case, the clockdomain info is added to a list which will be processed once the clockdomains for next PRCM module are processed.

Signed-off-by Tero Kristo <[email protected]>

---
 arch/arm/mach-omap2/prm_common.c |  3 +-
 drivers/clk/ti/clockdomain.c     | 77 ++++++++++++++++++++++++++++++++++------
 include/linux/clk/ti.h           |  2 +-
 3 files changed, 68 insertions(+), 14 deletions(-)

arch/arm/mach-omap2/prm_common.c +1 -2

index b4c4ab9..56462af 100644
@@ -523,10 +523,9 @@ int __init of_prcm_init(void)
 		mem = of_iomap(np, 0);
 		clk_memmaps[memmap_index] = mem;
 		ti_dt_clk_init_provider(np, memmap_index);
+		ti_dt_clockdomains_setup(np);
 		memmap_index++;
 	}
 
-	ti_dt_clockdomains_setup();
-
 	return 0;
 }

drivers/clk/ti/clockdomain.c +66 ~~-11~~

102 lines not on this page · raw message

include/linux/clk/ti.h +1 -1

index 4a21a87..20dd7c0 100644
@@ -263,7 +263,7 @@ void omap3_clk_lock_dpll5(void);
 void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
 void ti_dt_clocks_register(struct ti_dt_clk *oclks);
 void ti_dt_clk_init_provider(struct device_node *np, int index);
-void ti_dt_clockdomains_setup(void);
+void ti_dt_clockdomains_setup(struct device_node *node);
 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
 		      ti_of_clk_init_cb_t func);
 int of_ti_clk_autoidle_setup(struct device_node *node);

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-05-28 10:52 UTC #15 lore raw

RFC v2 2/6 ARM: PRCM: split PRCM module init to their own driver files

In reply to Archit Taneja

Currently, clock providers coming from CM, PRM, and SCRM are all initialized in prm_common.c.

Move the DT-match tables to their respective files, and create separate init functions for each module.

Originally worked on by: Tero Kristo <[email protected]>

Cc Tero Kristo <[email protected]>

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/mach-omap2/cm_common.c   | 18 ++++++++++++++
 arch/arm/mach-omap2/control.c     | 15 +++++++++++
 arch/arm/mach-omap2/control.h     |  1 +
 arch/arm/mach-omap2/io.c          |  4 +++
 arch/arm/mach-omap2/prcm-common.h |  5 ++++
 arch/arm/mach-omap2/prm_common.c  | 52 +++++++++++++++++++++++----------------
 6 files changed, 74 insertions(+), 21 deletions(-)

arch/arm/mach-omap2/cm_common.c +18 -0

index 40b3b5a..8506990 100644
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/of.h>
 
 #include "cm2xxx.h"
 #include "cm3xxx.h"

@@ -138,3 +139,20 @@ int cm_unregister(struct cm_ll_data *cld)
 
 	return 0;
 }
+
+static struct of_device_id omap_cm_dt_match_table[] = {
+	{ .compatible = "ti,omap3-cm" },
+	{ .compatible = "ti,omap4-cm1" },
+	{ .compatible = "ti,omap4-cm2" },
+	{ .compatible = "ti,omap5-cm-core-aon" },
+	{ .compatible = "ti,omap5-cm-core" },
+	{ .compatible = "ti,dra7-cm-core-aon" },
+	{ .compatible = "ti,dra7-cm-core" },
+	{ }
+};
+
+
+int __init of_cm_init(void)
+{
+	return of_prcm_module_init(omap_cm_dt_match_table);
+}

arch/arm/mach-omap2/control.c +15 -0

index 44bb4d5..12cd736 100644
@@ -581,3 +581,18 @@ void omap3_ctrl_set_iva_bootmode_idle(void)
 			 OMAP343X_CONTROL_IVA2_BOOTMOD);
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+
+static struct of_device_id omap_scrm_dt_match_table[] = {
+	{ .compatible = "ti,am3-scrm" },
+	{ .compatible = "ti,am4-scrm" },
+	{ .compatible = "ti,omap2-scrm" },
+	{ .compatible = "ti,omap3-scrm" },
+	{ .compatible = "ti,omap4-scrm" },
+	{ .compatible = "ti,omap5-scrm" },
+	{ }
+};
+
+int __init of_scrm_init(void)
+{
+	return of_prcm_module_init(omap_scrm_dt_match_table);
+}

arch/arm/mach-omap2/control.h +1 -0

index da05480..5d695f1 100644
@@ -428,6 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 extern void omap3_ctrl_set_iva_bootmode_idle(void);
+int of_scrm_init(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
 				      void __iomem *ctrl_pad);
 #else

arch/arm/mach-omap2/io.c +4 -0

index f14f9ac..c78e2b8 100644
@@ -725,6 +725,10 @@ int __init omap_clk_init(void)
 	if (!omap_clk_soc_init)
 		return 0;
 
+	ret = of_scrm_init();
+	if (ret)
+		return ret;
+
 	ret = of_prcm_init();
 	if (!ret)
 		ret = omap_clk_soc_init();

arch/arm/mach-omap2/prcm-common.h +5 -0

index 0e841fd..a68d98e 100644
@@ -493,6 +493,8 @@ struct omap_prcm_irq_setup {
 	.priority = _priority				\
 	}
 
+struct of_device_id;
+
 extern void omap_prcm_irq_cleanup(void);
 extern int omap_prcm_register_chain_handler(
 	struct omap_prcm_irq_setup *irq_setup);

@@ -500,6 +502,9 @@ extern int omap_prcm_event_to_irq(const char *event);
 extern void omap_prcm_irq_prepare(void);
 extern void omap_prcm_irq_complete(void);
 
+int of_prcm_module_init(struct of_device_id *match_table);
+int of_cm_init(void);
+
 # endif
 
 #endif

arch/arm/mach-omap2/prm_common.c +31 ~~-21~~

77 lines not on this page · raw message

Signature · 1 line

1.8.3.2

Tony Lindgren

maintainer

2014-06-16 11:48 UTC #16 lore raw

Re: [RFC v2 2/6] ARM: PRCM: split PRCM module init to their own driver files

Quoted 65 lines · Archit Taneja

Currently, clock providers coming from CM, PRM, and SCRM are all initialized in prm_common.c.

Move the DT-match tables to their respective files, and create separate init functions for each module.

Originally worked on by: Tero Kristo <[email protected]>

Cc Tero Kristo <[email protected]>

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/mach-omap2/cm_common.c   | 18 ++++++++++++++
 arch/arm/mach-omap2/control.c     | 15 +++++++++++
 arch/arm/mach-omap2/control.h     |  1 +
 arch/arm/mach-omap2/io.c          |  4 +++
 arch/arm/mach-omap2/prcm-common.h |  5 ++++
 arch/arm/mach-omap2/prm_common.c  | 52 +++++++++++++++++++++++----------------
 6 files changed, 74 insertions(+), 21 deletions(-)

arch/arm/mach-omap2/cm_common.c +18 -0

index 40b3b5a..8506990 100644
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/of.h>
 
 #include "cm2xxx.h"
 #include "cm3xxx.h"

@@ -138,3 +139,20 @@ int cm_unregister(struct cm_ll_data *cld)
 
 	return 0;
 }
+
+static struct of_device_id omap_cm_dt_match_table[] = {
+	{ .compatible = "ti,omap3-cm" },
+	{ .compatible = "ti,omap4-cm1" },
+	{ .compatible = "ti,omap4-cm2" },
+	{ .compatible = "ti,omap5-cm-core-aon" },
+	{ .compatible = "ti,omap5-cm-core" },
+	{ .compatible = "ti,dra7-cm-core-aon" },
+	{ .compatible = "ti,dra7-cm-core" },
+	{ }
+};
+
+
+int __init of_cm_init(void)
+{
+	return of_prcm_module_init(omap_cm_dt_match_table);
+}

arch/arm/mach-omap2/control.c +5 -0

index 44bb4d5..12cd736 100644
@@ -581,3 +581,18 @@ void omap3_ctrl_set_iva_bootmode_idle(void)
 			 OMAP343X_CONTROL_IVA2_BOOTMOD);
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+
+static struct of_device_id omap_scrm_dt_match_table[] = {
+	{ .compatible = "ti,am3-scrm" },
+	{ .compatible = "ti,am4-scrm" },
+	{ .compatible = "ti,omap2-scrm" },

arch/arm/mach-omap2/control.c void omap3_ctrl_set_iva_bootmode_idle(void) · line 598

Quoted 10 lines

arch/arm/mach-omap2/control.c +10 -0

+	{ .compatible = "ti,omap3-scrm" },
+	{ .compatible = "ti,omap4-scrm" },
+	{ .compatible = "ti,omap5-scrm" },
+	{ }
+};
+
+int __init of_scrm_init(void)
+{
+	return of_prcm_module_init(omap_scrm_dt_match_table);
+}

I think you may be able to leave out this driver like code from arch/arm/mach-omap2 by using the existing syscon mapping we have in the .dtsi files? See for example how the PBIAS is using the syscon in drivers/regulator/pbias-regulator.c.

If the clock registers don't fall into the existing SCM syscon area, we can also set up more syscon areas.

Regards,

Tony

Archit Taneja

author

2014-05-28 10:52 UTC #17 lore raw

RFC v2 3/6 ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x

In reply to Archit Taneja

In DRA7x SoCs, the CONTROL_MODULE_CORE sub block in the control module has a few register fields which perform gating or muxing of clocks.

These gate/muxes are generally SoC level clocks entering an IP, which didn't manage to make it in the clock management related registers for the IP.

Other OMAP SOCs don't seem to have clock related register fields in the control module.

We create a new table and function to init ctrl-core IPS as clock providers. This, along with scrm clock providers, are initialized in of_control_init(). We add a compatible string for dra7-ctrl-core in the DT match table.

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/mach-omap2/control.c | 22 +++++++++++++++++++++-
 arch/arm/mach-omap2/control.h |  2 +-
 arch/arm/mach-omap2/io.c      |  2 +-
 3 files changed, 23 insertions(+), 3 deletions(-)

arch/arm/mach-omap2/control.c +21 -1

index 12cd736..d9567bc 100644
@@ -592,7 +592,27 @@ static struct of_device_id omap_scrm_dt_match_table[] = {
 	{ }
 };
 
-int __init of_scrm_init(void)
+static int __init of_scrm_init(void)
 {
 	return of_prcm_module_init(omap_scrm_dt_match_table);
 }
+
+static struct of_device_id omap_ctrl_core_dt_match_table[] = {
+	{ .compatible = "ti,dra7-ctrl-core" },
+	{ }
+};
+
+static int __init of_ctrl_core_init(void)
+{
+	return of_prcm_module_init(omap_ctrl_core_dt_match_table);
+}
+
+int __init of_control_init(void)
+{
+	int ret;
+
+	ret = of_scrm_init();
+	ret |= of_ctrl_core_init();
+
+	return ret;
+}

arch/arm/mach-omap2/control.h +1 -1

index 5d695f1..405979e 100644
@@ -428,7 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 extern void omap3_ctrl_set_iva_bootmode_idle(void);
-int of_scrm_init(void);
+int of_control_init(void);
 extern void omap2_set_globals_control(void __iomem *ctrl,
 				      void __iomem *ctrl_pad);
 #else

arch/arm/mach-omap2/io.c +1 -1

index c78e2b8..49e344b 100644
@@ -725,7 +725,7 @@ int __init omap_clk_init(void)
 	if (!omap_clk_soc_init)
 		return 0;
 
-	ret = of_scrm_init();
+	ret = of_control_init();
 	if (ret)
 		return ret;

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-05-28 10:52 UTC #18 lore raw

RFC v2 4/6 ARM: dts: Add ctrl-core DT node for DRA7

In reply to Archit Taneja

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/boot/dts/dra7.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/boot/dts/dra7.dtsi +13 -0

index 149b550..14d1905 100644
@@ -148,6 +148,19 @@
 			};
 		};
 
+		ctrl_core: ctrl_core@4a002000 {
+			compatible = "ti,dra7-ctrl-core";
+			reg = <0x4a002000 0x6d0>;
+
+			ctrl_core_clocks: clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			ctrl_core_clockdomains: clockdomains {
+			};
+		};
+
 		counter32k: counter@4ae04000 {
 			compatible = "ti,omap-counter32k";
 			reg = <0x4ae04000 0x40>;

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-05-28 10:52 UTC #19 lore raw

RFC v2 5/6 ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core

In reply to Archit Taneja

The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state.

The DESHDCP clock is enabled/disabled at the DSS boundary by the bit DSS_DESHDCP_CLKEN in CTRL_CORE_CONTROL_IO_2.

Signed-off-by Archit Taneja <[email protected]>

---
 arch/arm/boot/dts/dra7xx-clocks.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/boot/dts/dra7xx-clocks.dtsi +10 -0

index cfb8fc7..a1653ba 100644
@@ -2007,6 +2007,16 @@
 	};
 };
 
+&ctrl_core_clocks {
+	dss_deshdcp_clk: dss_deshdcp_clk {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_iclk_div>;
+		ti,bit-shift = <0>;
+		reg = <0x0558>;
+	};
+};
+
 &cm_core_clockdomains {
 	coreaon_clkdm: coreaon_clkdm {
 		compatible = "ti,clockdomain";

Signature · 1 line

1.8.3.2

Archit Taneja

author

2014-05-28 10:52 UTC #20 lore raw

RFC v2 6/6 CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init

In reply to Archit Taneja

The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state.

Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only a very few flops get this clock all the time. So there is negligible impact.

Signed-off-by Archit Taneja <[email protected]>

---
 drivers/clk/ti/clk-7xx.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

drivers/clk/ti/clk-7xx.c +7 -1

index f7e4073..3f73a02 100644
@@ -179,6 +179,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 	DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
 	DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
 	DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
+	DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
 	DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
 	DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
 	DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),

@@ -306,7 +307,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
 int __init dra7xx_dt_clk_init(void)
 {
 	int rc;
-	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck;
+	struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
 
 	ti_dt_clocks_register(dra7xx_clks);

@@ -327,5 +328,10 @@ int __init dra7xx_dt_clk_init(void)
 	if (rc)
 		pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
 
+	dss_deshdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
+	rc = clk_prepare_enable(dss_deshdcp_ck);
+	if (rc)
+		pr_err("%s: failed to enable DESHDCP clock\n", __func__);
+
 	return rc;
 }

Signature · 1 line

1.8.3.2