Skip to contentSkip to conversation

cxgb4: Decode PCIe Gen3 link speed

PATCH Applied Roland Dreier 2 participants 2 messages Apr 29, 2014 – Apr 30, 2014

Subsystems (3)
Networking Network drivers CXGB4 Ethernet driver (CXGB4)
lore
Share & tools
lore

Roland Dreier

author
#0 lore raw

PATCH 1/1 cxgb4: Decode PCIe Gen3 link speed

From: Roland Dreier <[email protected]>

Add handling for " 8 GT/s" in print_port_info().

Signed-off-by Roland Dreier <[email protected]>
---
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +2 -0
index 6fe58913403a..24e16e3301e0 100644
@@ -5870,6 +5870,8 @@ static void print_port_info(const struct net_device *dev)
 		spd = " 2.5 GT/s";
 	else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
 		spd = " 5 GT/s";
+	else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
+		spd = " 8 GT/s";
 
 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
 		bufp += sprintf(bufp, "100/");
Signature · 1 line
1.9.1