reset: add reset controller framework

PATCH New Lucas Stach 1 participant 25 messages May 14, 2014

Subsystems (11)

Arm (32-bit) Arm sub-architectures Kbuild Common clk +7 more subsystems

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Lucas Stach

author

2014-05-14 20:47 UTC #0 lore raw

PATCH v2 1/25 reset: add reset controller framework

Add stripped sown version of the reset controller
framework from the Linux kernel.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/Kconfig                  |   1 +
 drivers/Makefile                 |   1 +
 drivers/reset/Kconfig            |  13 +++
 drivers/reset/Makefile           |   1 +
 drivers/reset/core.c             | 236 +++++++++++++++++++++++++++++++++++++++
 include/linux/reset-controller.h |  50 +++++++++
 include/linux/reset.h            |  67 +++++++++++
 7 files changed, 369 insertions(+)
 create mode 100644 drivers/reset/Kconfig
 create mode 100644 drivers/reset/Makefile
 create mode 100644 drivers/reset/core.c
 create mode 100644 include/linux/reset-controller.h
 create mode 100644 include/linux/reset.h

drivers/Kconfig +1 -0

index 7a2aa2810cb3..53e1e975600c 100644
@@ -26,5 +26,6 @@ source "drivers/w1/Kconfig"
 source "drivers/pinctrl/Kconfig"
 source "drivers/bus/Kconfig"
 source "drivers/regulator/Kconfig"
+source "drivers/reset/Kconfig"
 
 endmenu

drivers/Makefile +1 -0

index f79da89e94f6..ef3604f56cb8 100644
@@ -25,3 +25,4 @@ obj-$(CONFIG_W1) += w1/
 obj-y += pinctrl/
 obj-y += bus/
 obj-$(CONFIG_REGULATOR) += regulator/
+obj-$(CONFIG_RESET_CONTROLLER) += reset/

drivers/reset/Kconfig new file +13 -0

new file mode 100644
index 000000000000..c9d04f797862
@@ -0,0 +1,13 @@
+config ARCH_HAS_RESET_CONTROLLER
+	bool
+
+menuconfig RESET_CONTROLLER
+	bool "Reset Controller Support"
+	default y if ARCH_HAS_RESET_CONTROLLER
+	help
+	  Generic Reset Controller support.
+
+	  This framework is designed to abstract reset handling of devices
+	  via GPIOs or SoC-internal reset controller modules.
+
+	  If unsure, say no.

drivers/reset/Makefile new file +1 -0

new file mode 100644
index 000000000000..1e2d83f2b995
@@ -0,0 +1 @@
+obj-$(CONFIG_RESET_CONTROLLER) += core.o

drivers/reset/core.c new file +236 -0

236 lines not on this page · raw message

include/linux/reset-controller.h new file +50 -0

50 lines not on this page · raw message

include/linux/reset.h new file +67 -0

67 lines not on this page · raw message

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Lucas Stach

author

2014-05-14 20:46 UTC #1 lore raw

PATCH v2 2/25 tegra: lowlevel: add function to fetch chipid

This is needed as a safe way to flush the ABP bus.

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/mach-tegra/include/mach/lowlevel.h | 6 ++++++
 1 file changed, 6 insertions(+)

arch/arm/mach-tegra/include/mach/lowlevel.h +6 -0

index 52b405d5f859..10265183c10c 100644
@@ -70,6 +70,12 @@ enum tegra_chiptype {
 };
 
 static __always_inline
+u32 tegra_read_chipid(void)
+{
+	return readl(TEGRA_APB_MISC_BASE + APB_MISC_HIDREV);
+}
+
+static __always_inline
 enum tegra_chiptype tegra_get_chiptype(void)
 {
 	u32 hidrev;

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Lucas Stach

author

2014-05-14 20:47 UTC #2 lore raw

PATCH v2 3/25 reset: add tegra reset controller

In reply to Lucas Stach

Allows us to drop the hack in the clock controller and implement proper reset at device level.

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/Kconfig                |   1 +
 drivers/clk/tegra/clk-tegra20.c |   2 +
 drivers/clk/tegra/clk-tegra30.c |   2 +
 drivers/clk/tegra/clk.c         | 134 +++++++++++++++++++++++++++++++++++++++-
 drivers/clk/tegra/clk.h         |  12 ++++
 5 files changed, 150 insertions(+), 1 deletion(-)

arch/arm/Kconfig +1 -0

index 4a2ec41bb425..f93ef4c62673 100644
@@ -192,6 +192,7 @@ config ARCH_TEGRA
 	select OFDEVICE
 	select OFTREE
 	select RELOCATABLE
+	select RESET_CONTROLLER
 
 config ARCH_ZYNQ
 	bool "Xilinx Zynq-based boards"

drivers/clk/tegra/clk-tegra20.c +2 -0

index ea39f46b15fe..7c7a915b40d4 100644
@@ -347,6 +347,8 @@ static int tegra20_car_probe(struct device_d *dev)
 	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
 			    &clk_data);
 
+	tegra_clk_init_rst_controller(car_base, dev->device_node, 3 * 32);
+
 	return 0;
 }

drivers/clk/tegra/clk-tegra30.c +2 -0

index 94bbeace4ae4..adb5824e4be8 100644
@@ -341,6 +341,8 @@ static int tegra30_car_probe(struct device_d *dev)
 	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
 			    &clk_data);
 
+	tegra_clk_init_rst_controller(car_base, dev->device_node, 6 * 32);
+
 	return 0;
 }

drivers/clk/tegra/clk.c +133 -1

150 lines not on this page · raw message

drivers/clk/tegra/clk.h +12 -0

index 9bb8f1c45734..29d5249b2ec4 100644
@@ -148,3 +148,15 @@ struct tegra_clk_init_table {
 
 void tegra_init_from_table(struct tegra_clk_init_table *tbl,
 		struct clk *clks[], int clk_max);
+
+struct tegra_clk_periph_regs {
+	u32 enb_reg;
+	u32 enb_set_reg;
+	u32 enb_clr_reg;
+	u32 rst_reg;
+	u32 rst_set_reg;
+	u32 rst_clr_reg;
+};
+
+void tegra_clk_init_rst_controller(void __iomem *base, struct device_node *np,
+		unsigned int num);

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Lucas Stach

author

2014-05-14 20:46 UTC #3 lore raw

PATCH v2 4/25 clk: tegra: reset UARTS from clock controller

In reply to Lucas Stach

The console devices are the only ones that can't use the reset controller properly, as they get registered from platform code. Reset those devices from the clock controller.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/tegra/clk-tegra20.c |  1 +
 drivers/clk/tegra/clk-tegra30.c |  1 +
 drivers/clk/tegra/clk.c         | 11 +++++++++++
 drivers/clk/tegra/clk.h         |  2 ++
 4 files changed, 15 insertions(+)

drivers/clk/tegra/clk-tegra20.c +1 -0

index 7c7a915b40d4..cb0a57181de4 100644
@@ -348,6 +348,7 @@ static int tegra20_car_probe(struct device_d *dev)
 			    &clk_data);
 
 	tegra_clk_init_rst_controller(car_base, dev->device_node, 3 * 32);
+	tegra_clk_reset_uarts();
 
 	return 0;
 }

drivers/clk/tegra/clk-tegra30.c +1 -0

index adb5824e4be8..9536288f89ac 100644
@@ -342,6 +342,7 @@ static int tegra30_car_probe(struct device_d *dev)
 			    &clk_data);
 
 	tegra_clk_init_rst_controller(car_base, dev->device_node, 6 * 32);
+	tegra_clk_reset_uarts();
 
 	return 0;
 }

drivers/clk/tegra/clk.c +11 -0

index a6b81d029b9e..cb4d92020392 100644
@@ -187,3 +187,14 @@ void tegra_clk_init_rst_controller(void __iomem *base, struct device_node *np,
 	rst_ctlr.nr_resets = num;
 	reset_controller_register(&rst_ctlr);
 }
+
+void tegra_clk_reset_uarts(void) {
+	int i;
+	int console_device_ids[] = {6, 7, 55, 65, 66};
+
+	for (i = 0; i < ARRAY_SIZE(console_device_ids); i++) {
+		rst_ops.assert(&rst_ctlr, console_device_ids[i]);
+		udelay(2);
+		rst_ops.deassert(&rst_ctlr, console_device_ids[i]);
+	}
+};

drivers/clk/tegra/clk.h +2 -0

index 29d5249b2ec4..6ce9f7e26daa 100644
@@ -160,3 +160,5 @@ struct tegra_clk_periph_regs {
 
 void tegra_clk_init_rst_controller(void __iomem *base, struct device_node *np,
 		unsigned int num);
+
+void tegra_clk_reset_uarts(void);

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Lucas Stach

author

2014-05-14 20:46 UTC #4 lore raw

PATCH v2 5/25 mci: tegra: add reset control

In reply to Lucas Stach

Enable the driver to reset the device itself.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/mci/tegra-sdmmc.c | 9 +++++++++
 1 file changed, 9 insertions(+)

drivers/mci/tegra-sdmmc.c +9 -0

index e4d82197bde7..0ea0b5ca4a92 100644
@@ -28,6 +28,7 @@
 #include <mci.h>
 #include <of_gpio.h>
 #include <linux/clk.h>
+#include <linux/reset.h>
 
 #include "sdhci.h"

@@ -62,6 +63,7 @@ struct tegra_sdmmc_host {
 	struct mci_host		mci;
 	void __iomem		*regs;
 	struct clk		*clk;
+	struct reset_control	*reset;
 	int			gpio_cd, gpio_pwr;
 };
 #define to_tegra_sdmmc_host(mci) container_of(mci, struct tegra_sdmmc_host, mci)

@@ -400,6 +402,10 @@ static int tegra_sdmmc_probe(struct device_d *dev)
 	if (IS_ERR(host->clk))
 		return PTR_ERR(host->clk);
 
+	host->reset = reset_control_get(dev, NULL);
+	if (IS_ERR(host->reset))
+		return PTR_ERR(host->reset);
+
 	host->regs = dev_request_mem_region(dev, 0);
 	if (!host->regs) {
 		dev_err(dev, "could not get iomem region\n");

@@ -430,6 +436,9 @@ static int tegra_sdmmc_probe(struct device_d *dev)
 	}
 
 	clk_enable(host->clk);
+	reset_control_assert(host->reset);
+	udelay(2);
+	reset_control_deassert(host->reset);
 
 	mci->init = tegra_sdmmc_init;
 	mci->card_present = tegra_sdmmc_card_present;

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Lucas Stach

author

2014-05-14 20:46 UTC #5 lore raw

PATCH v2 6/25 clk: tegra: remove device reset hack

In reply to Lucas Stach

Now that we have a proper reset controller, it
isn't necessary anymore to keep the device reset
hack coupled to the clock.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/tegra/clk-periph.c | 18 ------------------
 1 file changed, 18 deletions(-)

drivers/clk/tegra/clk-periph.c +0 ~~-18~~

index be83955db1a5..c05e563aae55 100644
@@ -74,33 +74,15 @@ static int clk_periph_is_enabled(struct clk *hw)
 static int clk_periph_enable(struct clk *hw)
 {
 	struct tegra_clk_periph *periph = to_clk_periph(hw);
-	u32 reg;
-
-	reg = readl(periph->rst_reg);
-	reg |= (1 << periph->rst_shift);
-	writel(reg, periph->rst_reg);
 
 	periph->gate->ops->enable(periph->gate);
 
-	udelay(2);
-
-	reg = readl(periph->rst_reg);
-	reg &= ~(1 << periph->rst_shift);
-	writel(reg, periph->rst_reg);
-
 	return 0;
 }
 
 static void clk_periph_disable(struct clk *hw)
 {
 	struct tegra_clk_periph *periph = to_clk_periph(hw);
-	u32 reg;
-
-	reg = readl(periph->rst_reg);
-	reg |= (1 << periph->rst_shift);
-	writel(reg, periph->rst_reg);
-
-	udelay(2);
 
 	periph->gate->ops->disable(periph->gate);
 }

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Lucas Stach

author

2014-05-14 20:47 UTC #6 lore raw

PATCH v2 7/25 clk: tegra: allow to register clocks with 16 bit divider

In reply to Lucas Stach

Some peripherals have a double wide divider in front of them.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/tegra/clk-periph.c | 28 +++++++++++++++++++++-------
 drivers/clk/tegra/clk.h        |  4 ++++
 2 files changed, 25 insertions(+), 7 deletions(-)

drivers/clk/tegra/clk-periph.c +21 -7

index c05e563aae55..e4e5412b0980 100644
@@ -106,10 +106,10 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
 	.disable = clk_periph_disable,
 };
 
-struct clk *_tegra_clk_register_periph(const char *name,
+static struct clk *_tegra_clk_register_periph(const char *name,
 		const char **parent_names, int num_parents,
 		void __iomem *clk_base, u32 reg_offset, u8 id, u8 flags,
-		bool has_div)
+		int div)
 {
 	struct tegra_clk_periph *periph;
 	int ret, gate_offs, rst_offs;

@@ -136,15 +136,20 @@ struct clk *_tegra_clk_register_periph(const char *name,
 	if (!periph->gate)
 		goto out_gate;
 
-	if (has_div) {
+	if (div == 8) {
 		periph->div = tegra_clk_divider_alloc(NULL, NULL, clk_base +
-				reg_offset, 0, TEGRA_DIVIDER_ROUND_UP, 0, 8, 1);
+		              reg_offset, 0, TEGRA_DIVIDER_ROUND_UP, 0, 8, 1);
+		if (!periph->div)
+			goto out_div;
+	} else if (div == 16) {
+		periph->div = tegra_clk_divider_alloc(NULL, NULL, clk_base +
+		              reg_offset, 0, TEGRA_DIVIDER_ROUND_UP, 0, 16, 0);
 		if (!periph->div)
 			goto out_div;
 	}
 
 	periph->hw.name = name;
-	periph->hw.ops = has_div ? &tegra_clk_periph_ops :
+	periph->hw.ops = div ? &tegra_clk_periph_ops :
 				   &tegra_clk_periph_nodiv_ops;
 	periph->hw.parent_names = parent_names;
 	periph->hw.num_parents = num_parents;

@@ -181,7 +186,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
 {
 	return _tegra_clk_register_periph(name, parent_names, num_parents,
 					  clk_base, reg_offset, id, flags,
-					  false);
+					  0);
 }
 
 struct clk *tegra_clk_register_periph(const char *name,

@@ -190,5 +195,14 @@ struct clk *tegra_clk_register_periph(const char *name,
 {
 	return _tegra_clk_register_periph(name, parent_names, num_parents,
 					  clk_base, reg_offset, id, flags,
-					  true);
+					  8);
+}
+
+struct clk *tegra_clk_register_periph_div16(const char *name,
+		const char **parent_names, int num_parents,
+		void __iomem *clk_base, u32 reg_offset, u8 id, u8 flags)
+{
+	return _tegra_clk_register_periph(name, parent_names, num_parents,
+					  clk_base, reg_offset, id, flags,
+					  16);
 }

drivers/clk/tegra/clk.h +4 -0

index 6ce9f7e26daa..d5d07306021c 100644
@@ -138,6 +138,10 @@ struct clk *tegra_clk_register_periph(const char *name,
 		const char **parent_names, int num_parents,
 		void __iomem *clk_base, u32 reg_offset, u8 id, u8 flags);
 
+struct clk *tegra_clk_register_periph_div16(const char *name,
+		const char **parent_names, int num_parents,
+		void __iomem *clk_base, u32 reg_offset, u8 id, u8 flags);
+
 /* struct clk_init_table - clock initialization table */
 struct tegra_clk_init_table {
 	unsigned int	clk_id;

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Lucas Stach

author

2014-05-14 20:47 UTC #7 lore raw

PATCH v2 8/25 clk: tegra30: register i2c clocks

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/mach-tegra/include/mach/tegra30-car.h |  2 ++
 drivers/clk/tegra/clk-tegra30.c                | 16 ++++++++++++++++
 2 files changed, 18 insertions(+)

arch/arm/mach-tegra/include/mach/tegra30-car.h +2 -0

index ce110602fca3..286a2a613a8d 100644
@@ -25,6 +25,8 @@
 #define CRC_CLK_SOURCE_MSEL_SRC_PLLM	2
 #define CRC_CLK_SOURCE_MSEL_SRC_CLKM	3
 
+#define CRC_CLK_SOURCE_I2C4		0x3c4
+
 #define CRC_RST_DEV_V_SET		0x430
 #define CRC_RST_DEV_V_MSELECT		(1 << 3)

drivers/clk/tegra/clk-tegra30.c +16 -0

index 9536288f89ac..3b508304c5d7 100644
@@ -296,6 +296,22 @@ static void tegra30_periph_init(void)
 	clks[TEGRA30_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
 			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
 			CRC_CLK_SOURCE_SDMMC4, TEGRA30_CLK_SDMMC4, 1);
+
+	clks[TEGRA30_CLK_I2C1] = tegra_clk_register_periph_div16("i2c1",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C1, TEGRA30_CLK_I2C1, 1);
+	clks[TEGRA30_CLK_I2C2] = tegra_clk_register_periph_div16("i2c2",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C2, TEGRA30_CLK_I2C2, 1);
+	clks[TEGRA30_CLK_I2C3] = tegra_clk_register_periph_div16("i2c3",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C3, TEGRA30_CLK_I2C3, 1);
+	clks[TEGRA30_CLK_I2C4] = tegra_clk_register_periph_div16("i2c4",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C4, TEGRA30_CLK_I2C4, 1);
+	clks[TEGRA30_CLK_I2C5] = tegra_clk_register_periph_div16("i2c5",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_DVC, TEGRA30_CLK_I2C5, 1);
 }
 
 static struct tegra_clk_init_table init_table[] = {

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Lucas Stach

author

2014-05-14 20:47 UTC #8 lore raw

PATCH v2 9/25 clk: tegra20: register i2c clocks

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/clk/tegra/clk-tegra20.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

drivers/clk/tegra/clk-tegra20.c +13 -0

index cb0a57181de4..5803414b9338 100644
@@ -301,6 +301,19 @@ static void tegra20_periph_init(void)
 	clks[TEGRA20_CLK_SDMMC4] = tegra_clk_register_periph("sdmmc4",
 			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
 			CRC_CLK_SOURCE_SDMMC4, TEGRA20_CLK_SDMMC4, 1);
+
+	clks[TEGRA20_CLK_I2C1] = tegra_clk_register_periph_div16("i2c1",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C1, TEGRA20_CLK_I2C1, 1);
+	clks[TEGRA20_CLK_I2C2] = tegra_clk_register_periph_div16("i2c2",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C2, TEGRA20_CLK_I2C2, 1);
+	clks[TEGRA20_CLK_I2C3] = tegra_clk_register_periph_div16("i2c3",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_I2C3, TEGRA20_CLK_I2C3, 1);
+	clks[TEGRA20_CLK_DVC] = tegra_clk_register_periph_div16("dvc",
+			mux_pllpcm_clkm, ARRAY_SIZE(mux_pllpcm_clkm), car_base,
+			CRC_CLK_SOURCE_DVC, TEGRA20_CLK_DVC, 1);
 }
 
 static struct tegra_clk_init_table init_table[] = {

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Lucas Stach

author

2014-05-14 20:47 UTC #9 lore raw

PATCH v2 10/25 i2c: add Tegra driver

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
v2:
- remove debug clk_enable
- remove xzalloc check
- remove confusing if statement

---
 drivers/i2c/busses/Kconfig     |   4 +
 drivers/i2c/busses/Makefile    |   1 +
 drivers/i2c/busses/i2c-tegra.c | 699 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 704 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-tegra.c

drivers/i2c/busses/Kconfig +4 -0

index 68d9b469e86f..370abb0c2eb1 100644
@@ -20,6 +20,10 @@ config I2C_OMAP
 	bool "OMAP I2C Master driver"
 	depends on ARCH_OMAP
 
+config I2C_TEGRA
+	bool "Tegra I2C master driver"
+	depends on ARCH_TEGRA
+
 config I2C_VERSATILE
 	tristate "ARM Versatile/Realview I2C bus support"
 	depends on ARCH_VERSATILE

drivers/i2c/busses/Makefile +1 -0

index a30f9b87e3ba..9823d1bd3600 100644
@@ -1,4 +1,5 @@
 obj-$(CONFIG_I2C_GPIO)		+= i2c-gpio.o
 obj-$(CONFIG_I2C_IMX) += i2c-imx.o
 obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
+obj-$(CONFIG_I2C_TEGRA)		+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)	+= i2c-versatile.o

drivers/i2c/busses/i2c-tegra.c new file +699 -0

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Lucas Stach

author

2014-05-14 20:47 UTC #10 lore raw

PATCH v2 11/25 ARM: tegra: beaver: activate sdmmc1 voltage rail

In reply to Lucas Stach

In order to get the SD card solt working.

Signed-off-by Lucas Stach <[email protected]>

---
One day we might move this to a regulator, but now isn't the time.

---
 arch/arm/boards/nvidia-beaver/Makefile |  1 +
 arch/arm/boards/nvidia-beaver/board.c  | 38 ++++++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/Kconfig            |  2 ++
 3 files changed, 41 insertions(+)
 create mode 100644 arch/arm/boards/nvidia-beaver/board.c

arch/arm/boards/nvidia-beaver/Makefile +1 -0

index d2d217319b34..2b6c09e2798e 100644
@@ -2,3 +2,4 @@ CFLAGS_pbl-entry.o := \
 	-mcpu=arm7tdmi -march=armv4t \
 	-fno-tree-switch-conversion -fno-jump-tables
 lwl-y += entry.o
+obj-y += board.o

arch/arm/boards/nvidia-beaver/board.c new file +38 -0

new file mode 100644
index 000000000000..e87594d5b700
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <i2c/i2c.h>
+
+static int nvidia_beaver_devices_init(void)
+{
+	struct i2c_client client;
+	u8 data;
+
+	if (!of_machine_is_compatible("nvidia,beaver"))
+		return 0;
+
+	client.adapter = i2c_get_adapter(4);
+	client.addr = 0x2d;
+
+	/* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
+	data = 0x65;
+	i2c_write_reg(&client, 0x32, &data, 1);
+
+	return 0;
+}
+device_initcall(nvidia_beaver_devices_init);

arch/arm/mach-tegra/Kconfig +2 -0

index 1bbe6ce5e1bc..5e2b4cb16dcf 100644
@@ -63,6 +63,8 @@ config MACH_TOSHIBA_AC100
 config MACH_NVIDIA_BEAVER
 	bool "NVIDIA Beaver"
 	select ARCH_TEGRA_3x_SOC
+	select I2C
+	select I2C_TEGRA
 
 endmenu

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Lucas Stach

author

2014-05-14 20:47 UTC #11 lore raw

PATCH v2 12/25 ARM: tegra: beaver: adjust pinmux to make sdmmc1 work

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/dts/tegra30-beaver.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

arch/arm/dts/tegra30-beaver.dts +10 -0

index 1110b8974966..35b4d7e43c29 100644
@@ -191,6 +191,15 @@
 						"pex_l1_clkreq_n_pdd6";
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 			};
+			sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,pull-down-strength = <46>;
+				nvidia,pull-up-strength = <42>;
+				nvidia,slew-rate-rising = <1>;
+				nvidia,slew-rate-falling = <1>;
+			};
 			sdio3 {
 				nvidia,pins = "drive_sdio3";
 				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;

@@ -325,6 +334,7 @@
 						"vi_hsync_pd7";
 				nvidia,function = "ddr";
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			ddr_up {
 				nvidia,pins =	"vi_d11_pt3";

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Lucas Stach

author

2014-05-14 20:47 UTC #12 lore raw

PATCH v2 13/25 mci: tegra: apply pad autocalibration on T30

In reply to Lucas Stach

Needed for SD cards connected to sdmmc1 or sdmmc3
to work properly.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/mci/tegra-sdmmc.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

drivers/mci/tegra-sdmmc.c +25 -0

index 0ea0b5ca4a92..634515705f04 100644
@@ -59,6 +59,14 @@
 #define TEGRA_SDMMC_INT_SIG_EN				0x038
 #define  TEGRA_SDMMC_INT_SIG_EN_XFER_COMPLETE		(1 << 1)
 
+#define TEGRA_SDMMC_SDMEMCOMPPADCTRL			0x1e0
+#define  TEGRA_SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_SHIFT	0
+
+#define TEGRA_SDMMC_AUTO_CAL_CONFIG			0x1e4
+#define  TEGRA_SDMMC_AUTO_CAL_CONFIG_PU_OFFSET_SHIFT	0
+#define  TEGRA_SDMMC_AUTO_CAL_CONFIG_PD_OFFSET_SHIFT	8
+#define  TEGRA_SDMMC_AUTO_CAL_CONFIG_ENABLE		(1 << 29)
+
 struct tegra_sdmmc_host {
 	struct mci_host		mci;
 	void __iomem		*regs;

@@ -333,6 +341,23 @@ static int tegra_sdmmc_init(struct mci_host *mci, struct device_d *dev)
 	val |= TEGRA_SDMMC_PWR_CNTL_33_V | TEGRA_SDMMC_PWR_CNTL_SD_BUS;
 	writel(val, regs + TEGRA_SDMMC_PWR_CNTL);
 
+	/* sdmmc1 and sdmmc3 on T30 need a bit of padctrl init */
+	if (of_device_is_compatible(mci->hw_dev->device_node,
+			"nvidia,tegra30-sdhci") &&
+			((u32)regs == 0x78000000 || (u32)regs == 78000400)) {
+		val = readl(regs + TEGRA_SDMMC_SDMEMCOMPPADCTRL);
+		val &= 0xfffffff0;
+		val |= 0x7 << TEGRA_SDMMC_SDMEMCOMPPADCTRL_VREF_SEL_SHIFT;
+		writel(val, regs + TEGRA_SDMMC_SDMEMCOMPPADCTRL);
+
+		val = readl(regs + TEGRA_SDMMC_AUTO_CAL_CONFIG);
+		val &= 0xffff0000;
+		val |= (0x62 << TEGRA_SDMMC_AUTO_CAL_CONFIG_PU_OFFSET_SHIFT) |
+		       (0x70 << TEGRA_SDMMC_AUTO_CAL_CONFIG_PD_OFFSET_SHIFT) |
+		       TEGRA_SDMMC_AUTO_CAL_CONFIG_ENABLE;
+		writel(val, regs + TEGRA_SDMMC_AUTO_CAL_CONFIG);
+	}
+
 	/* setup signaling */
 	writel(0xffffffff, regs + TEGRA_SDMMC_INT_STAT_EN);
 	writel(0xffffffff, regs + TEGRA_SDMMC_INT_SIG_EN);

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Lucas Stach

author

2014-05-14 20:47 UTC #13 lore raw

PATCH v2 14/25 mci: tegra: don't set 8bit mode unconditionally

In reply to Lucas Stach

Those flags should be set from the DT parsing code.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/mci/tegra-sdmmc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

drivers/mci/tegra-sdmmc.c +1 -2

index 634515705f04..62cf7305d318 100644
@@ -470,8 +470,7 @@ static int tegra_sdmmc_probe(struct device_d *dev)
 	mci->set_ios = tegra_sdmmc_set_ios;
 	mci->send_cmd = tegra_sdmmc_send_cmd;
 	mci->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	mci->host_caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-	                  MMC_CAP_MMC_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED_52MHZ |
+	mci->host_caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED_52MHZ |
 	                  MMC_CAP_SD_HIGHSPEED;
 
 	dev->priv = host;

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Lucas Stach

author

2014-05-14 20:47 UTC #14 lore raw

PATCH v2 15/25 pinctrl: tegra30: parse drive groups

In reply to Lucas Stach

These are special groups to configure pad properties such as drive strength and slew rate for a group of pads.

Signed-off-by Lucas Stach <[email protected]>

---
 drivers/pinctrl/pinctrl-tegra30.c | 159 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 158 insertions(+), 1 deletion(-)

drivers/pinctrl/pinctrl-tegra30.c +158 -1

index 032377fe8cd2..888bf04b0409 100644
@@ -37,6 +37,23 @@ struct tegra30_pingroup {
 	u16 reg;
 };
 
+struct tegra30_drive_pingroup {
+	const char *name;
+	u16 reg;
+	u32 hsm_bit:5;
+	u32 schmitt_bit:5;
+	u32 lpmd_bit:5;
+	u32 drvdn_bit:5;
+	u32 drvup_bit:5;
+	u32 slwr_bit:5;
+	u32 slwf_bit:5;
+	u32 drvtype_bit:5;
+	u32 drvdn_width:6;
+	u32 drvup_width:6;
+	u32 slwr_width:6;
+	u32 slwf_width:6;
+};
+
 #define PG(pg_name, f0, f1, f2, f3, offset)		\
 	{						\
 		.name = #pg_name,			\

@@ -44,6 +61,25 @@ struct tegra30_pingroup {
 		.reg = offset				\
 	}
 
+#define DRV_PG(pg_name, r, hsm_b, schmitt_b, lpmd_b,	\
+               drvdn_b, drvdn_w, drvup_b, drvup_w,	\
+               slwr_b, slwr_w, slwf_b, slwf_w)		\
+	{						\
+		.name = "drive_" #pg_name,		\
+		.reg = r - 0x868,			\
+		.hsm_bit = hsm_b,			\
+		.schmitt_bit = schmitt_b,		\
+		.lpmd_bit = lpmd_b,			\
+		.drvdn_bit = drvdn_b,			\
+		.drvdn_width = drvdn_w,			\
+		.drvup_bit = drvup_b,			\
+		.drvup_width = drvup_w,			\
+		.slwr_bit = slwr_b,			\
+		.slwr_width = slwr_w,			\
+		.slwf_bit = slwf_b,			\
+		.slwf_width = slwf_w,			\
+	}
+
 static const struct tegra30_pingroup tegra30_groups[] = {
 	/* name,                 f0,        f1,        f2,        f3,           reg  */
 	PG(clk_32k_out_pa0,      blink,     rsvd2,     rsvd3,     rsvd4,        0x31c),

@@ -297,6 +333,122 @@ static const struct tegra30_pingroup tegra30_groups[] = {
 	PG(pwr_int_n,            pwr_int_n, rsvd2,     rsvd3,     rsvd4,        0x32c),
 };
 
+static const struct tegra30_drive_pingroup tegra30_drive_groups[] = {
+	DRV_PG(ao1,   0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(ao2,   0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(at1,   0x870,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
+	DRV_PG(at2,   0x874,  2,  3,  4,  14,  5,  19,  5,  24,  2,  28,  2),
+	DRV_PG(at3,   0x878,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(at4,   0x87c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(at5,   0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(cdev1, 0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(cdev2, 0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(cec,   0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(crt,   0x8f8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(csus,  0x88c, -1, -1, -1,  12,  5,  19,  5,  24,  4,  28,  4),
+	DRV_PG(dap1,  0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap2,  0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap3,  0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dap4,  0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dbg,   0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(ddc,   0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(dev3,  0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(gma,   0x900, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
+	DRV_PG(gmb,   0x904, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
+	DRV_PG(gmc,   0x908, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
+	DRV_PG(gmd,   0x90c, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
+	DRV_PG(gme,   0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gmf,   0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gmg,   0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gmh,   0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2),
+	DRV_PG(gpv,   0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(lcd1,  0x8a4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(lcd2,  0x8a8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(owr,   0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(sdio1, 0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(sdio2, 0x8ac,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(sdio3, 0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2),
+	DRV_PG(spi,   0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uaa,   0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uab,   0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uart2, 0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uart3, 0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(uda,   0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2),
+	DRV_PG(vi1,   0x8c8, -1, -1, -1,  14,  5,  19,  5,  24,  4,  28,  4),
+};
+
+static int pinctrl_tegra30_set_drvstate(struct pinctrl_tegra30 *ctrl,
+                                        struct device_node *np)
+{
+	const char *pins = NULL;
+	const struct tegra30_drive_pingroup *group = NULL;
+	int hsm = -1, schmitt = -1, pds = -1, pus = -1, srr = -1, srf = -1;
+	int i;
+	u32 __iomem *regaddr;
+	u32 val;
+
+	if (of_property_read_string(np, "nvidia,pins", &pins))
+		return 0;
+
+	for (i = 0; i < ARRAY_SIZE(tegra30_drive_groups); i++) {
+		if (!strcmp(pins, tegra30_drive_groups[i].name)) {
+			group = &tegra30_drive_groups[i];
+			break;
+		}
+	}
+	/* if no matching drivegroup is found */
+	if (i == ARRAY_SIZE(tegra30_groups))
+		return 0;
+
+	regaddr = ctrl->regs.ctrl + (group->reg >> 2);
+
+	of_property_read_u32_array(np, "nvidia,high-speed-mode", &hsm, 1);
+	of_property_read_u32_array(np, "nvidia,schmitt", &schmitt, 1);
+	of_property_read_u32_array(np, "nvidia,pull-down-strength", &pds, 1);
+	of_property_read_u32_array(np, "nvidia,pull-up-strength", &pus, 1);
+	of_property_read_u32_array(np, "nvidia,slew-rate-rising", &srr, 1);
+	of_property_read_u32_array(np, "nvidia,slew-rate-falling", &srf, 1);
+
+	if (hsm >= 0) {
+		val = readl(regaddr);
+		val &= ~(0x1 << group->hsm_bit);
+		val |= hsm << group->hsm_bit;
+		writel(val, regaddr);
+	}
+	if (schmitt >= 0) {
+		val = readl(regaddr);
+		val &= ~(0x1 << group->schmitt_bit);
+		val |= hsm << group->schmitt_bit;
+		writel(val, regaddr);
+	}
+	if (pds >= 0) {
+		val = readl(regaddr);
+		val &= ~(((1 << group->drvdn_width) - 1) << group->drvdn_bit);
+		val |= hsm << group->drvdn_bit;
+		writel(val, regaddr);
+	}
+	if (pus >= 0) {
+		val = readl(regaddr);
+		val &= ~(((1 << group->drvup_width) - 1) << group->drvup_bit);
+		val |= hsm << group->drvup_bit;
+		writel(val, regaddr);
+	}
+	if (srr >= 0) {
+		val = readl(regaddr);
+		val &= ~(((1 << group->slwr_width) - 1) << group->slwr_bit);
+		val |= hsm << group->slwr_bit;
+		writel(val, regaddr);
+	}
+	if (srf >= 0) {
+		val = readl(regaddr);
+		val &= ~(((1 << group->slwf_width) - 1) << group->slwf_bit);
+		val |= hsm << group->slwf_bit;
+		writel(val, regaddr);
+	}
+
+	return 1;
+}
+
 static void pinctrl_tegra30_set_func(struct pinctrl_tegra30 *ctrl,
 				     u32 reg, int func)
 {

@@ -405,8 +557,13 @@ static int pinctrl_tegra30_set_state(struct pinctrl_device *pdev,
 				break;
 			}
 		}
-		/* if no matching pingroup is found bail out */
+		/* if no matching pingroup is found */
 		if (j == ARRAY_SIZE(tegra30_groups)) {
+			/* see if we can find a drivegroup */
+			if (pinctrl_tegra30_set_drvstate(ctrl, np))
+				continue;
+
+			/* nothing matching found, warn and bail out */
 			dev_warn(ctrl->pinctrl.dev,
 				 "invalid pingroup %s referenced in node %s\n",
 				 pins, np->name);

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Lucas Stach

author

2014-05-14 20:49 UTC #15 lore raw

PATCH v2 16/25 scripts: tegra: import cbootimage

In reply to Lucas Stach

Needed to built the BCTs and bootable images.

Version 1.2 from https://github.com/NVIDIA/cbootimage.git

Signed-off-by Lucas Stach <[email protected]>

---
 scripts/Makefile                             |    1 +
 scripts/tegra/Makefile                       |   22 +
 scripts/tegra/aes_ref.c                      |  326 ++++++++
 scripts/tegra/bct_dump.c                     |  296 +++++++
 scripts/tegra/cbootimage.c                   |  247 ++++++
 scripts/tegra/cbootimage.h                   |  108 +++
 scripts/tegra/context.c                      |   42 +
 scripts/tegra/context.h                      |   28 +
 scripts/tegra/crypto.c                       |  299 +++++++
 scripts/tegra/crypto.h                       |   47 ++
 scripts/tegra/data_layout.c                  |  898 +++++++++++++++++++++
 scripts/tegra/data_layout.h                  |   55 ++
 scripts/tegra/nvaes_ref.h                    |   35 +
 scripts/tegra/parse.c                        |  803 +++++++++++++++++++
 scripts/tegra/parse.h                        |  923 +++++++++++++++++++++
 scripts/tegra/set.c                          |  206 +++++
 scripts/tegra/set.h                          |   49 ++
 scripts/tegra/t114/nvbctlib_t114.c           | 1103 +++++++++++++++++++++++++
 scripts/tegra/t114/nvboot_bct_t114.h         |  363 +++++++++
 scripts/tegra/t114/nvboot_sdram_param_t114.h |  806 +++++++++++++++++++
 scripts/tegra/t114/parse_t114.c              |  430 ++++++++++
 scripts/tegra/t124/nvbctlib_t124.c           | 1104 ++++++++++++++++++++++++++
 scripts/tegra/t124/nvboot_bct_t124.h         |  359 +++++++++
 scripts/tegra/t124/nvboot_sdram_param_t124.h |  803 +++++++++++++++++++
 scripts/tegra/t124/parse_t124.c              |  429 ++++++++++
 scripts/tegra/t20/nvbctlib_t20.c             |  684 ++++++++++++++++
 scripts/tegra/t20/nvboot_bct_t20.h           |  316 ++++++++
 scripts/tegra/t20/nvboot_sdram_param_t20.h   |  363 +++++++++
 scripts/tegra/t20/parse_t20.c                |  251 ++++++
 scripts/tegra/t30/nvbctlib_t30.c             |  891 +++++++++++++++++++++
 scripts/tegra/t30/nvboot_bct_t30.h           |  379 +++++++++
 scripts/tegra/t30/nvboot_sdram_param_t30.h   |  568 +++++++++++++
 scripts/tegra/t30/parse_t30.c                |  360 +++++++++
 33 files changed, 13594 insertions(+)
 create mode 100644 scripts/tegra/Makefile
 create mode 100644 scripts/tegra/aes_ref.c
 create mode 100644 scripts/tegra/bct_dump.c
 create mode 100644 scripts/tegra/cbootimage.c
 create mode 100644 scripts/tegra/cbootimage.h
 create mode 100644 scripts/tegra/context.c
 create mode 100644 scripts/tegra/context.h
 create mode 100644 scripts/tegra/crypto.c
 create mode 100644 scripts/tegra/crypto.h
 create mode 100644 scripts/tegra/data_layout.c
 create mode 100644 scripts/tegra/data_layout.h
 create mode 100644 scripts/tegra/nvaes_ref.h
 create mode 100644 scripts/tegra/parse.c
 create mode 100644 scripts/tegra/parse.h
 create mode 100644 scripts/tegra/set.c
 create mode 100644 scripts/tegra/set.h
 create mode 100644 scripts/tegra/t114/nvbctlib_t114.c
 create mode 100644 scripts/tegra/t114/nvboot_bct_t114.h
 create mode 100644 scripts/tegra/t114/nvboot_sdram_param_t114.h
 create mode 100644 scripts/tegra/t114/parse_t114.c
 create mode 100644 scripts/tegra/t124/nvbctlib_t124.c
 create mode 100644 scripts/tegra/t124/nvboot_bct_t124.h
 create mode 100644 scripts/tegra/t124/nvboot_sdram_param_t124.h
 create mode 100644 scripts/tegra/t124/parse_t124.c
 create mode 100644 scripts/tegra/t20/nvbctlib_t20.c
 create mode 100644 scripts/tegra/t20/nvboot_bct_t20.h
 create mode 100644 scripts/tegra/t20/nvboot_sdram_param_t20.h
 create mode 100644 scripts/tegra/t20/parse_t20.c
 create mode 100644 scripts/tegra/t30/nvbctlib_t30.c
 create mode 100644 scripts/tegra/t30/nvboot_bct_t30.h
 create mode 100644 scripts/tegra/t30/nvboot_sdram_param_t30.h
 create mode 100644 scripts/tegra/t30/parse_t30.c

scripts/Makefile +1 -0

index 3908c1dcb953..c02c7f3bd3d1 100644
@@ -24,6 +24,7 @@ subdir-$(CONFIG_OMAP4_USBBOOT)	+= omap4_usbboot
 subdir-$(CONFIG_ARCH_IMX)	+= imx
 subdir-$(CONFIG_X86)		+= setupmbr
 subdir-$(CONFIG_DTC)		+= dtc
+subdir-$(CONFIG_ARCH_TEGRA)	+= tegra
 
 targetprogs-$(CONFIG_BAREBOXENV_TARGET) += bareboxenv-target
 targetprogs-$(CONFIG_KERNEL_INSTALL_TARGET) += kernel-install-target

scripts/tegra/Makefile new file +22 -0

new file mode 100644
index 000000000000..99aef3fa05c6
@@ -0,0 +1,22 @@
+hostprogs-$(CONFIG_ARCH_TEGRA) += cbootimage
+
+always          := $(hostprogs-y)
+
+HOSTLOADLIBES_cbootimage  = '-lm'
+
+cbootimage-objs := \
+	cbootimage.o \
+	data_layout.o \
+	set.o \
+	crypto.o \
+	aes_ref.o \
+	context.o \
+	parse.o \
+	t124/parse_t124.o \
+	t114/parse_t114.o \
+	t30/parse_t30.o \
+	t20/parse_t20.o \
+	t124/nvbctlib_t124.o \
+	t114/nvbctlib_t114.o \
+	t30/nvbctlib_t30.o \
+	t20/nvbctlib_t20.o

scripts/tegra/aes_ref.c new file +326 -0

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scripts/tegra/bct_dump.c new file +296 -0

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scripts/tegra/cbootimage.c new file +247 -0

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scripts/tegra/cbootimage.h new file +108 -0

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scripts/tegra/context.c new file +42 -0

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scripts/tegra/context.h new file +28 -0

new file mode 100644
index 000000000000..6e724718b640
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#ifndef INCLUDED_CONTEXT_H
+#define INCLUDED_CONTEXT_H
+
+#include "cbootimage.h"
+
+int init_context(build_image_context *context);
+void cleanup_context(build_image_context *context);
+
+#endif /* #ifndef INCLUDED_CONTEXT_H */

scripts/tegra/crypto.c new file +299 -0

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scripts/tegra/crypto.h new file +47 -0

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scripts/tegra/data_layout.c new file +898 -0

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scripts/tegra/data_layout.h new file +55 -0

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scripts/tegra/nvaes_ref.h new file +35 -0

new file mode 100644
index 000000000000..76bd6c3a96ab
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#include "cbootimage.h"
+#include "string.h"
+
+#ifndef INCLUDED_NVAES_REF_H
+#define INCLUDED_NVAES_REF_H
+
+#define NVAES_STATECOLS	4
+#define NVAES_KEYCOLS	4
+#define NVAES_ROUNDS	10
+
+void nv_aes_expand_key(u_int8_t *key, u_int8_t *expkey);
+void nv_aes_encrypt(u_int8_t *in,
+		u_int8_t *expkey,
+		u_int8_t *out);
+
+#endif // INCLUDED_NVAES_REF_H

scripts/tegra/parse.c new file +803 -0

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scripts/tegra/parse.h new file +923 -0

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scripts/tegra/set.c new file +206 -0

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scripts/tegra/set.h new file +49 -0

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scripts/tegra/t114/nvbctlib_t114.c new file +1103 -0

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scripts/tegra/t114/nvboot_bct_t114.h new file +363 -0

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scripts/tegra/t114/nvboot_sdram_param_t114.h new file +806 -0

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scripts/tegra/t114/parse_t114.c new file +430 -0

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scripts/tegra/t124/nvbctlib_t124.c new file +1104 -0

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scripts/tegra/t124/nvboot_bct_t124.h new file +359 -0

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scripts/tegra/t124/nvboot_sdram_param_t124.h new file +803 -0

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scripts/tegra/t124/parse_t124.c new file +429 -0

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scripts/tegra/t20/nvbctlib_t20.c new file +684 -0

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scripts/tegra/t20/nvboot_bct_t20.h new file +316 -0

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scripts/tegra/t20/nvboot_sdram_param_t20.h new file +363 -0

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scripts/tegra/t20/parse_t20.c new file +251 -0

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scripts/tegra/t30/nvbctlib_t30.c new file +891 -0

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scripts/tegra/t30/nvboot_bct_t30.h new file +379 -0

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scripts/tegra/t30/nvboot_sdram_param_t30.h new file +568 -0

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scripts/tegra/t30/parse_t30.c new file +360 -0

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Lucas Stach

author

2014-05-14 20:47 UTC #16 lore raw

PATCH v2 17/25 tegra: cbootimage: remove noisy output

In reply to Lucas Stach

Our build is quiet by default, so don't allow cbootimage to spam our logs.

Signed-off-by Lucas Stach <[email protected]>

---
 scripts/tegra/cbootimage.c | 5 -----
 1 file changed, 5 deletions(-)

scripts/tegra/cbootimage.c +0 -5

index 1332c5f118b5..51422d1efa69 100644
@@ -217,8 +217,6 @@ main(int argc, char *argv[])
 
 		fwrite(context.bct, 1, context.bct_size,
 			context.raw_file);
-		printf("New BCT file %s has been successfully generated!\n",
-			context.image_filename);
 		goto fail;
 	}

@@ -232,9 +230,6 @@ main(int argc, char *argv[])
 	/* The image hasn't been written yet. */
 	if (write_image_file(&context) != 0)
 		printf("Error writing image file.\n");
-	else
-		printf("Image file %s has been successfully generated!\n",
-				context.image_filename);
 
  fail:
 	/* Close the file(s). */

Signature · 7 lines

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Lucas Stach

author

2014-05-14 20:47 UTC #17 lore raw

PATCH v2 18/25 Makefile.lib: add rule to built Tegra BCTs

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 .gitignore           | 1 +
 scripts/Makefile.lib | 6 ++++++
 2 files changed, 7 insertions(+)

.gitignore +1 -0

index d49049124846..5555e1544e7e 100644
@@ -20,6 +20,7 @@
 *.elf
 *.mcp
 *.orig
+*.bct
 *.dcd
 *.dcd.S
 *.bbenv

scripts/Makefile.lib +6 -0

index d4306cbe7820..08518704fe40 100644
@@ -400,3 +400,9 @@ quiet_cmd_imx_image = IMX-IMG $@
 
 quiet_cmd_kwb_image = KWB     $@
       cmd_kwb_image = scripts/kwbimage -p $< $(OPTS_$(@F)) -o $@
+
+quiet_cmd_cboot_bct = BCT     $@
+      cmd_cboot_bct = $(objtree)/scripts/tegra/cbootimage -gbct -s $(soc) $< $@
+
+$(obj)/%.bct: $(obj)/%.bct.cfg
+	$(call cmd,cboot_bct)

Signature · 7 lines

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_______________________________________________
barebox mailing list
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Lucas Stach

author

2014-05-14 20:48 UTC #18 lore raw

PATCH v2 19/25 images: add Tegra20 image build rules

In reply to Lucas Stach

Allows to build persistent images for the Tegra20
line of SoCs.

Signed-off-by Lucas Stach <[email protected]>

---
 images/.gitignore     | 2 ++
 images/Makefile       | 2 +-
 images/Makefile.tegra | 8 ++++++++
 3 files changed, 11 insertions(+), 1 deletion(-)

images/.gitignore +2 -0

index 1f601e730f1d..5f6f0b2ab2bb 100644
@@ -8,6 +8,8 @@
 *.kwbimg
 *.kwbuartimg
 *.socfpgaimg
+*.t20img
+*.t20img.cfg
 pbl.lds
 barebox.x
 barebox.z

images/Makefile +1 -1

index 5509a4cf8003..1ad7dace854d 100644
@@ -117,5 +117,5 @@ images: $(addprefix $(obj)/, $(image-y)) FORCE
 	@for i in $(image-y); do echo $$i; done
 
 clean-files := *.pbl *.pblb *.pblx *.map start_*.imximg *.img barebox.z start_*.kwbimg \
-	start_*.kwbuartimg *.socfpgaimg *.mlo
+	start_*.kwbuartimg *.socfpgaimg *.mlo *.t20img *.t20img.cfg
 clean-files += pbl.lds

images/Makefile.tegra +8 -0

index c957599958ca..6c9a70529eac 100644
@@ -1,6 +1,14 @@
 #
 # barebox image generation Makefile for Tegra images
 #
+quiet_cmd_tegra20_image = T20IMG  $@
+      cmd_tegra20_image = echo "Version = 0x00020001;Bctcopy = 1; \
+                                Bctfile = $(BCT_$(@F)); \
+                                BootLoader = $(subst .t20img,,$@),0x00108000,0x00108000,Complete;" \
+                                > [email protected]; \
+                          $(objtree)/scripts/tegra/cbootimage -s tegra20 [email protected] $@
+$(obj)/%.t20img: $(obj)/% FORCE
+	$(call if_changed,tegra20_image)
 
 board = $(srctree)/arch/$(ARCH)/boards

Signature · 7 lines

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_______________________________________________
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Lucas Stach

author

2014-05-14 20:48 UTC #19 lore raw

PATCH v2 20/25 images: add Tegra30 image build rules

In reply to Lucas Stach

Allows to build persistent images for the Tegra30
line of SoCs.

Signed-off-by Lucas Stach <[email protected]>

---
 images/.gitignore     | 2 ++
 images/Makefile       | 3 ++-
 images/Makefile.tegra | 9 +++++++++
 3 files changed, 13 insertions(+), 1 deletion(-)

images/.gitignore +2 -0

index 5f6f0b2ab2bb..42991af25c4b 100644
@@ -10,6 +10,8 @@
 *.socfpgaimg
 *.t20img
 *.t20img.cfg
+*.t30img
+*.t30img.cfg
 pbl.lds
 barebox.x
 barebox.z

images/Makefile +2 -1

index 1ad7dace854d..b050dbf312b8 100644
@@ -117,5 +117,6 @@ images: $(addprefix $(obj)/, $(image-y)) FORCE
 	@for i in $(image-y); do echo $$i; done
 
 clean-files := *.pbl *.pblb *.pblx *.map start_*.imximg *.img barebox.z start_*.kwbimg \
-	start_*.kwbuartimg *.socfpgaimg *.mlo *.t20img *.t20img.cfg
+	start_*.kwbuartimg *.socfpgaimg *.mlo *.t20img *.t20img.cfg *.t30img \
+	*.t30img.cfg
 clean-files += pbl.lds

images/Makefile.tegra +9 -0

index 6c9a70529eac..7dc44a2d899a 100644
@@ -10,6 +10,15 @@ quiet_cmd_tegra20_image = T20IMG  $@
 $(obj)/%.t20img: $(obj)/% FORCE
 	$(call if_changed,tegra20_image)
 
+quiet_cmd_tegra30_image = T30IMG  $@
+      cmd_tegra30_image = echo "Version = 0x00030001;Bctcopy = 1; \
+                                Bctfile = $(BCT_$(@F)); \
+                                BootLoader = $(subst .t30img,,$@),0x80108000,0x80108000,Complete;" \
+                                > [email protected]; \
+                          $(objtree)/scripts/tegra/cbootimage -s tegra30 [email protected] $@
+$(obj)/%.t30img: $(obj)/% FORCE
+	$(call if_changed,tegra30_image)
+
 board = $(srctree)/arch/$(ARCH)/boards
 
 # ----------------------- Tegra20 based boards ---------------------------

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Lucas Stach

author

2014-05-14 20:48 UTC #20 lore raw

PATCH v2 21/25 ARM: boards: colibri t20: import BCT cfgs

In reply to Lucas Stach

From https://github.com/NVIDIA/cbootimage-configs.git

There are a bunch of different versions and boot options for this board. Import BCTs for all of them.

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/boards/toradex-colibri-t20/Makefile       |   4 +
 .../colibri-t20_256_hsmmc.bct.cfg                  | 451 ++++++++++++++++++++
 .../colibri-t20_256_v11_nand.bct.cfg               | 459 +++++++++++++++++++++
 .../colibri-t20_256_v12_nand.bct.cfg               | 459 +++++++++++++++++++++
 .../colibri-t20_512_hsmmc.bct.cfg                  | 451 ++++++++++++++++++++
 .../colibri-t20_512_v11_nand.bct.cfg               | 459 +++++++++++++++++++++
 .../colibri-t20_512_v12_nand.bct.cfg               | 459 +++++++++++++++++++++
 7 files changed, 2742 insertions(+)
 create mode 100644 arch/arm/boards/toradex-colibri-t20/colibri-t20_256_hsmmc.bct.cfg
 create mode 100644 arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v11_nand.bct.cfg
 create mode 100644 arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v12_nand.bct.cfg
 create mode 100644 arch/arm/boards/toradex-colibri-t20/colibri-t20_512_hsmmc.bct.cfg
 create mode 100644 arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v11_nand.bct.cfg
 create mode 100644 arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v12_nand.bct.cfg

arch/arm/boards/toradex-colibri-t20/Makefile +4 -0

index d2d217319b34..1f767328fac4 100644
@@ -1,4 +1,8 @@
 CFLAGS_pbl-entry.o := \
 	-mcpu=arm7tdmi -march=armv4t \
 	-fno-tree-switch-conversion -fno-jump-tables
+soc := tegra20
 lwl-y += entry.o
+extra-y += colibri-t20_256_hsmmc.bct colibri-t20_256_v11_nand.bct \
+           colibri-t20_256_v12_nand.bct colibri-t20_512_hsmmc.bct \
+           colibri-t20_512_v11_nand.bct colibri-t20_512_v12_nand.bct
\ No newline at end of file

arch/arm/boards/toradex-colibri-t20/colibri-t20_256_hsmmc.bct.cfg new file +451 -0

451 lines not on this page · raw message

arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v11_nand.bct.cfg new file +459 -0

459 lines not on this page · raw message

arch/arm/boards/toradex-colibri-t20/colibri-t20_256_v12_nand.bct.cfg new file +459 -0

459 lines not on this page · raw message

arch/arm/boards/toradex-colibri-t20/colibri-t20_512_hsmmc.bct.cfg new file +451 -0

451 lines not on this page · raw message

arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v11_nand.bct.cfg new file +459 -0

459 lines not on this page · raw message

arch/arm/boards/toradex-colibri-t20/colibri-t20_512_v12_nand.bct.cfg new file +459 -0

459 lines not on this page · raw message

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Lucas Stach

author

2014-05-14 20:47 UTC #21 lore raw

PATCH v2 22/25 images: tegra: build all Toradex Colibri images

In reply to Lucas Stach

Six images for the the 256MB and 512MB version with different boot sources (MMC, NAND [different chips on pre-/production modules]).

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/boards/toradex-colibri-t20/entry.c | 42 ++++++++++++++++++++++++++++-
 images/Makefile.tegra                       | 40 ++++++++++++++++++++++++---
 2 files changed, 78 insertions(+), 4 deletions(-)

arch/arm/boards/toradex-colibri-t20/entry.c +41 -1

index 886613f13d8c..695862cfd3e7 100644
@@ -22,7 +22,7 @@
 
 extern char __dtb_tegra20_colibri_iris_start[];
 
-ENTRY_FUNCTION(start_toradex_colibri_t20_iris, r0, r1, r2)
+static void common_toradex_colibri_t20_iris_start(void)
 {
 	uint32_t fdt;

@@ -32,3 +32,43 @@ ENTRY_FUNCTION(start_toradex_colibri_t20_iris, r0, r1, r2)
 
 	tegra_avp_reset_vector(fdt);
 }
+
+ENTRY_FUNCTION(start_colibri_t20_256_usbload, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_256_hsmmc, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_256_v11_nand, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_256_v12_nand, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_usbload, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_hsmmc, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_v11_nand, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}
+
+ENTRY_FUNCTION(start_colibri_t20_512_v12_nand, r0, r1, r2)
+{
+	common_toradex_colibri_t20_iris_start();
+}

images/Makefile.tegra +37 -3

index 7dc44a2d899a..75efc6830211 100644
@@ -26,9 +26,43 @@ pblx-$(CONFIG_MACH_TOSHIBA_AC100) += start_toshiba_ac100
 FILE_barebox-tegra20-toshiba-ac100.img = start_toshiba_ac100.pblx
 image-$(CONFIG_MACH_TOSHIBA_AC100) += barebox-tegra20-toshiba-ac100.img
 
-pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_toradex_colibri_t20_iris
-FILE_barebox-tegra20-toradex-colibri-t20-iris.img = start_toradex_colibri_t20_iris.pblx
-image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-iris.img
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_256_usbload
+FILE_barebox-tegra20-toradex-colibri-t20-256-usbloader-iris.img = start_colibri_t20_256_usbload.pblx
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-256-usbloader-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_256_hsmmc
+BCT_start_colibri_t20_256_hsmmc.pblx.t20img = $(board)/toradex-colibri-t20/colibri-t20_256_hsmmc.bct
+FILE_barebox-tegra20-toradex-colibri-t20-256-hsmmc-iris.img = start_colibri_t20_256_hsmmc.pblx.t20img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-256-hsmmc-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_256_v11_nand
+BCT_start_colibri_t20_256_v11_nand.pblx.t20img = $(board)/toradex-colibri-t20/colibri-t20_256_v11_nand.bct
+FILE_barebox-tegra20-toradex-colibri-t20-256-v11-nand-iris.img = start_colibri_t20_256_v11_nand.pblx.t20img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-256-v11-nand-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_256_v12_nand
+BCT_start_colibri_t20_256_v12_nand.pblx.t20img = $(board)/toradex-colibri-t20/colibri-t20_256_v12_nand.bct
+FILE_barebox-tegra20-toradex-colibri-t20-256-v12-nand-iris.img = start_colibri_t20_256_v12_nand.pblx.t20img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-256-v12-nand-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_512_usbload
+FILE_barebox-tegra20-toradex-colibri-t20-512-usbloader-iris.img = start_colibri_t20_512_usbload.pblx
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-512-usbloader-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_512_hsmmc
+BCT_start_colibri_t20_512_hsmmc.pblx.t20img = $(board)/toradex-colibri-t20/colibri-t20_512_hsmmc.bct
+FILE_barebox-tegra20-toradex-colibri-t20-512-hsmmc-iris.img = start_colibri_t20_512_hsmmc.pblx.t20img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-512-hsmmc-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_512_v11_nand
+BCT_start_colibri_t20_512_v11_nand.pblx.t20img = $(board)/toradex-colibri-t20/colibri-t20_512_v11_nand.bct
+FILE_barebox-tegra20-toradex-colibri-t20-512-v11-nand-iris.img = start_colibri_t20_512_v11_nand.pblx.t20img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-512-v11-nand-iris.img
+
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_512_v12_nand
+BCT_start_colibri_t20_512_v12_nand.pblx.t20img = $(board)/toradex-colibri-t20/colibri-t20_512_v12_nand.bct
+FILE_barebox-tegra20-toradex-colibri-t20-512-v12-nand-iris.img = start_colibri_t20_512_v12_nand.pblx.t20img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-512-v12-nand-iris.img
 
 # ----------------------- Tegra30 based boards ---------------------------
 pblx-$(CONFIG_MACH_NVIDIA_BEAVER) += start_nvidia_beaver

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Lucas Stach

author

2014-05-14 20:48 UTC #22 lore raw

PATCH v2 23/25 ARM: boards: beaver: import BCT cfg

In reply to Lucas Stach

From https://github.com/NVIDIA/cbootimage-configs.git

Signed-off-by Lucas Stach <[email protected]>

---
 arch/arm/boards/nvidia-beaver/Makefile             |   2 +
 .../boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg   | 819 +++++++++++++++++++++
 2 files changed, 821 insertions(+)
 create mode 100644 arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg

arch/arm/boards/nvidia-beaver/Makefile +2 -0

index 2b6c09e2798e..7ade54e8546d 100644
@@ -1,5 +1,7 @@
 CFLAGS_pbl-entry.o := \
 	-mcpu=arm7tdmi -march=armv4t \
 	-fno-tree-switch-conversion -fno-jump-tables
+soc := tegra30
 lwl-y += entry.o
 obj-y += board.o
+extra-y += beaver-2gb-emmc.bct

arch/arm/boards/nvidia-beaver/beaver-2gb-emmc.bct.cfg new file +819 -0

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Lucas Stach

author

2014-05-14 20:48 UTC #23 lore raw

PATCH v2 24/25 images: tegra: build NVidia Beaver image

In reply to Lucas Stach

Signed-off-by Lucas Stach <[email protected]>

---
 images/Makefile.tegra | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

images/Makefile.tegra +7 -2

index 75efc6830211..2828353b5609 100644
@@ -66,5 +66,10 @@ image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-
 
 # ----------------------- Tegra30 based boards ---------------------------
 pblx-$(CONFIG_MACH_NVIDIA_BEAVER) += start_nvidia_beaver
-FILE_barebox-tegra30-nvidia-beaver.img = start_nvidia_beaver.pblx
-image-$(CONFIG_MACH_NVIDIA_BEAVER) += barebox-tegra30-nvidia-beaver.img
+FILE_barebox-tegra30-nvidia-beaver-usbloader.img = start_nvidia_beaver.pblx
+image-$(CONFIG_MACH_NVIDIA_BEAVER) += barebox-tegra30-nvidia-beaver-usbloader.img
+
+pblx-$(CONFIG_MACH_NVIDIA_BEAVER) += start_nvidia_beaver
+BCT_start_nvidia_beaver.pblx.t30img = $(board)/nvidia-beaver/beaver-2gb-emmc.bct
+FILE_barebox-tegra30-nvidia-beaver-emmc.img = start_nvidia_beaver.pblx.t30img
+image-$(CONFIG_MACH_NVIDIA_BEAVER) += barebox-tegra30-nvidia-beaver-emmc.img

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Lucas Stach

author

2014-05-14 20:47 UTC #24 lore raw

PATCH v2 25/25 images: tegra: rename ac100 image

In reply to Lucas Stach

To make it clear that this image is only suitable
for loading via usbloader. We can't do anything
about this, as there is no upstream BCT available
for AC100.

Signed-off-by Lucas Stach <[email protected]>

---
 images/Makefile.tegra | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

images/Makefile.tegra +2 -2

index 2828353b5609..f22c2d308b44 100644
@@ -23,8 +23,8 @@ board = $(srctree)/arch/$(ARCH)/boards
 
 # ----------------------- Tegra20 based boards ---------------------------
 pblx-$(CONFIG_MACH_TOSHIBA_AC100) += start_toshiba_ac100
-FILE_barebox-tegra20-toshiba-ac100.img = start_toshiba_ac100.pblx
-image-$(CONFIG_MACH_TOSHIBA_AC100) += barebox-tegra20-toshiba-ac100.img
+FILE_barebox-tegra20-toshiba-ac100-usbloader.img = start_toshiba_ac100.pblx
+image-$(CONFIG_MACH_TOSHIBA_AC100) += barebox-tegra20-toshiba-ac100-usbloader.img
 
 pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_colibri_t20_256_usbload
 FILE_barebox-tegra20-toradex-colibri-t20-256-usbloader-iris.img = start_colibri_t20_256_usbload.pblx

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