qcom clock updates

PATCH New Stephen Boyd 2 participants 9 messages May 16, 2014 – May 29, 2014

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Stephen Boyd

author

2014-05-16 23:07 UTC #0 lore raw

cover qcom clock updates

Here are some bug fixes and updates to qcom clock driver. Mostly focused on running more drivers on msm8974 based devices and some fixes found in the process.

Stephen Boyd (7):
clk: qcom: Fix clk_rcg2_is_enabled() check
clk: qcom: Fix mmcc-8974's PLL configurations
clk: qcom: Return highest rate when round_rate() exceeds plan
clk: qcom: Support display RCG clocks
clk: qcom: Properly support display clocks on msm8974
clk: qcom: Support msm8974pro global clock control hardware
clk: qcom: Return error pointers for unimplemented clocks

 .../devicetree/bindings/clock/qcom,gcc.txt         |   2 +
 drivers/clk/qcom/clk-rcg.h                         |   3 +
 drivers/clk/qcom/clk-rcg2.c                        | 304 +++++++++++++++++++--
 drivers/clk/qcom/common.c                          |   4 +-
 drivers/clk/qcom/gcc-msm8974.c                     | 130 ++++++++-
 drivers/clk/qcom/mmcc-msm8974.c                    | 118 ++++----
 include/dt-bindings/clock/qcom,gcc-msm8974.h       |   4 +
 7 files changed, 485 insertions(+), 80 deletions(-)

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Stephen Boyd

author

2014-05-16 23:07 UTC #1 lore raw

PATCH 1/7 clk: qcom: Fix clk_rcg2_is_enabled() check

If the bit is set the clock is off so we should be checking for a clear bit, not a set bit. Invert the logic.

Fixes bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs))

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/clk-rcg2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/clk/qcom/clk-rcg2.c +1 -1

index 00f878a04d3f..0996a3a39855 100644
@@ -55,7 +55,7 @@ static int clk_rcg2_is_enabled(struct clk_hw *hw)
 	if (ret)
 		return ret;
 
-	return (cmd & CMD_ROOT_OFF) != 0;
+	return (cmd & CMD_ROOT_OFF) == 0;
 }
 
 static u8 clk_rcg2_get_parent(struct clk_hw *hw)

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hosted by The Linux Foundation

Stephen Boyd

author

2014-05-16 23:07 UTC #2 lore raw

PATCH 2/7 clk: qcom: Fix mmcc-8974's PLL configurations

In reply to Stephen Boyd

We forgot to add the status bit for the PLLs and we were using the wrong register and masks for configuration, leading to unexpected PLL configurations. Fix this.

Fixes d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC))

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/mmcc-msm8974.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

drivers/clk/qcom/mmcc-msm8974.c +8 -5

index 60b7c24a5cd6..62200bbc759e 100644
@@ -170,6 +170,7 @@ static struct clk_pll mmpll0 = {
 	.config_reg = 0x0014,
 	.mode_reg = 0x0000,
 	.status_reg = 0x001c,
+	.status_bit = 17,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll0",
                 .parent_names = (const char *[]){ "xo" },

@@ -193,9 +194,10 @@ static struct clk_pll mmpll1 = {
 	.l_reg = 0x0044,
 	.m_reg = 0x0048,
 	.n_reg = 0x004c,
-	.config_reg = 0x0054,
+	.config_reg = 0x0050,
 	.mode_reg = 0x0040,
 	.status_reg = 0x005c,
+	.status_bit = 17,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll1",
                 .parent_names = (const char *[]){ "xo" },

@@ -219,7 +221,7 @@ static struct clk_pll mmpll2 = {
 	.l_reg = 0x4104,
 	.m_reg = 0x4108,
 	.n_reg = 0x410c,
-	.config_reg = 0x4114,
+	.config_reg = 0x4110,
 	.mode_reg = 0x4100,
 	.status_reg = 0x411c,
         .clkr.hw.init = &(struct clk_init_data){

@@ -234,9 +236,10 @@ static struct clk_pll mmpll3 = {
 	.l_reg = 0x0084,
 	.m_reg = 0x0088,
 	.n_reg = 0x008c,
-	.config_reg = 0x0094,
+	.config_reg = 0x0090,
 	.mode_reg = 0x0080,
 	.status_reg = 0x009c,
+	.status_bit = 17,
         .clkr.hw.init = &(struct clk_init_data){
                 .name = "mmpll3",
                 .parent_names = (const char *[]){ "xo" },

@@ -2319,7 +2322,7 @@ static const struct pll_config mmpll1_config = {
 	.vco_val = 0x0,
 	.vco_mask = 0x3 << 20,
 	.pre_div_val = 0x0,
-	.pre_div_mask = 0x3 << 12,
+	.pre_div_mask = 0x7 << 12,
 	.post_div_val = 0x0,
 	.post_div_mask = 0x3 << 8,
 	.mn_ena_mask = BIT(24),

@@ -2333,7 +2336,7 @@ static struct pll_config mmpll3_config = {
 	.vco_val = 0x0,
 	.vco_mask = 0x3 << 20,
 	.pre_div_val = 0x0,
-	.pre_div_mask = 0x3 << 12,
+	.pre_div_mask = 0x7 << 12,
 	.post_div_val = 0x0,
 	.post_div_mask = 0x3 << 8,
 	.mn_ena_mask = BIT(24),

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Stephen Boyd

author

2014-05-16 23:07 UTC #3 lore raw

PATCH 3/7 clk: qcom: Return highest rate when round_rate() exceeds plan

In reply to Stephen Boyd

Some drivers may want to call clk_set_rate() with a very large number to force the clock to go as fast as it possibly can without having to know the range between the highest rate and second highest rate. Add support for this by defaulting to the highest rate in the frequency table if we can't find a frequency greater than what is requested.

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/clk-rcg2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/clk/qcom/clk-rcg2.c +2 -1

index 0996a3a39855..cbecaec30562 100644
@@ -181,7 +181,8 @@ struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
 		if (rate <= f->freq)
 			return f;
 
-	return NULL;
+	/* Default to our fastest rate */
+	return f - 1;
 }
 
 static long _freq_tbl_determine_rate(struct clk_hw *hw,

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Stephen Boyd

author

2014-05-16 23:07 UTC #4 lore raw

PATCH 4/7 clk: qcom: Support display RCG clocks

In reply to Stephen Boyd

Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices.

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/clk-rcg.h  |   3 +
 drivers/clk/qcom/clk-rcg2.c | 299 +++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 287 insertions(+), 15 deletions(-)

drivers/clk/qcom/clk-rcg.h +3 -0

index 1d6b6dece328..b9ec11dfd1b4 100644
@@ -155,5 +155,8 @@ struct clk_rcg2 {
 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
 
 extern const struct clk_ops clk_rcg2_ops;
+extern const struct clk_ops clk_edp_pixel_ops;
+extern const struct clk_ops clk_byte_ops;
+extern const struct clk_ops clk_pixel_ops;
 
 #endif

drivers/clk/qcom/clk-rcg2.c +284 ~~-15~~

338 lines not on this page · raw message

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Stephen Boyd

author

2014-05-16 23:07 UTC #5 lore raw

PATCH 5/7 clk: qcom: Properly support display clocks on msm8974

In reply to Stephen Boyd

The display clocks all source from dedicated phy PLLs within their respective multimedia hardware block. Hook up these PLLs to the display clocks with the appropriate parent mappings, clock flags, and the appropriate clock ops. This should allow the display clocks to work once the appropriate phy PLL driver registers their PLL clocks.

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/mmcc-msm8974.c | 105 +++++++++++++++++++++-------------------
 1 file changed, 54 insertions(+), 51 deletions(-)

drivers/clk/qcom/mmcc-msm8974.c +54 ~~-51~~

index 62200bbc759e..c65b90515872 100644
@@ -41,9 +41,11 @@
 #define P_EDPVCO	3
 #define P_GPLL1		4
 #define P_DSI0PLL	4
+#define P_DSI0PLL_BYTE	4
 #define P_MMPLL2	4
 #define P_MMPLL3	4
 #define P_DSI1PLL	5
+#define P_DSI1PLL_BYTE	5
 
 static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
 	[P_XO]		= 0,

@@ -161,6 +163,24 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 	"dsi1pll",
 };
 
+static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
+	[P_XO]			= 0,
+	[P_EDPLINK]		= 4,
+	[P_HDMIPLL]		= 3,
+	[P_GPLL0]		= 5,
+	[P_DSI0PLL_BYTE]	= 1,
+	[P_DSI1PLL_BYTE]	= 2,
+};
+
+static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
+	"xo",
+	"edp_link_clk",
+	"hdmipll",
+	"gpll0_vote",
+	"dsi0pllbyte",
+	"dsi1pllbyte",
+};
+
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
 static struct clk_pll mmpll0 = {

@@ -500,15 +520,8 @@ static struct clk_rcg2 jpeg2_clk_src = {
 	},
 };
 
-static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
-	F(125000000, P_DSI0PLL, 2, 0, 0),
-	F(250000000, P_DSI0PLL, 1, 0, 0),
-	{ }
-};
-
-static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
-	F(125000000, P_DSI1PLL, 2, 0, 0),
-	F(250000000, P_DSI1PLL, 1, 0, 0),
+static struct freq_tbl pixel_freq_tbl[] = {
+	{ .src = P_DSI0PLL },
 	{ }
 };

@@ -517,12 +530,13 @@ static struct clk_rcg2 pclk0_clk_src = {
 	.mnd_width = 8,
 	.hid_width = 5,
 	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-	.freq_tbl = ftbl_mdss_pclk0_clk,
+	.freq_tbl = pixel_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pclk0_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = 6,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_pixel_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };

@@ -531,12 +545,13 @@ static struct clk_rcg2 pclk1_clk_src = {
 	.mnd_width = 8,
 	.hid_width = 5,
 	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-	.freq_tbl = ftbl_mdss_pclk1_clk,
+	.freq_tbl = pixel_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pclk1_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = 6,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_pixel_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };

@@ -754,41 +769,36 @@ static struct clk_rcg2 cpp_clk_src = {
 	},
 };
 
-static struct freq_tbl ftbl_mdss_byte0_clk[] = {
-	F(93750000, P_DSI0PLL, 8, 0, 0),
-	F(187500000, P_DSI0PLL, 4, 0, 0),
-	{ }
-};
-
-static struct freq_tbl ftbl_mdss_byte1_clk[] = {
-	F(93750000, P_DSI1PLL, 8, 0, 0),
-	F(187500000, P_DSI1PLL, 4, 0, 0),
+static struct freq_tbl byte_freq_tbl[] = {
+	{ .src = P_DSI0PLL_BYTE },
 	{ }
 };
 
 static struct clk_rcg2 byte0_clk_src = {
 	.cmd_rcgr = 0x2120,
 	.hid_width = 5,
-	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-	.freq_tbl = ftbl_mdss_byte0_clk,
+	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
+	.freq_tbl = byte_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "byte0_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = 6,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_byte_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
 static struct clk_rcg2 byte1_clk_src = {
 	.cmd_rcgr = 0x2140,
 	.hid_width = 5,
-	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-	.freq_tbl = ftbl_mdss_byte1_clk,
+	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
+	.freq_tbl = byte_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "byte1_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = 6,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_byte_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };

@@ -826,12 +836,12 @@ static struct clk_rcg2 edplink_clk_src = {
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = 6,
 		.ops = &clk_rcg2_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
-	F(175000000, P_EDPVCO, 2, 0, 0),
-	F(350000000, P_EDPVCO, 11, 0, 0),
+static struct freq_tbl edp_pixel_freq_tbl[] = {
+	{ .src = P_EDPVCO },
 	{ }
 };

@@ -840,12 +850,12 @@ static struct clk_rcg2 edppixel_clk_src = {
 	.mnd_width = 8,
 	.hid_width = 5,
 	.parent_map = mmcc_xo_dsi_hdmi_edp_map,
-	.freq_tbl = ftbl_mdss_edppixel_clk,
+	.freq_tbl = edp_pixel_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "edppixel_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp,
 		.num_parents = 6,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_edp_pixel_ops,
 	},
 };

@@ -857,11 +867,11 @@ static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 static struct clk_rcg2 esc0_clk_src = {
 	.cmd_rcgr = 0x2160,
 	.hid_width = 5,
-	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
+	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 	.freq_tbl = ftbl_mdss_esc0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "esc0_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = 6,
 		.ops = &clk_rcg2_ops,
 	},

@@ -870,26 +880,18 @@ static struct clk_rcg2 esc0_clk_src = {
 static struct clk_rcg2 esc1_clk_src = {
 	.cmd_rcgr = 0x2180,
 	.hid_width = 5,
-	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
+	.parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 	.freq_tbl = ftbl_mdss_esc0_1_clk,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "esc1_clk_src",
-		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
+		.parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 		.num_parents = 6,
 		.ops = &clk_rcg2_ops,
 	},
 };
 
-static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
-	F(25200000, P_HDMIPLL, 1, 0, 0),
-	F(27000000, P_HDMIPLL, 1, 0, 0),
-	F(27030000, P_HDMIPLL, 1, 0, 0),
-	F(65000000, P_HDMIPLL, 1, 0, 0),
-	F(74250000, P_HDMIPLL, 1, 0, 0),
-	F(108000000, P_HDMIPLL, 1, 0, 0),
-	F(148500000, P_HDMIPLL, 1, 0, 0),
-	F(268500000, P_HDMIPLL, 1, 0, 0),
-	F(297000000, P_HDMIPLL, 1, 0, 0),
+static struct freq_tbl extpclk_freq_tbl[] = {
+	{ .src = P_HDMIPLL },
 	{ }
 };

@@ -897,12 +899,13 @@ static struct clk_rcg2 extpclk_clk_src = {
 	.cmd_rcgr = 0x2060,
 	.hid_width = 5,
 	.parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
-	.freq_tbl = ftbl_mdss_extpclk_clk,
+	.freq_tbl = extpclk_freq_tbl,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "extpclk_clk_src",
 		.parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 		.num_parents = 6,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_byte_ops,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Stephen Boyd

author

2014-05-16 23:07 UTC #6 lore raw

PATCH 6/7 clk: qcom: Support msm8974pro global clock control hardware

In reply to Stephen Boyd

A new PLL (gpll4) is added on msm8974 PRO devices to support a faster sdc1 clock rate. Add support for this and the two new sdcc cal clocks.

Signed-off-by Stephen Boyd <[email protected]>

---
 .../devicetree/bindings/clock/qcom,gcc.txt         |   2 +
 drivers/clk/qcom/gcc-msm8974.c                     | 130 ++++++++++++++++++++-
 include/dt-bindings/clock/qcom,gcc-msm8974.h       |   4 +
 3 files changed, 130 insertions(+), 6 deletions(-)

Documentation/devicetree/bindings/clock/qcom,gcc.txt +2 -0

index 7b7104e8cb1e..9cfcb4f2bc97 100644
@@ -8,6 +8,8 @@ Required properties :
 			"qcom,gcc-msm8660"
 			"qcom,gcc-msm8960"
 			"qcom,gcc-msm8974"
+			"qcom,gcc-msm8974pro"
+			"qcom,gcc-msm8974pro-ac"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1

drivers/clk/qcom/gcc-msm8974.c +124 -6

186 lines not on this page · raw message

include/dt-bindings/clock/qcom,gcc-msm8974.h +4 -0

index 223ca174d9d3..51e51c860fe6 100644
@@ -316,5 +316,9 @@
 #define GCC_CE2_CLK_SLEEP_ENA					299
 #define GCC_CE2_AXI_CLK_SLEEP_ENA				300
 #define GCC_CE2_AHB_CLK_SLEEP_ENA				301
+#define GPLL4							302
+#define GPLL4_VOTE						303
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
+#define GCC_SDCC1_CDCCAL_FF_CLK					305
 
 #endif

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Stephen Boyd

author

2014-05-16 23:07 UTC #7 lore raw

PATCH 7/7 clk: qcom: Return error pointers for unimplemented clocks

In reply to Stephen Boyd

Not all clocks are implemented but client drivers can still request them. Currently we will return a NULL pointer to them if the clock isn't implemented in software but NULL pointers are valid clock pointers. Return an error pointer so that driver's don't proceed without a clock they may actually need.

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/common.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/clk/qcom/common.c +3 -1

index 86b45fba5f90..9b5a1cfc6b91 100644
@@ -62,8 +62,10 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
 	data->clk_num = num_clks;
 
 	for (i = 0; i < num_clks; i++) {
-		if (!rclks[i])
+		if (!rclks[i]) {
+			clks[i] = ERR_PTR(-ENOENT);
 			continue;
+		}
 		clk = devm_clk_register_regmap(dev, rclks[i]);
 		if (IS_ERR(clk))
 			return PTR_ERR(clk);

Signature · 2 lines

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hosted by The Linux Foundation

Mike Turquette

Applied

2014-05-29 04:53 UTC #8 lore raw

cover qcom clock updates

In reply to Stephen Boyd

Quoting Stephen Boyd (2014-05-16 16:07:07)

Quoted 3 lines

Here are some bug fixes and updates to qcom clock driver. Mostly focused on running more drivers on msm8974 based devices and some fixes found in the process.

Applied to clk-next.

Regards,
Mike

Quoted 23 lines

Stephen Boyd (7):
clk: qcom: Fix clk_rcg2_is_enabled() check
clk: qcom: Fix mmcc-8974's PLL configurations
clk: qcom: Return highest rate when round_rate() exceeds plan
clk: qcom: Support display RCG clocks
clk: qcom: Properly support display clocks on msm8974
clk: qcom: Support msm8974pro global clock control hardware
clk: qcom: Return error pointers for unimplemented clocks
 .../devicetree/bindings/clock/qcom,gcc.txt         |   2 +
 drivers/clk/qcom/clk-rcg.h                         |   3 +
 drivers/clk/qcom/clk-rcg2.c                        | 304 +++++++++++++++++++--
 drivers/clk/qcom/common.c                          |   4 +-
 drivers/clk/qcom/gcc-msm8974.c                     | 130 ++++++++-
 drivers/clk/qcom/mmcc-msm8974.c                    | 118 ++++----
 include/dt-bindings/clock/qcom,gcc-msm8974.h       |   4 +
 7 files changed, 485 insertions(+), 80 deletions(-)
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation