nvc0: support for GK20A (Tegra K1)
cover nvc0: support for GK20A (Tegra K1)
The following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1).
GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers.
Alexandre Courbot (2):
nvc0: add GK20A 3D class
nvc0: use SM35 ISA with GK20A
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 5 files changed, 20 insertions(+), 6 deletions(-)
Signature · 1 line
1.9.3
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PATCH v2 1/2 nvc0: add GK20A 3D class
GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected.
--- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)
src/gallium/drivers/nouveau/nv_object.xml.h +1 -0
@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.#define NVC8_3D_CLASS 0x00009297#define NVE4_3D_CLASS 0x0000a097#define NVF0_3D_CLASS 0x0000a197 +#define NVEA_3D_CLASS 0x0000a297#define GM107_3D_CLASS 0x0000b097#define NV50_2D_CLASS 0x0000502d#define NVC0_2D_CLASS 0x0000902d
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +8 -1
@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class =NVF0_3D_CLASS ;break ;case 0xe0 : - obj_class =NVE4_3D_CLASS ; +switch (dev->chipset) { +case 0xea : + obj_class =NVEA_3D_CLASS ; +break ; +default : + obj_class =NVE4_3D_CLASS ; +break ; + }break ;case 0xd0 : obj_class =NVC8_3D_CLASS ;
Signature · 1 line
1.9.3
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Re: [PATCH 1/2] nvc0: add GK20A 3D class
Quoted 27 lines · Alexandre Courbot
GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected.
Signed-off-by Alexandre Courbot <[email protected]>--- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)src/gallium/drivers/nouveau/nv_object.xml.h +1
-0@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.#define NVC8_3D_CLASS 0x00009297#define NVE4_3D_CLASS 0x0000a097#define NVF0_3D_CLASS 0x0000a197 +#define NVEA_3D_CLASS 0x0000a297#define GM107_3D_CLASS 0x0000b097#define NV50_2D_CLASS 0x0000502d#define NVC0_2D_CLASS 0x0000902dsrc/gallium/drivers/nouveau/nvc0/nvc0_screen.c +0
-0
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c nvc0_screen_create(struct nouveau_device *dev) · line 707
Quoted 7 lines
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +3
-1@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class =NVF0_3D_CLASS ;break ;case 0xe0 : - obj_class =NVE4_3D_CLASS ; +switch (dev->chipset) { +case 0xea : + obj_class =NVEA_3D_CLASS ;
Again, would be nice to be consistent with the way you set the ISA... perhaps change this to a >= as well? But I guess the two could be disconnected. Up to you, just thought I'd bring it up.
Quoted 11 lines
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +5
-1+break ; +default : + obj_class =NVE4_3D_CLASS ; +break ; + }break ;case 0xd0 : obj_class =NVC8_3D_CLASS ; --1.9.3
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Re: [PATCH 1/2] nvc0: add GK20A 3D class
Quoted 31 lines · Ilia Mirkin
Quoted 30 lines · Alexandre Courbot
GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected.
Signed-off-by Alexandre Courbot <[email protected]>--- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)src/gallium/drivers/nouveau/nv_object.xml.h +1
-0@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.#define NVC8_3D_CLASS 0x00009297#define NVE4_3D_CLASS 0x0000a097#define NVF0_3D_CLASS 0x0000a197 +#define NVEA_3D_CLASS 0x0000a297#define GM107_3D_CLASS 0x0000b097#define NV50_2D_CLASS 0x0000502d#define NVC0_2D_CLASS 0x0000902dsrc/gallium/drivers/nouveau/nvc0/nvc0_screen.c +0
-0@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class =NVF0_3D_CLASS ;break ;case 0xe0 :
Quoted 8 lines
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c nvc0_screen_create(struct nouveau_device *dev) · line 707
Quoted 4 lines
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +3
-1- obj_class =NVE4_3D_CLASS ; +switch (dev->chipset) { +case 0xea : + obj_class =NVEA_3D_CLASS ;Again, would be nice to be consistent with the way you set the ISA... perhaps change this to a >= as well? But I guess the two could be disconnected. Up to you, just thought I'd bring it up.
Right below we have the following being done:
switch (dev->chipset) {
case 0xc8:
obj_class = NVC8_3D_CLASS;
break;
case 0xc1:
obj_class = NVC1_3D_CLASS;
break;
default:
obj_class = NVC0_3D_CLASS;
break;
}Shouldn't we try to be consistent with this more local example instead?
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Ilia Mirkin
Reviewed-byRe: [PATCH 1/2] nvc0: add GK20A 3D class
Quoted 70 lines · Alexandre Courbot
Quoted 45 lines · Ilia Mirkin
Quoted 42 lines · Alexandre Courbot
GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected.
Signed-off-by Alexandre Courbot <[email protected]>--- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)src/gallium/drivers/nouveau/nv_object.xml.h +0
-0@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THESOFTWARE.
#defineNVC8_3D_CLASS0x00009297
#defineNVE4_3D_CLASS0x0000a097
#defineNVF0_3D_CLASS0x0000a197
+#defineNVEA_3D_CLASS0x0000a297
#defineGM107_3D_CLASS0x0000b097
#defineNV50_2D_CLASS0x0000502d
#defineNVC0_2D_CLASS0x0000902dsrc/gallium/drivers/nouveau/nvc0/nvc0_screen.c +0
-1@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class =NVF0_3D_CLASS ;break ;case 0xe0 : - obj_class =NVE4_3D_CLASS ;Quoted 8 lines
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c nvc0_screen_create(struct nouveau_device *dev) · line 707
Quoted 3 lines
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +3
-0+switch (dev->chipset) { +case 0xea : + obj_class =NVEA_3D_CLASS ;Again, would be nice to be consistent with the way you set the ISA... perhaps change this to a >= as well? But I guess the two could be disconnected. Up to you, just thought I'd bring it up.
Right below we have the following being done:
switch (dev->chipset) { case 0xc8: obj_class = NVC8_3D_CLASS; break; case 0xc1: obj_class = NVC1_3D_CLASS; break; default: obj_class = NVC0_3D_CLASS; break; }
Quoted 1 line
Shouldn't we try to be consistent with this more local example instead?
Which is why I didn't insist. The situation with nvcx is a little different -- nvc8 (GF110) and nvc1 (GF108) are special, but e.g. nvce (GF114) and nvcf (GF116) want the nvc0 class. OTOH you're using >= 0xea as the metric for selecting SM35, so I was just pointing out the inconsistency. Of course there needn't be a 1:1 mapping between these things, and the likelihood of another 0xex chipset being released is fairly low. So:
PATCH v2 1/2 nvc0: add GK20A 3D class
In reply to a message not in the archiveGK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected.
--- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-)
src/gallium/drivers/nouveau/nv_object.xml.h +1 -0
@@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.#define NVC8_3D_CLASS 0x00009297#define NVE4_3D_CLASS 0x0000a097#define NVF0_3D_CLASS 0x0000a197 +#define NVEA_3D_CLASS 0x0000a297#define GM107_3D_CLASS 0x0000b097#define NV50_2D_CLASS 0x0000502d#define NVC0_2D_CLASS 0x0000902d
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +8 -1
@@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class =NVF0_3D_CLASS ;break ;case 0xe0 : - obj_class =NVE4_3D_CLASS ; +switch (dev->chipset) { +case 0xea : + obj_class =NVEA_3D_CLASS ; +break ; +default : + obj_class =NVE4_3D_CLASS ; +break ; + }break ;case 0xd0 : obj_class =NVC8_3D_CLASS ;
Signature · 1 line
1.9.3
v2 cover nvc0: support for GK20A (Tegra K1)
In reply to a message not in the archiveThe following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1).
GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers.
Changes since v1:
- Update TargetNVC0::getFileSize() to return the right number of GPR
- Remove definition for unneeded NVISA_GK110_CHIPSET
- Use consistent comparison scheme in nv50_ir_emit_nvc0.cpp
Alexandre Courbot (2):
nvc0: add GK20A 3D class
nvc0: use SM35 ISA with GK20A
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 5 files changed, 21 insertions(+), 8 deletions(-)
Signature · 1 line
1.9.3
PATCH v2 2/2 nvc0: use SM35 ISA with GK20A
In reply to a message not in the archiveGK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected.
--- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- 3 files changed, 11 insertions(+), 5 deletions(-)
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +1 -0
@@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol#define NVISA_GF100_CHIPSET_C0 0xc0#define NVISA_GF100_CHIPSET_D0 0xd0#define NVISA_GK104_CHIPSET 0xe0 +#define NVISA_GK20A_CHIPSET 0xea#define NVISA_GK110_CHIPSET 0xf0#define NVISA_GM107_CHIPSET 0x110
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +1 -1
@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET) + if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); }
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +9 -4
@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset != NVISA_GK20A_CHIPSET) { + *code = (const uint32_t *)&gk104_builtin_code[0]; + *size = sizeof(gk104_builtin_code); + break; + } + /* fall-through for GK20A */ case 0xf0: case 0x100: *code = (const uint32_t *)&gk110_builtin_code[0];
@@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const switch (chipset & ~0xf) { case 0xe0: - return gk104_builtin_offsets[builtin]; + if (chipset != NVISA_GK20A_CHIPSET) + return gk104_builtin_offsets[builtin]; + /* fall-through for GK20A */ case 0xf0: case 0x100: return gk110_builtin_offsets[builtin];
Signature · 1 line
1.9.3
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Re: [PATCH 2/2] nvc0: use SM35 ISA with GK20A
Quoted 27 lines · Alexandre Courbot
GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected.
Signed-off-by Alexandre Courbot <[email protected]>--- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- 3 files changed, 11 insertions(+), 5 deletions(-)src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +1
-0@@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol#define NVISA_GF100_CHIPSET_C0 0xc0#define NVISA_GF100_CHIPSET_D0 0xd0#define NVISA_GK104_CHIPSET 0xe0 +#define NVISA_GK20A_CHIPSET 0xea#define NVISA_GK110_CHIPSET 0xf0#define NVISA_GM107_CHIPSET 0x110src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +0
-0
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp TargetNVC0::createCodeEmitterNVC0(Program::Type type) · line 3033
Quoted 8 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +1
-1@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET) + if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); }
As mentioned on IRC, you also need to update TargetNVC0::getFileSize to return 255 GPRs, since that value is presumably ISA-specific. You could, at that point, get rid of the GK110_CHIPSET define. Eventually all that stuff needs to be nuked and replaced with an 'isa' property. But you don't have to do that.
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const · line 52
Quoted 12 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +1
-3@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset != NVISA_GK20A_CHIPSET) {
You change the code emitter if chipset >= GK20A. Might as well be consistent here and below.
Quoted 22 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +8
-2+ *code = (const uint32_t *)&gk104_builtin_code[0]; + *size = sizeof(gk104_builtin_code); + break; + } + /* fall-through for GK20A */ case 0xf0: case 0x100: *code = (const uint32_t *)&gk110_builtin_code[0];@@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const switch (chipset & ~0xf) { case 0xe0: - return gk104_builtin_offsets[builtin]; + if (chipset != NVISA_GK20A_CHIPSET) + return gk104_builtin_offsets[builtin]; + /* fall-through for GK20A */ case 0xf0: case 0x100: return gk110_builtin_offsets[builtin]; --1.9.3
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Re: [PATCH 2/2] nvc0: use SM35 ISA with GK20A
Quoted 32 lines · Ilia Mirkin
Quoted 31 lines · Alexandre Courbot
GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected.
Signed-off-by Alexandre Courbot <[email protected]>--- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- 3 files changed, 11 insertions(+), 5 deletions(-)src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +1
-0@@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol#define NVISA_GF100_CHIPSET_C0 0xc0#define NVISA_GF100_CHIPSET_D0 0xd0#define NVISA_GK104_CHIPSET 0xe0 +#define NVISA_GK20A_CHIPSET 0xea#define NVISA_GK110_CHIPSET 0xf0#define NVISA_GM107_CHIPSET 0x110src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +0
-1@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET)
Quoted 8 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp TargetNVC0::createCodeEmitterNVC0(Program::Type type) · line 3033
Quoted 4 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +1
-0+ if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); }As mentioned on IRC, you also need to update
TargetNVC0::getFileSizeto return 255 GPRs, since that value is presumably ISA-specific. You could, at that point, get rid of theGK110_CHIPSETdefine.
Will do.
Quoted 4 lines
Eventually
all that stuff needs to be nuked and replaced with an 'isa' property. But you don't have to do that.
Quoted 15 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const · line 52
Quoted 12 lines
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +1
-3@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset != NVISA_GK20A_CHIPSET) {You change the code emitter if chipset >= GK20A. Might as well be consistent here and below.
Sure.
PATCH v2 2/2 nvc0: use SM35 ISA with GK20A
In reply to Alexandre CourbotGK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected.
--- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-)
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +1 -1
@@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol#define NVISA_GF100_CHIPSET_C0 0xc0#define NVISA_GF100_CHIPSET_D0 0xd0#define NVISA_GK104_CHIPSET 0xe0 -#define NVISA_GK110_CHIPSET 0xf0 +#define NVISA_GK20A_CHIPSET 0xea#define NVISA_GM107_CHIPSET 0x110struct nv50_ir_prog_info
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +1 -1
@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET) + if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); }
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +10 -5
@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset < NVISA_GK20A_CHIPSET) { + *code = (const uint32_t *)&gk104_builtin_code[0]; + *size = sizeof(gk104_builtin_code); + break; + } + /* fall-through for GK20A */ case 0xf0: case 0x100: *code = (const uint32_t *)&gk110_builtin_code[0];
@@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const switch (chipset & ~0xf) { case 0xe0: - return gk104_builtin_offsets[builtin]; + if (chipset < NVISA_GK20A_CHIPSET) + return gk104_builtin_offsets[builtin]; + /* fall-through for GK20A */ case 0xf0: case 0x100: return gk110_builtin_offsets[builtin];
@@ -235,7 +240,7 @@ TargetNVC0::getFileSize(DataFile file) const { switch (file) { case FILE_NULL: return 0; - case FILE_GPR: return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63; + case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63; case FILE_PREDICATE: return 7; case FILE_FLAGS: return 1; case FILE_ADDRESS: return 0;
Signature · 1 line
1.9.3
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Ilia Mirkin
Reviewed-byRe: [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A
Quoted 4 lines · Alexandre Courbot
GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected.
Signed-off-by Alexandre Courbot <[email protected]>
Quoted 75 lines
--- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-)src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +1
-1@@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol#define NVISA_GF100_CHIPSET_C0 0xc0#define NVISA_GF100_CHIPSET_D0 0xd0#define NVISA_GK104_CHIPSET 0xe0 -#define NVISA_GK110_CHIPSET 0xf0 +#define NVISA_GK20A_CHIPSET 0xea#define NVISA_GM107_CHIPSET 0x110struct nv50_ir_prog_info src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +1
-1@@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET) + if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); }src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +10
-6@@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset < NVISA_GK20A_CHIPSET) { + *code = (const uint32_t *)&gk104_builtin_code[0]; + *size = sizeof(gk104_builtin_code); + break; + } + /* fall-through for GK20A */ case 0xf0: case 0x100: *code = (const uint32_t *)&gk110_builtin_code[0];@@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const switch (chipset & ~0xf) { case 0xe0: - return gk104_builtin_offsets[builtin]; + if (chipset < NVISA_GK20A_CHIPSET) + return gk104_builtin_offsets[builtin]; + /* fall-through for GK20A */ case 0xf0: case 0x100: return gk110_builtin_offsets[builtin];@@ -235,7 +240,7 @@ TargetNVC0::getFileSize(DataFile file) const { switch (file) { case FILE_NULL: return 0; - case FILE_GPR: return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63; + case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63; case FILE_PREDICATE: return 7; case FILE_FLAGS: return 1; case FILE_ADDRESS: return 0; --1.9.3