Enable RC6/Turbo on CHV

From: Deepak S <[email protected]>

Support to individually control Media/Render well based on the register access. Add CHV specific write function to habdle difference between registers that are sadowed vs those that need forcewake even for writes.

Streamline the CHV forcewake functions just like was done for VLV.

This will also fix a bug in accessing the common well registers, where we'd end up trying to wake up the wells too many times since we'd call force_wake_get/put twice per register access, with FORCEFAKE_ALL both times.

v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
Re-factor CHV/VLV Forcewake offsets (Ben)

v3: Fix for decrementing fw count in chv read/write. (Deepak)

v4: Squash the patches (Mika)

Reviewed-by Mika Kuoppala <[email protected]>

[vsyrjala: Move the register range macros into intel_uncore.c]

Signed-off-by Ville Syrjälä <[email protected]>

Signed-off-by Deepak S <[email protected]>

---
 drivers/gpu/drm/i915/intel_uncore.c | 135 +++++++++++++++++++++++++++++++-----
 1 file changed, 118 insertions(+), 17 deletions(-)

drivers/gpu/drm/i915/intel_uncore.c +118 -17

index 2f5d5d3..7409de0 100644
@@ -486,16 +486,43 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
 
-#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
-	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
-	((reg) >= 0x5000 && (reg) < 0x8000) ||\
-	((reg) >= 0xB000 && (reg) < 0x12000) ||\
-	((reg) >= 0x2E000 && (reg) < 0x30000))
+#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
 
-#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
-	(((reg) >= 0x12000 && (reg) < 0x14000) ||\
-	((reg) >= 0x22000 && (reg) < 0x24000) ||\
-	((reg) >= 0x30000 && (reg) < 0x40000))
+#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x2000, 0x4000) || \
+	 REG_RANGE((reg), 0x5000, 0x8000) || \
+	 REG_RANGE((reg), 0xB000, 0x12000) || \
+	 REG_RANGE((reg), 0x2E000, 0x30000))
+
+#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x12000, 0x14000) || \
+	 REG_RANGE((reg), 0x22000, 0x24000) || \
+	 REG_RANGE((reg), 0x30000, 0x40000))
+
+#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x2000, 0x4000) || \
+	 REG_RANGE((reg), 0x5000, 0x8000) || \
+	 REG_RANGE((reg), 0x8300, 0x8500) || \
+	 REG_RANGE((reg), 0xB000, 0xC000) || \
+	 REG_RANGE((reg), 0xE000, 0xE800))
+
+#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x8800, 0x8900) || \
+	 REG_RANGE((reg), 0xD000, 0xD800) || \
+	 REG_RANGE((reg), 0x12000, 0x14000) || \
+	 REG_RANGE((reg), 0x1A000, 0x1C000) || \
+	 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
+	 REG_RANGE((reg), 0x30000, 0x40000))
+
+#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
+	(REG_RANGE((reg), 0x4000, 0x5000) || \
+	 REG_RANGE((reg), 0x8000, 0x8300) || \
+	 REG_RANGE((reg), 0x8500, 0x8600) || \
+	 REG_RANGE((reg), 0x9000, 0xB000) || \
+	 REG_RANGE((reg), 0xC000, 0xC800) || \
+	 REG_RANGE((reg), 0xF000, 0x10000) || \
+	 REG_RANGE((reg), 0x14000, 0x14400) || \
+	 REG_RANGE((reg), 0x22000, 0x24000))
 
 static void
 ilk_dummy_write(struct drm_i915_private *dev_priv)

@@ -590,7 +617,35 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
 	REG_READ_FOOTER; \
 }
 
+#define __chv_read(x) \
+static u##x \
+chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+	unsigned fwengine = 0; \
+	REG_READ_HEADER(x); \
+	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+			fwengine = FORCEWAKE_RENDER; \
+	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_mediacount == 0) \
+			fwengine = FORCEWAKE_MEDIA; \
+	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+		if (dev_priv->uncore.fw_rendercount == 0) \
+			fwengine |= FORCEWAKE_RENDER; \
+		if (dev_priv->uncore.fw_mediacount == 0) \
+			fwengine |= FORCEWAKE_MEDIA; \
+	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+	val = __raw_i915_read##x(dev_priv, reg); \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	REG_READ_FOOTER; \
+}
 
+__chv_read(8)
+__chv_read(16)
+__chv_read(32)
+__chv_read(64)
 __vlv_read(8)
 __vlv_read(16)
 __vlv_read(32)

@@ -608,6 +663,7 @@ __gen4_read(16)
 __gen4_read(32)
 __gen4_read(64)
 
+#undef __chv_read
 #undef __vlv_read
 #undef __gen6_read
 #undef __gen5_read

@@ -712,6 +768,38 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
 	REG_WRITE_FOOTER; \
 }
 
+#define __chv_write(x) \
+static void \
+chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
+	unsigned fwengine = 0; \
+	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
+	REG_WRITE_HEADER; \
+	if (!shadowed) { \
+		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_rendercount == 0) \
+				fwengine = FORCEWAKE_RENDER; \
+		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_mediacount == 0) \
+				fwengine = FORCEWAKE_MEDIA; \
+		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
+			if (dev_priv->uncore.fw_rendercount == 0) \
+				fwengine |= FORCEWAKE_RENDER; \
+			if (dev_priv->uncore.fw_mediacount == 0) \
+				fwengine |= FORCEWAKE_MEDIA; \
+		} \
+	} \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
+	__raw_i915_write##x(dev_priv, reg, val); \
+	if (fwengine) \
+		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
+	REG_WRITE_FOOTER; \
+}
+
+__chv_write(8)
+__chv_write(16)
+__chv_write(32)
+__chv_write(64)
 __gen8_write(8)
 __gen8_write(16)
 __gen8_write(32)

@@ -733,6 +821,7 @@ __gen4_write(16)
 __gen4_write(32)
 __gen4_write(64)
 
+#undef __chv_write
 #undef __gen8_write
 #undef __hsw_write
 #undef __gen6_write

@@ -796,14 +885,26 @@ void intel_uncore_init(struct drm_device *dev)
 
 	switch (INTEL_INFO(dev)->gen) {
 	default:
-		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
-		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
-		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
-		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
-		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
-		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
-		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
-		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
+		if (IS_CHERRYVIEW(dev)) {
+			dev_priv->uncore.funcs.mmio_writeb  = chv_write8;
+			dev_priv->uncore.funcs.mmio_writew  = chv_write16;
+			dev_priv->uncore.funcs.mmio_writel  = chv_write32;
+			dev_priv->uncore.funcs.mmio_writeq  = chv_write64;
+			dev_priv->uncore.funcs.mmio_readb  = chv_read8;
+			dev_priv->uncore.funcs.mmio_readw  = chv_read16;
+			dev_priv->uncore.funcs.mmio_readl  = chv_read32;
+			dev_priv->uncore.funcs.mmio_readq  = chv_read64;
+
+		} else {
+			dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
+			dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
+			dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
+			dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
+			dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
+			dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
+			dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
+			dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
+		}
 		break;
 	case 7:
 	case 6:

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/i915_reg.h       | 10 ++++
 drivers/gpu/drm/i915/intel_pm.c       | 95 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
 4 files changed, 119 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_drv.h +1 -0

index 0412b12..5f0e338 100644
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h +0 -0

index c1f36a5..37f4b12 100644

drivers/gpu/drm/i915/i915_reg.h +0 -0

 /* See configdb bunit SB addr map */
 #define BUNIT_REG_BISOC				0x11
 

@@ -529,6 +530,14 @@ enum punit_power_well {
 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

drivers/gpu/drm/i915/i915_reg.h +1 -0

 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +942,7 @@ enum punit_power_well {
 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
 /* control register for cpu gtt access */
 #define TILECTL				0x101000
 #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 1816c52..08dcdc5 100644

drivers/gpu/drm/i915/intel_pm.c +13 -0

+	rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
+					CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+	rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

drivers/gpu/drm/i915/intel_pm.c +65 -1

+	return rpn;
+}
+
 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;

@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 
 static void cherryview_init_gt_powersave(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	cherryview_setup_pctx(dev);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 dev_priv->rps.max_freq);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 dev_priv->rps.min_freq);
+
+	/* Preserve min/max settings in case of re-init */
+	if (dev_priv->rps.max_freq_softlimit == 0)
+		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+	if (dev_priv->rps.min_freq_softlimit == 0)
+		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
 	int i;
 
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

@@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
 

drivers/gpu/drm/i915/intel_sideband.c +4 -0

index 01d841e..a74f60b 100644
@@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
 			SB_CRWRDA_NP, reg, &val);
 }
 
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+

drivers/gpu/drm/i915/intel_sideband.c +0 -0

 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 {
 	u32 val = 0;

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Hi Deepak,

Quoted 39 lines · [email protected] writes:

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---
  drivers/gpu/drm/i915/i915_drv.h       |  1 +
  drivers/gpu/drm/i915/i915_reg.h       | 10 ++++
  drivers/gpu/drm/i915/intel_pm.c       | 95 ++++++++++++++++++++++++++++++++++-
  drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
  4 files changed, 119 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_drv.h +1 -0

index 0412b12..5f0e338 100644
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
  u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
  void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
  void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h +0 -0

index c1f36a5..37f4b12 100644
@@ -487,6 +487,7 @@
  #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
  #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 

drivers/gpu/drm/i915/i915_reg.h line 490

Quoted 1 line

drivers/gpu/drm/i915/i915_reg.h +1 -0

+#define   CHV_IOSF_PORT_NC			0x04

Use IOSF_PORT_PUNIT instead of defining this?

Quoted 5 lines

drivers/gpu/drm/i915/i915_reg.h +0 -0

  /* See configdb bunit SB addr map */
  #define BUNIT_REG_BISOC				0x11
 

@@ -529,6 +530,14 @@ enum punit_power_well {
  #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 540

Quoted 10 lines

drivers/gpu/drm/i915/i915_reg.h +8 -0

  #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
+#define CHV_FB_RPE_FREQ_SHIFT			8
+#define CHV_FB_RPE_FREQ_MASK			0xff
+

These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS 0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf

etc...

Quoted 19 lines

drivers/gpu/drm/i915/i915_reg.h +1 -0

  #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
  #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
  #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +942,7 @@ enum punit_power_well {
  #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
  /* control register for cpu gtt access */
  #define TILECTL				0x101000
  #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 1816c52..08dcdc5 100644
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
  	mutex_unlock(&dev_priv->rps.hw_lock);
  }
 

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3739

Quoted 6 lines

drivers/gpu/drm/i915/intel_pm.c +6 -0

+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+

I didn't find any reason we couldn't use vlv_punit_read().

Quoted 13 lines

drivers/gpu/drm/i915/intel_pm.c +13 -0

+	rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
+					CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+	rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3762

Quoted 10 lines

drivers/gpu/drm/i915/intel_pm.c +10 -0

+	return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpn;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+	rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

Please don't reuse mask/shift from other register even tho they happen to be identical. This confuses the reader alot. Define new ones with proper naming.

Quoted 99 lines

drivers/gpu/drm/i915/intel_pm.c +65 -1

+	return rpn;
+}
+
  int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
  {
  	u32 val, rp0;

@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 
  static void cherryview_init_gt_powersave(struct drm_device *dev)
  {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
  	cherryview_setup_pctx(dev);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 dev_priv->rps.max_freq);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 dev_priv->rps.min_freq);
+
+	/* Preserve min/max settings in case of re-init */
+	if (dev_priv->rps.max_freq_softlimit == 0)
+		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+	if (dev_priv->rps.min_freq_softlimit == 0)
+		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
  }
 
  static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct intel_engine_cs *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
  	int i;
 
  	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

@@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
  	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
  }
 

drivers/gpu/drm/i915/intel_sideband.c +0 -0

index 01d841e..a74f60b 100644
@@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  			SB_CRWRDA_NP, reg, &val);
  }
 

Quoted 4 lines

drivers/gpu/drm/i915/intel_sideband.c +4 -0

+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+

drivers/gpu/drm/i915/intel_sideband.c void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) · line 131

Quoted 10 lines

drivers/gpu/drm/i915/intel_sideband.c +10 -0

+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
+			SB_CRRDDA_NP, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return val;
+}
+

Use vlv_punit_read() and you can get rid of this function.

-Mika

Quoted 10 lines

drivers/gpu/drm/i915/intel_sideband.c +0 -0

  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
  {
  	u32 val = 0;

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Quoted 43 lines · Mika Kuoppala

Hi Deepak,

Quoted 39 lines · [email protected] writes:

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---
  drivers/gpu/drm/i915/i915_drv.h       |  1 +
  drivers/gpu/drm/i915/i915_reg.h       | 10 ++++
  drivers/gpu/drm/i915/intel_pm.c       | 95 ++++++++++++++++++++++++++++++++++-
  drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
  4 files changed, 119 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_drv.h +1 -0

index 0412b12..5f0e338 100644
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
  u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
  void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
  void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h +0 -0

index c1f36a5..37f4b12 100644
@@ -487,6 +487,7 @@
  #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
  #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 

Quoted 2 lines

drivers/gpu/drm/i915/i915_reg.h line 490

Quoted 1 line

drivers/gpu/drm/i915/i915_reg.h +1 -0

+#define   CHV_IOSF_PORT_NC			0x04

Use IOSF_PORT_PUNIT instead of defining this?

Yes, Agreed, I will address this

Quoted 21 lines

Quoted 5 lines

drivers/gpu/drm/i915/i915_reg.h +0 -0

  /* See configdb bunit SB addr map */
  #define BUNIT_REG_BISOC				0x11
 

@@ -529,6 +530,14 @@ enum punit_power_well {
  #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 540

Quoted 10 lines

drivers/gpu/drm/i915/i915_reg.h +8 -0

  #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
+#define CHV_FB_RPE_FREQ_SHIFT			8
+#define CHV_FB_RPE_FREQ_MASK			0xff
+

These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS 0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf

Quoted 1 line

etc...

I can change. Q? don't we want to identify the register with CHV?

Quoted 19 lines

Quoted 19 lines

drivers/gpu/drm/i915/i915_reg.h +1 -0

  #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
  #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
  #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +942,7 @@ enum punit_power_well {
  #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
  /* control register for cpu gtt access */
  #define TILECTL				0x101000
  #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 1816c52..08dcdc5 100644
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
  	mutex_unlock(&dev_priv->rps.hw_lock);
  }
 

Quoted 7 lines

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3739

Quoted 6 lines

drivers/gpu/drm/i915/intel_pm.c +6 -0

+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+

I didn't find any reason we couldn't use vlv_punit_read().

I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV I would prefer to keep distinguish between fuse and punit read.

Quoted 98 lines · Deepak S

Quoted 43 lines · Mika Kuoppala

Hi Deepak,

Quoted 39 lines · [email protected] writes:

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---
   drivers/gpu/drm/i915/i915_drv.h       |  1 +
   drivers/gpu/drm/i915/i915_reg.h       | 10 ++++
   drivers/gpu/drm/i915/intel_pm.c       | 95 ++++++++++++++++++++++++++++++++++-
   drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
   4 files changed, 119 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_drv.h +1 -0

index 0412b12..5f0e338 100644
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
   u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
   void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
   u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
   u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
   void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
   u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h +0 -0

index c1f36a5..37f4b12 100644
@@ -487,6 +487,7 @@
   #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
   #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 

Quoted 2 lines

drivers/gpu/drm/i915/i915_reg.h line 490

Quoted 1 line

drivers/gpu/drm/i915/i915_reg.h +1 -0

+#define   CHV_IOSF_PORT_NC			0x04

Use IOSF_PORT_PUNIT instead of defining this?

Yes, Agreed, I will address this

Quoted 17 lines

Quoted 5 lines

drivers/gpu/drm/i915/i915_reg.h +0 -0

   /* See configdb bunit SB addr map */
   #define BUNIT_REG_BISOC				0x11
 

@@ -529,6 +530,14 @@ enum punit_power_well {
   #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 540

Quoted 10 lines

drivers/gpu/drm/i915/i915_reg.h +8 -0

   #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
+#define CHV_FB_RPE_FREQ_SHIFT			8
+#define CHV_FB_RPE_FREQ_MASK			0xff
+

These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS 0xdb

Quoted 5 lines

    PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
    PUNIT_GPU_STATUS_MAX_FREQ_MASK	0xff

PUNIT_REG_GPU_DUTYCYCLE 0xdf

etc...

I can change. Q? don't we want to identify the register with CHV?

Quoted 19 lines

Quoted 19 lines

drivers/gpu/drm/i915/i915_reg.h +1 -0

   #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
   #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
   #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +942,7 @@ enum punit_power_well {
   #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
   #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
   /* control register for cpu gtt access */
   #define TILECTL				0x101000
   #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 1816c52..08dcdc5 100644
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
   	mutex_unlock(&dev_priv->rps.hw_lock);
   }
 

Quoted 7 lines

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3739

Quoted 6 lines

drivers/gpu/drm/i915/intel_pm.c +6 -0

+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+

I didn't find any reason we couldn't use vlv_punit_read().

Quoted 2 lines

I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV I would prefer to keep distinguish between fuse and punit read.

If the register is in the punit you should use the punit funcs. If there's something special about those registers just add a comment which explains it.

The whole nc unit seems to have disappeared in CHV, so it's rather confusing when you see NC being mentioned and then you go digging through the docs and can't find anything like it.

Quoted 43 lines · Mika Kuoppala

Hi Deepak,

Quoted 39 lines · [email protected] writes:

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---
  drivers/gpu/drm/i915/i915_drv.h       |  1 +
  drivers/gpu/drm/i915/i915_reg.h       | 10 ++++
  drivers/gpu/drm/i915/intel_pm.c       | 95 ++++++++++++++++++++++++++++++++++-
  drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
  4 files changed, 119 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_drv.h +1 -0

index 0412b12..5f0e338 100644
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
  u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
  void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
  void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h +0 -0

index c1f36a5..37f4b12 100644
@@ -487,6 +487,7 @@
  #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
  #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 

Quoted 2 lines

drivers/gpu/drm/i915/i915_reg.h line 490

Quoted 1 line

drivers/gpu/drm/i915/i915_reg.h +1 -0

+#define   CHV_IOSF_PORT_NC			0x04

Use IOSF_PORT_PUNIT instead of defining this?

Yes, Agreed, I will address this

Quoted 21 lines

Quoted 5 lines

drivers/gpu/drm/i915/i915_reg.h +0 -0

  /* See configdb bunit SB addr map */
  #define BUNIT_REG_BISOC				0x11
 

@@ -529,6 +530,14 @@ enum punit_power_well {
  #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 540

Quoted 10 lines

drivers/gpu/drm/i915/i915_reg.h +8 -0

  #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
+#define CHV_FB_RPE_FREQ_SHIFT			8
+#define CHV_FB_RPE_FREQ_MASK			0xff
+

These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS 0xdb
PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
PUNIT_REG_GPU_DUTYCYCLE 0xdf

Quoted 1 line

etc...

I can change. Q? don't we want to identify the register with CHV?

Quoted 19 lines

Quoted 19 lines

drivers/gpu/drm/i915/i915_reg.h +1 -0

  #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
  #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
  #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +942,7 @@ enum punit_power_well {
  #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
  #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
  /* control register for cpu gtt access */
  #define TILECTL				0x101000
  #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 1816c52..08dcdc5 100644
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
  	mutex_unlock(&dev_priv->rps.hw_lock);
  }
 

Quoted 7 lines

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3739

Quoted 6 lines

drivers/gpu/drm/i915/intel_pm.c +6 -0

+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+

I didn't find any reason we couldn't use vlv_punit_read().

I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV I would prefer to keep distinguish between fuse and punit read.

Quoted 126 lines

Quoted 13 lines

drivers/gpu/drm/i915/intel_pm.c +13 -0

+	rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
+					CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+	rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3762

Quoted 10 lines

drivers/gpu/drm/i915/intel_pm.c +10 -0

+	return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpn;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+	rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

Please don't reuse mask/shift from other register even tho they happen to be identical. This confuses the reader alot. Define new ones with proper naming.

Quoted 99 lines

drivers/gpu/drm/i915/intel_pm.c +65 -1

+	return rpn;
+}
+
  int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
  {
  	u32 val, rp0;

@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 
  static void cherryview_init_gt_powersave(struct drm_device *dev)
  {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
  	cherryview_setup_pctx(dev);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 dev_priv->rps.max_freq);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 dev_priv->rps.min_freq);
+
+	/* Preserve min/max settings in case of re-init */
+	if (dev_priv->rps.max_freq_softlimit == 0)
+		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+	if (dev_priv->rps.min_freq_softlimit == 0)
+		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
  }
 
  static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
  {
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct intel_engine_cs *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
  	int i;
 
  	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

@@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
  	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
  	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
  }
 

drivers/gpu/drm/i915/intel_sideband.c +0 -0

index 01d841e..a74f60b 100644
@@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  			SB_CRWRDA_NP, reg, &val);
  }
 

Quoted 15 lines

Quoted 4 lines

drivers/gpu/drm/i915/intel_sideband.c +4 -0

+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+

drivers/gpu/drm/i915/intel_sideband.c void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) · line 131

Quoted 10 lines

drivers/gpu/drm/i915/intel_sideband.c +10 -0

+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
+			SB_CRRDDA_NP, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return val;
+}
+

Use vlv_punit_read() and you can get rid of this function.

Same as above. I would prefer to keep distinguish between fuse and punit read. If needed i can change Let me know you thoughts?

Quoted 12 lines

-Mika

Quoted 10 lines

drivers/gpu/drm/i915/intel_sideband.c +0 -0

  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
  {
  	u32 val = 0;

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Quoted 69 lines · Deepak S

Quoted 43 lines · Mika Kuoppala

Hi Deepak,

Quoted 39 lines · [email protected] writes:

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---
   drivers/gpu/drm/i915/i915_drv.h       |  1 +
   drivers/gpu/drm/i915/i915_reg.h       | 10 ++++
   drivers/gpu/drm/i915/intel_pm.c       | 95 ++++++++++++++++++++++++++++++++++-
   drivers/gpu/drm/i915/intel_sideband.c | 14 ++++++
   4 files changed, 119 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_drv.h +1 -0

index 0412b12..5f0e338 100644
@@ -2621,6 +2621,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
   u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
   void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
   u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
   u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
   void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
   u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

drivers/gpu/drm/i915/i915_reg.h +0 -0

index c1f36a5..37f4b12 100644
@@ -487,6 +487,7 @@
   #define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
   #define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
 

Quoted 2 lines

drivers/gpu/drm/i915/i915_reg.h line 490

Quoted 1 line

drivers/gpu/drm/i915/i915_reg.h +1 -0

+#define   CHV_IOSF_PORT_NC			0x04

Use IOSF_PORT_PUNIT instead of defining this?

Yes, Agreed, I will address this

Quoted 21 lines

Quoted 5 lines

drivers/gpu/drm/i915/i915_reg.h +0 -0

   /* See configdb bunit SB addr map */
   #define BUNIT_REG_BISOC				0x11
 

@@ -529,6 +530,14 @@ enum punit_power_well {
   #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */

drivers/gpu/drm/i915/i915_reg.h enum punit_power_well { · line 540

Quoted 10 lines

drivers/gpu/drm/i915/i915_reg.h +8 -0

   #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define CHV_IOSF_NC_FB_GFX_FREQ_FUSE		0xdb
+#define CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT		16
+#define CHV_FB_GFX_MAX_FREQ_FUSE_MASK		0xff
+
+#define CHV_IOSF_NC_FB_GFX_RPE_FUSE		0xdf
+#define CHV_FB_RPE_FREQ_SHIFT			8
+#define CHV_FB_RPE_FREQ_MASK			0xff
+

These seem to be also part of punit space so I would prefer:
PUNIT_REG_GPU_STATUS 0xdb

    PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
    PUNIT_GPU_STATUS_MAX_FREQ_MASK	0xff

PUNIT_REG_GPU_DUTYCYCLE 0xdf

Quoted 2 lines

Quoted 1 line

etc...

I can change. Q? don't we want to identify the register with CHV?

If you like, add /* chv */ after those punit regs you add.

I would not globber the namespace more. As in this case only chv code will use these inside cherryview_* named functions.

Quoted 169 lines

Quoted 19 lines

Quoted 19 lines

drivers/gpu/drm/i915/i915_reg.h +1 -0

   #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
   #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
   #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +942,7 @@ enum punit_power_well {
   #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
   #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
   /* control register for cpu gtt access */
   #define TILECTL				0x101000
   #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 1816c52..08dcdc5 100644
@@ -3731,6 +3731,38 @@ void gen6_update_ring_freq(struct drm_device *dev)
   	mutex_unlock(&dev_priv->rps.hw_lock);
   }
 

Quoted 7 lines

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3739

Quoted 6 lines

drivers/gpu/drm/i915/intel_pm.c +6 -0

+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+

I didn't find any reason we couldn't use vlv_punit_read().

I am adding separate function to be inline with VLV. If needed we can modify both VLV and CHV I would prefer to keep distinguish between fuse and punit read.

Quoted 126 lines

Quoted 13 lines

drivers/gpu/drm/i915/intel_pm.c +13 -0

+	rp0 = (val >> CHV_FB_GFX_MAX_FREQ_FUSE_SHIFT) &
+					CHV_FB_GFX_MAX_FREQ_FUSE_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_RPE_FUSE);
+	rpe = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

drivers/gpu/drm/i915/intel_pm.c void gen6_update_ring_freq(struct drm_device *dev) · line 3762

Quoted 10 lines

drivers/gpu/drm/i915/intel_pm.c +10 -0

+	return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpn;
+
+	val = chv_nc_read(dev_priv, CHV_IOSF_NC_FB_GFX_FREQ_FUSE);
+	rpn = (val >> CHV_FB_RPE_FREQ_SHIFT) & CHV_FB_RPE_FREQ_MASK;
+

Please don't reuse mask/shift from other register even tho they happen to be identical. This confuses the reader alot. Define new ones with proper naming.

Quoted 99 lines

drivers/gpu/drm/i915/intel_pm.c +65 -1

+	return rpn;
+}
+
   int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
   {
   	u32 val, rp0;

@@ -3890,7 +3922,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 
   static void cherryview_init_gt_powersave(struct drm_device *dev)
   {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
   	cherryview_setup_pctx(dev);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 dev_priv->rps.max_freq);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 dev_priv->rps.min_freq);
+
+	/* Preserve min/max settings in case of re-init */
+	if (dev_priv->rps.max_freq_softlimit == 0)
+		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+	if (dev_priv->rps.min_freq_softlimit == 0)
+		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
   }
 
   static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

@@ -3902,7 +3963,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
   {
   	struct drm_i915_private *dev_priv = dev->dev_private;
   	struct intel_engine_cs *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
   	int i;
 
   	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

@@ -3949,6 +4010,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
   	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
   	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
   }
 

drivers/gpu/drm/i915/intel_sideband.c +0 -0

index 01d841e..a74f60b 100644
@@ -115,6 +115,20 @@ void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
   			SB_CRWRDA_NP, reg, &val);
   }
 

Quoted 15 lines

Quoted 4 lines

drivers/gpu/drm/i915/intel_sideband.c +4 -0

+u32 chv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+{
+	u32 val = 0;
+

drivers/gpu/drm/i915/intel_sideband.c void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) · line 131

Quoted 10 lines

drivers/gpu/drm/i915/intel_sideband.c +10 -0

+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), CHV_IOSF_PORT_NC,
+			SB_CRRDDA_NP, addr, &val);
+	mutex_unlock(&dev_priv->dpio_lock);
+
+	return val;
+}
+

Use vlv_punit_read() and you can get rid of this function.

Quoted 2 lines

Same as above. I would prefer to keep distinguish between fuse and punit read. If needed i can change Let me know you thoughts?

The registers are in the punit space. The sideband target address is punit target address. For what I know, this is a punit access. Please explain why this fuse distingtion is needed/comes from.

If it has been fuse read in past then we have opportunity to forget the ugly past in here and match the code with the documentation. If this is the case, please change it to punit read and remove references to 'nc'

Thanks,
-Mika

Quoted 12 lines

Quoted 12 lines

-Mika

Quoted 10 lines

drivers/gpu/drm/i915/intel_sideband.c +0 -0

   u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
   {
   	u32 val = 0;

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

v6: Rename the variables to match the spec (Mika)

v7: change min/max freq variable naming to match spec (Mika)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---

 drivers/gpu/drm/i915/i915_reg.h | 11 +++++
 drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 102 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_reg.h +11 -0

index c1f36a5..8a935cf 100644
@@ -529,6 +529,16 @@ enum punit_power_well {
 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define PUNIT_GPU_STATUS_REG			0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
+
 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +943,7 @@ enum punit_power_well {
 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
 /* control register for cpu gtt access */
 #define TILECTL				0x101000
 #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +91 -1

index 1816c52..0f36405 100644
@@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+	rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
+	rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
+
+	return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpn;
+
+	val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+	rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
+	return rpn;
+}
+
 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;

@@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 
 static void cherryview_init_gt_powersave(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	cherryview_setup_pctx(dev);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 dev_priv->rps.max_freq);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 dev_priv->rps.min_freq);
+
+	/* Preserve min/max settings in case of re-init */
+	if (dev_priv->rps.max_freq_softlimit == 0)
+		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+	if (dev_priv->rps.min_freq_softlimit == 0)
+		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

@@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
 	int i;
 
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

@@ -3949,6 +4007,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
 

Signature · 6 lines

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Quoted 12 lines · [email protected] writes:

From: Deepak S <[email protected]>

v2: Disable media turbo and Add DOWN_IDLE_AVG support (Ville)

v3: Mass rename of the dev_priv->rps variables in upstream.

v4: Rebase against latest code. (Deepak)

v5: Rebase against latest nightly code. (Deepak)

v6: Rename the variables to match the spec (Mika)

Quoted 5 lines

v7: change min/max freq variable naming to match spec (Mika)

Signed-off-by Deepak S <[email protected]>

Signed-off-by Daniel Vetter <[email protected]>

---

Reviewed-by Mika Kuoppala <[email protected]>

Quoted 166 lines

 drivers/gpu/drm/i915/i915_reg.h | 11 +++++
 drivers/gpu/drm/i915/intel_pm.c | 92 ++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 102 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/i915_reg.h +11 -0

index c1f36a5..8a935cf 100644
@@ -529,6 +529,16 @@ enum punit_power_well {
 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
 
+#define PUNIT_GPU_STATUS_REG			0xdb
+#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT	16
+#define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
+#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT	8
+#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
+
+#define PUNIT_GPU_DUTYCYCLE_REG		0xdf
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT	8
+#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
+
 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
 #define   FB_GFX_MAX_FREQ_FUSE_SHIFT		3
 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8

@@ -933,6 +943,7 @@ enum punit_power_well {
 #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
 
+
 /* control register for cpu gtt access */
 #define TILECTL				0x101000
 #define   TILECTL_SWZCTL			(1 << 0)

drivers/gpu/drm/i915/intel_pm.c +91 -1

index 1816c52..0f36405 100644
@@ -3731,6 +3731,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
+int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rp0;
+
+	val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+	rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
+
+	return rp0;
+}
+
+static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpe;
+
+	val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
+	rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
+
+	return rpe;
+}
+
+int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
+{
+	u32 val, rpn;
+
+	val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
+	rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
+	return rpn;
+}
+
 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
 	u32 val, rp0;

@@ -3890,7 +3919,36 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
 
 static void cherryview_init_gt_powersave(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
 	cherryview_setup_pctx(dev);
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+
+	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
+	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
+	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
+			 dev_priv->rps.max_freq);
+
+	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
+	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
+	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
+			 dev_priv->rps.min_freq);
+
+	/* Preserve min/max settings in case of re-init */
+	if (dev_priv->rps.max_freq_softlimit == 0)
+		dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
+
+	if (dev_priv->rps.min_freq_softlimit == 0)
+		dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
+
+	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)

@@ -3902,7 +3960,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
-	u32 gtfifodbg, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
 	int i;
 
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

@@ -3949,6 +4007,38 @@ static void cherryview_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+	/* 4 Program defaults and thresholds for RPS*/
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	/* 5: Enable RPS */
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_AVG);
+
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
+	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
+			 dev_priv->rps.cur_freq);
+
+	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
+			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
+			 dev_priv->rps.efficient_freq);
+
+	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
+
 	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 }
 

Signature · 6 lines

1.9.1

_______________________________________________
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[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

From: Deepak S <[email protected]>

Signed-off-by Deepak S <[email protected]>

[vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]

Signed-off-by Ville Syrjälä <[email protected]>

Acked-by Ben Widawsky <[email protected]>

---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 08dcdc5..0b73a6d 100644

drivers/gpu/drm/i915/intel_pm.c +10 -0

 	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+	case 2:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 3:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
 
 	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
 	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);

Signature · 6 lines

1.9.1

_______________________________________________
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Quoted 19 lines · [email protected] writes:

From: Deepak S <[email protected]>

Signed-off-by Deepak S <[email protected]>

[vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]

Signed-off-by Ville Syrjälä <[email protected]>

Acked-by Ben Widawsky <[email protected]>

---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 08dcdc5..0b73a6d 100644
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
 

drivers/gpu/drm/i915/intel_pm.c static void cherryview_enable_rps(struct drm_device *dev) · line 4029

Quoted 1 line

drivers/gpu/drm/i915/intel_pm.c +1 -0

+	/* ToDo: Update the mem freq based on latest spec [CHV]*/

Please do and consider fixing the vlv decoding. It seems to be off too.

-Mika

Quoted 21 lines

drivers/gpu/drm/i915/intel_pm.c +10 -0

 	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+	case 2:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 3:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
 
 	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
 	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Quoted 21 lines · Mika Kuoppala

Quoted 19 lines · [email protected] writes:

From: Deepak S <[email protected]>

Signed-off-by Deepak S <[email protected]>

[vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]

Signed-off-by Ville Syrjälä <[email protected]>

Acked-by Ben Widawsky <[email protected]>

---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 08dcdc5..0b73a6d 100644
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
 		   GEN6_RP_UP_BUSY_AVG |
 		   GEN6_RP_DOWN_IDLE_AVG);
 

Quoted 4 lines

drivers/gpu/drm/i915/intel_pm.c static void cherryview_enable_rps(struct drm_device *dev) · line 4029

Quoted 1 line

drivers/gpu/drm/i915/intel_pm.c +1 -0

+	/* ToDo: Update the mem freq based on latest spec [CHV]*/

Please do and consider fixing the vlv decoding. It seems to be off too.

Poke about this one here. Iirc the situation on vlv is simply terminal confusion, and iirc the current code matches reality of shipping vbiosen, but not any spec.

I hope we're bettter for chv.

Quoted 22 lines · Daniel Vetter

Quoted 21 lines · Mika Kuoppala

Quoted 19 lines · [email protected] writes:

From: Deepak S <[email protected]>

Signed-off-by Deepak S <[email protected]>

[vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]

Signed-off-by Ville Syrjälä <[email protected]>

Acked-by Ben Widawsky <[email protected]>

---
  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
  1 file changed, 11 insertions(+)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 08dcdc5..0b73a6d 100644
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
  		   GEN6_RP_UP_BUSY_AVG |
  		   GEN6_RP_DOWN_IDLE_AVG);
 

Quoted 6 lines

Quoted 3 lines

drivers/gpu/drm/i915/intel_pm.c static void cherryview_enable_rps(struct drm_device *dev) · line 4029

Quoted 1 line

drivers/gpu/drm/i915/intel_pm.c +1 -0

+	/* ToDo: Update the mem freq based on latest spec [CHV]*/

Please do and consider fixing the vlv decoding. It seems to be off too.

Poke about this one here. Iirc the situation on vlv is simply terminal confusion, and iirc the current code matches reality of shipping vbiosen, but not any spec.

Yeah changed back here:

commit f6d519481b662d9fc52836e6e6107520f03e0122

Author: Deepak S <[email protected]>
Date:   Thu Apr 3 21:01:28 2014 +0530

Revert "drm/i915/vlv: fixup DDR freq detection per Punit spec"

As per the inputs provided by hardware team we still use DDR Rates as 0,1=800, 2=1066, 3=1333.
With this change, Turbo freqs used on current machines matches.

I think what we need is a comment there which states why we're going against the spec, just to avoid future confusion and someone accidentally changing it back again.

Quoted 1 line

I hope we're bettter for chv.

One can dream.

Quoted 21 lines · Mika Kuoppala

Quoted 19 lines · [email protected] writes:

From: Deepak S <[email protected]>

Signed-off-by Deepak S <[email protected]>

[vsyrjala: Fix merge fubmle where the code ended up in g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]

Signed-off-by Ville Syrjälä <[email protected]>

Acked-by Ben Widawsky <[email protected]>

---
  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
  1 file changed, 11 insertions(+)

drivers/gpu/drm/i915/intel_pm.c +0 -0

index 08dcdc5..0b73a6d 100644
@@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_device *dev)
  		   GEN6_RP_UP_BUSY_AVG |
  		   GEN6_RP_DOWN_IDLE_AVG);
 

Quoted 3 lines

drivers/gpu/drm/i915/intel_pm.c static void cherryview_enable_rps(struct drm_device *dev) · line 4029

Quoted 1 line

drivers/gpu/drm/i915/intel_pm.c +1 -0

+	/* ToDo: Update the mem freq based on latest spec [CHV]*/

Please do and consider fixing the vlv decoding. It seems to be off too.

Poke about this one here. Iirc the situation on vlv is simply terminal confusion, and iirc the current code matches reality of shipping vbiosen, but not any spec. I hope we're bettter for chv.
-Daniel

Quoted 27 lines

-Mika

Quoted 21 lines

drivers/gpu/drm/i915/intel_pm.c +10 -0

  	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	switch ((val >> 6) & 3) {
+	case 0:
+	case 1:
+	case 2:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 3:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
 
  	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
  	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);

Signature · 6 lines

1.9.1

_______________________________________________
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx