sunxi: Bug fixes, sun4i and sun5i support, pmic support and network improvements

We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails.

file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all.

Signed-off-by Hans de Goede <[email protected]>

Quoted 7 lines · Hans de Goede

We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails.

file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all.

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Quoted 7 lines · On Fri, 30 May 2014 10:19:16 +0100 Ian Campbell <[email protected]> wrote:

Quoted 6 lines · Hans de Goede

We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails.

file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all.

Quoted 3 lines

Quoted 1 line

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Acked-by Siarhei Siamashka <[email protected]>

Was there any valid reason why this important bugfix has not been nominated for v2014.07?

Quoted 14 lines · Siarhei Siamashka

Quoted 10 lines · On Fri, 30 May 2014 10:19:16 +0100 Ian Campbell <[email protected]> wrote:

Quoted 7 lines · Hans de Goede

We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails.

file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all.

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Quoted 4 lines

Acked-by Siarhei Siamashka <[email protected]>

Was there any valid reason why this important bugfix has not been nominated for v2014.07?

Not sure what you mean, it is part of the PR at
http://patchwork.ozlabs.org/patch/371704/

Adjust the u-boot-spl.lds linker script to match the changes made in the "arm: move exception handling out of start.S files" commit.

Signed-off-by Hans de Goede <[email protected]>

The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack,

and then exits while the dma transfer is in
progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem.

Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code.

Signed-off-by Hans de Goede <[email protected]>

There is no way to reset the cpu, so use the watchdog for this.

Signed-off-by Hans de Goede <[email protected]>

arch/arm/include/asm/arch-sunxi/timer.h +3 -0

+#define WDT_MODE_EN             (0x1 << 0)
+#define WDT_MODE_RESET_EN       (0x1 << 1)
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>

Quoted 3 lines · Hans de Goede

There is no way to reset the cpu, so use the watchdog for this.

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

One nit

arch/arm/include/asm/arch-sunxi/timer.h line 15

Quoted 2 lines

arch/arm/include/asm/arch-sunxi/timer.h +2 -0

+#define WDT_CTRL_RESTART        (0x1 << 0)
+#define WDT_CTRL_KEY		(0x0a57 << 1)

Some sort of whitespace snafuu I think.

Add support for the Allwinner A10 SoC also know as the Allwinner sun4i family.

Signed-off-by Henrik Nordstrom <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Signed-off-by Oliver Schinagl <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/Makefile   |  2 +
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  7 ++++
 arch/arm/cpu/armv7/sunxi/dram.c     | 81 +++++++++++++++++++++++++++++++++++--
 board/sunxi/Makefile                |  1 +
 board/sunxi/dram_cubieboard.c       | 31 ++++++++++++++
 boards.cfg                          |  1 +

Quoted 1 line · Hans de Goede

Add support for the Allwinner A10 SoC also know as the Allwinner sun4i family.

"known".

Could you enumerate the main differences vs the existing sun7i stuff. e.g.:
- dram init and timing (hpcr?) values
- CCM_AHB_GATE_DLL
- ...

Quoted 11 lines

Signed-off-by Henrik Nordstrom <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Signed-off-by Oliver Schinagl <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
  arch/arm/cpu/armv7/sunxi/Makefile   |  2 +
  arch/arm/cpu/armv7/sunxi/cpu_info.c |  7 ++++
  arch/arm/cpu/armv7/sunxi/dram.c     | 81 +++++++++++++++++++++++++++++++++++--
  board/sunxi/Makefile                |  1 +
  board/sunxi/dram_cubieboard.c       | 31 ++++++++++++++
  boards.cfg                          |  1 +

Please mention that you are enabling cb with this patch in the commit message.

Quoted 5 lines

  static void mctl_set_drive(void)
  {
  	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;

arch/arm/cpu/armv7/sunxi/dram.c static void mctl_ddr3_reset(void) · line 86

Quoted 5 lines

arch/arm/cpu/armv7/sunxi/dram.c +4 -0

+#ifdef CONFIG_SUN7I
  	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+#else
+	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
+#endif

This could be written as an ifdef around the "0x3<< 28 |" only (moved to its own line). Is that a better way though?

arch/arm/cpu/armv7/sunxi/dram.c unsigned long dramc_init(struct dram_para *para) · line 553

Quoted 6 lines

arch/arm/cpu/armv7/sunxi/dram.c +2 -0

@@ -490,6 +549,22 @@ unsigned long dramc_init(struct dram_para *para)
 
  	mctl_enable_dllx(para->tpr3);
 
+#ifdef CONFIG_SUN4I
+	/* set odt impendance divide ratio */

"impedance"

Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner sun5i family.

Signed-off-by Henrik Nordstrom <[email protected]>

Signed-off-by Stefan Roese <[email protected]>

Signed-off-by Oliver Schinagl <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/Makefile   |  2 ++
 arch/arm/cpu/armv7/sunxi/board.c    | 12 ++++++++++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c |  8 ++++++++
 arch/arm/cpu/armv7/sunxi/dram.c     | 21 +++++++++++++++++++++
 board/sunxi/Makefile                |  2 ++
 board/sunxi/dram_a13_oli_micro.c    | 32 ++++++++++++++++++++++++++++++++
 board/sunxi/dram_r7dongle.c         | 31 +++++++++++++++++++++++++++++++
 boards.cfg                          |  2 ++

Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code.

Signed-off-by Hans de Goede <[email protected]>

From: Henrik Nordstrom <[email protected]>

Add support for the x-powers axp209 pmic which is found on most A10, A13 and A20 boards.

While changing the boards.cfg lines for the Cubietruck, add myself as board maintainer for the Cubietruck.

board/sunxi/board.c +2 -0

+#endif
+
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
 	printf(" %lu MiB\n", ramsize >> 20);
 	if (!ramsize)
 		hang();

board/sunxi/board.c +3 -0

+#endif
+	else
+		printf("Failed to set core voltage! Can't set CPU frequency\n");
 }
 #endif

drivers/power/axp209.c new file +20 -0

new file mode 100644
index 0000000..a3f9d52
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <axp209.h>
+
+enum axp209_reg {
+	AXP209_POWER_STATUS = 0x00,
+	AXP209_CHIP_VERSION = 0x03,
+	AXP209_DCDC2_VOLTAGE = 0x23,
+	AXP209_DCDC3_VOLTAGE = 0x27,
+	AXP209_LDO24_VOLTAGE = 0x28,
+	AXP209_LDO3_VOLTAGE = 0x29,
+	AXP209_IRQ_STATUS3 = 0x4a,
+	AXP209_IRQ_STATUS5 = 0x4c,

drivers/power/axp209.c new file +9 -0

+
+int axp209_write(enum axp209_reg reg, u8 val)
+{
+	return i2c_write(0x34, reg, 1, &val, 1);
+}
+
+int axp209_read(enum axp209_reg reg, u8 *val)
+{
+	return i2c_read(0x34, reg, 1, val, 1);

drivers/power/axp209.c new file +7 -0

+	rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+

drivers/power/axp209.c new file +27 -0

+
+	return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo4(int mvolt)
+{
+	int cfg, rc;
+	static const int vindex[] = {
+		1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
+		2700, 2800, 3000, 3100, 3200, 3300
+	};
+	u8 reg;
+
+	/* Translate mvolt to register cfg value, requested <= selected */
+	for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
+
+	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
+	if (rc)
+		return rc;
+
+	/* LDO4 configuration is in lower 4 bits */
+	reg = (reg & 0xf0) | (cfg << 0);
+	rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
+	if (rc)
+		return rc;
+
+	return 0;

Quoted 7 lines · Hans de Goede

From: Henrik Nordstrom <[email protected]>

Add support for the x-powers axp209 pmic which is found on most A10, A13 and A20 boards.

While changing the boards.cfg lines for the Cubietruck, add myself as board maintainer for the Cubietruck.

I don't know much about these PMIC things, so just some general comments/questions.

board/sunxi/board.c void i2c_init_board(void) · line 122

Quoted 8 lines

  #include <asm/arch/clock.h>
  #include <asm/arch/dram.h>
  #include <asm/arch/gpio.h>

board/sunxi/board.c +1 -0

@@ -116,12 +119,35 @@ void i2c_init_board(void)
  #ifdef CONFIG_SPL_BUILD
  void sunxi_board_init(void)
  {
+	int power_failed = 0;

bool?

board/sunxi/board.c void i2c_init_board(void) · line 131

Quoted 10 lines

board/sunxi/board.c +7 -0

  	unsigned long ramsize;
 
+#ifdef CONFIG_AXP209_POWER
+	power_failed |= axp209_init();
+	power_failed |= axp209_set_dcdc2(1400);
+	power_failed |= axp209_set_dcdc3(1250);
+	power_failed |= axp209_set_ldo2(3000);
+	power_failed |= axp209_set_ldo3(2800);
+	power_failed |= axp209_set_ldo4(2800);

I take it that it is safe to keep poking at things after one of them fails?

Quoted 12 lines

board/sunxi/board.c +6 -0

+#endif
+
  	printf("DRAM:");
  	ramsize = sunxi_dram_init();
  	printf(" %lu MiB\n", ramsize >> 20);
  	if (!ramsize)
  		hang();
+
+	/*
+	 * Only clock up the CPU to full speed if we are reasonably
+	 * assured it's being powered with suitable core voltage

board/sunxi/board.c void i2c_init_board(void) · line 148

Quoted 6 lines

board/sunxi/board.c +6 -0

+	 */
+	if (!power_failed)
+#ifdef CONFIG_SUN7I
+		clock_set_pll1(912000000);
+#else
+		clock_set_pll1(1008000000);

#define CLK_FULL_SPEED in the relevant sun?i-config.h-es?

Quoted 36 lines

board/sunxi/board.c +3 -0

+#endif
+	else
+		printf("Failed to set core voltage! Can't set CPU frequency\n");
  }
  #endif

drivers/power/axp209.c new file +24 -0

new file mode 100644
index 0000000..a3f9d52
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2012
+ * Henrik Nordstrom <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <axp209.h>
+
+enum axp209_reg {
+	AXP209_POWER_STATUS = 0x00,
+	AXP209_CHIP_VERSION = 0x03,
+	AXP209_DCDC2_VOLTAGE = 0x23,
+	AXP209_DCDC3_VOLTAGE = 0x27,
+	AXP209_LDO24_VOLTAGE = 0x28,
+	AXP209_LDO3_VOLTAGE = 0x29,
+	AXP209_IRQ_STATUS3 = 0x4a,
+	AXP209_IRQ_STATUS5 = 0x4c,
+	AXP209_SHUTDOWN = 0x32,
+};
+
+#define AXP209_POWER_STATUS_ON_BY_DC	(1<<0)

drivers/power/axp209.c line 30

Quoted 6 lines

drivers/power/axp209.c new file +6 -0

+
+#define AXP209_IRQ3_PEK_SHORT		(1<<1)
+#define AXP209_IRQ3_PEK_LONG		(1<<0)
+
+#define AXP209_IRQ5_PEK_UP		(1<<6)
+#define AXP209_IRQ5_PEK_DOWN		(1<<5)

Only IRQ5 is used?

Quoted 15 lines

drivers/power/axp209.c new file +14 -0

+
+int axp209_write(enum axp209_reg reg, u8 val)
+{
+	return i2c_write(0x34, reg, 1, &val, 1);
+}
+
+int axp209_read(enum axp209_reg reg, u8 *val)
+{
+	return i2c_read(0x34, reg, 1, val, 1);
+}
+
+int axp209_set_dcdc2(int mvolt)
+{
+	int cfg = (mvolt - 700) / 25;

drivers/power/axp209.c line 49

Quoted 5 lines

drivers/power/axp209.c new file +5 -0

+	int rc;
+	u8 current;
+
+	if (cfg < 0)
+		cfg = 0;

Can we make mvolt and cfg unsigned? (I suppose you'd then need a range check on mvolt before the subtraction, so perhaps it doesn't save much?)

drivers/power/axp209.c line 51

Quoted 3 lines

drivers/power/axp209.c new file +2 -0

+	if (cfg > (1 << 6) - 1)
+		cfg = (1 << 6) - 1;

#define AXP209_DCDC2_MAX?

drivers/power/axp209.c line 78

Quoted 10 lines

drivers/power/axp209.c new file +10 -0

+int axp209_set_dcdc3(int mvolt)
+{
+	int cfg = (mvolt - 700) / 25;
+	u8 reg;
+	int rc;
+
+	if (cfg < 0)
+		cfg = 0;
+	if (cfg > (1 << 7) - 1)
+		cfg = (1 << 7) - 1;

Some two comments as for DCDC2 (which I won't bother making for subsequent clocks).

perhaps cfg = clamp(cfg, 0, 1<<7-1)? Or even cfg = mvolt_to_cfg(mvolt, 700, 25, 0, 1<<7-1)?

drivers/power/axp209.c line 81

Quoted 3 lines

drivers/power/axp209.c new file +2 -0

+	rc = axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
+	rc |= axp209_read(AXP209_DCDC3_VOLTAGE, &reg);

Is read safe if the write failed? Since the reg is never used I assume it's just some sort of sync? Or do you need to confirm the contents "took"? If not you could remove reg and readback into cfg.

drivers/power/axp209.c line 101

Quoted 5 lines

drivers/power/axp209.c new file +5 -0

+	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
+	if (rc)
+		return rc;
+
+	reg = (reg & 0x0f) | (cfg << 4);

Do we know what these magic numbers mean?

(ah, you have a comment on the use of the lower 4 bits, but not the upper 4 used here...)

Quoted 11 lines

drivers/power/axp209.c new file +11 -0

+	rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+int axp209_set_ldo3(int mvolt)
+{
+	int cfg = (mvolt - 700) / 25;
+

drivers/power/axp209.c line 118

Quoted 6 lines

drivers/power/axp209.c new file +6 -0

+	if (cfg < 0)
+		cfg = 0;
+	if (cfg > 127)
+		cfg = 127;
+	if (mvolt == -1)
+		cfg = 0x80;	/* detemined by LDO3IN pin */

"determined"

Quoted 32 lines

drivers/power/axp209.c new file +31 -0

+
+	return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
+}
+
+int axp209_set_ldo4(int mvolt)
+{
+	int cfg, rc;
+	static const int vindex[] = {
+		1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
+		2700, 2800, 3000, 3100, 3200, 3300
+	};
+	u8 reg;
+
+	/* Translate mvolt to register cfg value, requested <= selected */
+	for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
+
+	rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
+	if (rc)
+		return rc;
+
+	/* LDO4 configuration is in lower 4 bits */
+	reg = (reg & 0xf0) | (cfg << 0);
+	rc = axp209_write(AXP209_LDO24_VOLTAGE, reg);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+void axp209_poweroff(void)
+{

drivers/power/axp209.c line 155

Quoted 6 lines

drivers/power/axp209.c new file +6 -0

+	u8 val;
+
+	if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
+		return;
+
+	val |= 1 << 7;

#define?

Add support for the x-powers axp152 pmic which is found on most A10s boards.

Quoted 1 line · Hans de Goede

Add support for the x-powers axp152 pmic which is found on most A10s boards.

This driver looks superficially very similar to the last one, have you considered merging them?

Other than that most of the generic questions I had on the last one seem to appear here too, magic numbers and so on.

 drivers/net/sunxi_emac.c  | 521 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/net/sunxi_wemac.c | 525 ----------------------------------------------

commit b6d2111e9a43c927cc83609625107c5b2a518163

Author: Stefan Roese <[email protected]>
Date:   Mon Nov 5 13:12:49 2012 +0100

net: Rename and cleanup sunxi (Allwinner) emac driver

There have been 3 versions of the sunxi_emac support patch during its development. Somehow version 2 ended up in upstream u-boot where as the u-boot-sunxi git repo got version 3.

This bumps the version in upstream u-boot to version 3 of the patch:
- Initialize MII clock earlier so mii access to allow independent use
- Name change from WEMAC to EMAC to match mainline kernel & chip manual
- Cosmetic code cleanup

Signed-off-by Stefan Roese <[email protected]>

Signed-off-by Henrik Nordstrom <[email protected]>

Signed-off-by Oliver Schinagl <[email protected]>

Signed-off-by Hans de Goede <[email protected]>

drivers/net/Makefile +1 -1

index 6005f7e..da2b5f8 100644
@@ -20,6 +20,7 @@ obj-$(CONFIG_DNET) += dnet.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
+obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
 obj-$(CONFIG_ENC28J60) += enc28j60.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
 obj-$(CONFIG_ETHOC) += ethoc.o

@@ -51,7 +52,6 @@ obj-$(CONFIG_RTL8169) += rtl8169.o
 obj-$(CONFIG_SH_ETHER) += sh_eth.o
 obj-$(CONFIG_SMC91111) += smc91111.o
 obj-$(CONFIG_SMC911X) += smc911x.o
-obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o

drivers/net/sunxi_emac.c renamed from drivers/net/sunxi_wemac.c +68 -72

similarity index 78%
rename from drivers/net/sunxi_wemac.c
rename to drivers/net/sunxi_emac.c
index 699a381..5a06d68 100644
@@ -1,5 +1,5 @@
 /*
- * sunxi_wemac.c -- Allwinner A10 ethernet driver
+ * sunxi_emac.c -- Allwinner A10 ethernet driver
  *
  * (C) Copyright 2012, Stefan Roese <[email protected]>
  *

@@ -7,16 +7,16 @@
  */
 
 #include <common.h>
+#include <linux/err.h>
 #include <malloc.h>
-#include <net.h>
 #include <miiphy.h>
-#include <linux/err.h>
+#include <net.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 
 /* EMAC register  */
-struct wemac_regs {
+struct emac_regs {
 	u32 ctl;	/* 0x00 */
 	u32 tx_mode;	/* 0x04 */
 	u32 tx_flow;	/* 0x08 */

@@ -27,7 +27,7 @@ struct wemac_regs {
 	u32 tx_pl1;	/* 0x1c */
 	u32 tx_sta;	/* 0x20 */
 	u32 tx_io_data;	/* 0x24 */
-	u32 tx_io_data1; /* 0x28 */
+	u32 tx_io_data1;/* 0x28 */
 	u32 tx_tsvl0;	/* 0x2c */
 	u32 tx_tsvh0;	/* 0x30 */
 	u32 tx_tsvl1;	/* 0x34 */

@@ -141,33 +141,33 @@ struct sunxi_sramc_regs {
 
 #define EMAC_MAC_IPGT		0x15
 
-#define EMAC_MAC_NBTB_IPG1	0xC
+#define EMAC_MAC_NBTB_IPG1	0xc
 #define EMAC_MAC_NBTB_IPG2	0x12
 
 #define EMAC_MAC_CW		0x37
-#define EMAC_MAC_RM		0xF
+#define EMAC_MAC_RM		0xf
 
 #define EMAC_MAC_MFL		0x0600
 
 /* Receive status */
-#define EMAC_CRCERR		(1 << 4)
-#define EMAC_LENERR		(3 << 5)
+#define EMAC_CRCERR		(0x1 << 4)
+#define EMAC_LENERR		(0x3 << 5)
 
 #define DMA_CPU_TRRESHOLD	2000
 
-struct wemac_eth_dev {
+struct emac_eth_dev {
 	u32 speed;
 	u32 duplex;
 	u32 phy_configured;
 	int link_printed;
 };
 
-struct wemac_rxhdr {
+struct emac_rxhdr {
 	s16 rx_len;
 	u16 rx_status;
 };
 
-static void wemac_inblk_32bit(void *reg, void *data, int count)
+static void emac_inblk_32bit(void *reg, void *data, int count)
 {
 	int cnt = (count + 3) >> 2;
 

@@ -181,7 +181,7 @@ static void wemac_inblk_32bit(void *reg, void *data, int count)
 	}
 }
 
-static void wemac_outblk_32bit(void *reg, void *data, int count)
+static void emac_outblk_32bit(void *reg, void *data, int count)
 {
 	int cnt = (count + 3) >> 2;
 

@@ -194,14 +194,12 @@ static void wemac_outblk_32bit(void *reg, void *data, int count)
 	}
 }
 
-/*
- * Read a word from phyxcer
- */
-static int wemac_phy_read(const char *devname, unsigned char addr,
+/* Read a word from phyxcer */
+static int emac_phy_read(const char *devname, unsigned char addr,
 			  unsigned char reg, unsigned short *value)
 {
 	struct eth_device *dev = eth_get_dev_by_name(devname);
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	/* issue the phy address and reg */
 	writel(addr << 8 | reg, &regs->mac_madr);

@@ -221,14 +219,12 @@ static int wemac_phy_read(const char *devname, unsigned char addr,
 	return 0;
 }
 
-/*
- * Write a word to phyxcer
- */
-static int wemac_phy_write(const char *devname, unsigned char addr,
+/* Write a word to phyxcer */
+static int emac_phy_write(const char *devname, unsigned char addr,
 			   unsigned char reg, unsigned short value)
 {
 	struct eth_device *dev = eth_get_dev_by_name(devname);
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	/* issue the phy address and reg */
 	writel(addr << 8 | reg, &regs->mac_madr);

@@ -250,7 +246,7 @@ static int wemac_phy_write(const char *devname, unsigned char addr,
 
 static void emac_setup(struct eth_device *dev)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 	u32 reg_val;
 	u16 phy_val;
 	u32 duplex_flag;

@@ -266,7 +262,7 @@ static void emac_setup(struct eth_device *dev)
 	writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
 
 	/* Set MAC CTL1 */
-	wemac_phy_read(dev->name, 1, 0, &phy_val);
+	emac_phy_read(dev->name, 1, 0, &phy_val);
 	debug("PHY SETUP, reg 0 value: %x\n", phy_val);
 	duplex_flag = !!(phy_val & (1 << 8));
 

@@ -288,9 +284,9 @@ static void emac_setup(struct eth_device *dev)
 	writel(EMAC_MAC_MFL, &regs->mac_maxf);
 }
 
-static void wemac_reset(struct eth_device *dev)
+static void emac_reset(struct eth_device *dev)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	debug("resetting device\n");
 

@@ -302,10 +298,10 @@ static void wemac_reset(struct eth_device *dev)
 	udelay(200);
 }
 
-static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
+static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-	struct wemac_eth_dev *priv = dev->priv;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+	struct emac_eth_dev *priv = dev->priv;
 	u16 phy_reg;
 
 	/* Init EMAC */

@@ -317,10 +313,7 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 	/* Init MAC */
 
 	/* Soft reset MAC */
-	clrbits_le32(&regs->mac_ctl0, 1 << 15);
-
-	/* Set MII clock */
-	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
+	clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
 
 	/* Clear RX counter */
 	writel(0x0, &regs->rx_fbc);

@@ -336,14 +329,14 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 
 	mdelay(1);
 
-	wemac_reset(dev);
+	emac_reset(dev);
 
 	/* PHY POWER UP */
-	wemac_phy_read(dev->name, 1, 0, &phy_reg);
-	wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
+	emac_phy_read(dev->name, 1, 0, &phy_reg);
+	emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
 	mdelay(1);
 
-	wemac_phy_read(dev->name, 1, 0, &phy_reg);
+	emac_phy_read(dev->name, 1, 0, &phy_reg);
 
 	priv->speed = miiphy_speed(dev->name, 0);
 	priv->duplex = miiphy_duplex(dev->name, 0);

@@ -357,11 +350,11 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 
 	/* Set EMAC SPEED depend on PHY */
 	clrsetbits_le32(&regs->mac_supp, 1 << 8,
-			((phy_reg & (1 << 13)) >> 13) << 8);
+			((phy_reg & (0x1 << 13)) >> 13) << 8);
 
 	/* Set duplex depend on phy */
 	clrsetbits_le32(&regs->mac_ctl1, 1 << 0,
-			((phy_reg & (1 << 8)) >> 8) << 0);
+			((phy_reg & (0x1 << 8)) >> 8) << 0);
 
 	/* Enable RX/TX */
 	setbits_le32(&regs->ctl, 0x7);

@@ -369,15 +362,15 @@ static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
 	return 0;
 }
 
-static void sunxi_wemac_eth_halt(struct eth_device *dev)
+static void sunxi_emac_eth_halt(struct eth_device *dev)
 {
 	/* Nothing to do here */
 }
 
-static int sunxi_wemac_eth_recv(struct eth_device *dev)
+static int sunxi_emac_eth_recv(struct eth_device *dev)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
-	struct wemac_rxhdr rxhdr;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+	struct emac_rxhdr rxhdr;
 	u32 rxcount;
 	u32 reg_val;
 	int rx_len;

@@ -386,8 +379,7 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 
 	/* Check packet ready or not */
 
-	/*
-	 * Race warning: The first packet might arrive with
+	/* Race warning: The first packet might arrive with
 	 * the interrupts disabled, but the second will fix
 	 */
 	rxcount = readl(&regs->rx_fbc);

@@ -401,26 +393,25 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 	reg_val = readl(&regs->rx_io_data);
 	if (reg_val != 0x0143414d) {
 		/* Disable RX */
-		clrbits_le32(&regs->ctl, 1 << 2);
+		clrbits_le32(&regs->ctl, 0x1 << 2);
 
 		/* Flush RX FIFO */
-		setbits_le32(&regs->rx_ctl, 1 << 3);
-		while (readl(&regs->rx_ctl) & (1 << 3))
+		setbits_le32(&regs->rx_ctl, 0x1 << 3);
+		while (readl(&regs->rx_ctl) & (0x1 << 3))
 			;
 
 		/* Enable RX */
-		setbits_le32(&regs->ctl, 1 << 2);
+		setbits_le32(&regs->ctl, 0x1 << 2);
 
 		return 0;
 	}
 
-	/*
-	 * A packet ready now
+	/* A packet ready now
 	 * Get status/length
 	 */
 	good_packet = 1;
 
-	wemac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
+	emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
 
 	rx_len = rxhdr.rx_len;
 	rx_status = rxhdr.rx_status;

@@ -440,13 +431,13 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 			printf("length error\n");
 	}
 
-	/* Move data from WEMAC */
+	/* Move data from EMAC */
 	if (good_packet) {
 		if (rx_len > DMA_CPU_TRRESHOLD) {
 			printf("Received packet is too big (len=%d)\n", rx_len);
 		} else {
-			wemac_inblk_32bit((void *)&regs->rx_io_data,
-					  NetRxPackets[0], rx_len);
+			emac_inblk_32bit((void *)&regs->rx_io_data,
+					 NetRxPackets[0], rx_len);
 
 			/* Pass to upper layer */
 			NetReceive(NetRxPackets[0], rx_len);

@@ -457,15 +448,15 @@ static int sunxi_wemac_eth_recv(struct eth_device *dev)
 	return 0;
 }
 
-static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
+static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
 {
-	struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
+	struct emac_regs *regs = (struct emac_regs *)dev->iobase;
 
 	/* Select channel 0 */
 	writel(0, &regs->tx_ins);
 
 	/* Write packet */
-	wemac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
+	emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
 
 	/* Set TX len */
 	writel(len, &regs->tx_pl0);

@@ -476,50 +467,55 @@ static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
 	return 0;
 }
 
-int sunxi_wemac_initialize(void)
+int sunxi_emac_initialize(void)
 {
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_sramc_regs *sram =
 		(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
+	struct emac_regs *regs =
+		(struct emac_regs *)SUNXI_EMAC_BASE;
 	struct eth_device *dev;
-	struct wemac_eth_dev *priv;
+	struct emac_eth_dev *priv;
 	int pin;
 
 	dev = malloc(sizeof(*dev));
 	if (dev == NULL)
 		return -ENOMEM;
 
-	priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
+	priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
 	if (!priv) {
 		free(dev);
 		return -ENOMEM;
 	}
 
 	memset(dev, 0, sizeof(*dev));
-	memset(priv, 0, sizeof(struct wemac_eth_dev));
+	memset(priv, 0, sizeof(struct emac_eth_dev));
 
 	/* Map SRAM to EMAC */
 	setbits_le32(&sram->ctrl1, 0x5 << 2);
 
 	/* Configure pin mux settings for MII Ethernet */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
-		sunxi_gpio_set_cfgpin(pin, 2);
+		sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
 
 	/* Set up clock gating */
-	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
+	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+
+	/* Set MII clock */
+	clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
 
-	dev->iobase = SUNXI_EMAC_BASE;
+	dev->iobase = (int)regs;
 	dev->priv = priv;
-	dev->init = sunxi_wemac_eth_init;
-	dev->halt = sunxi_wemac_eth_halt;
-	dev->send = sunxi_wemac_eth_send;
-	dev->recv = sunxi_wemac_eth_recv;
-	strcpy(dev->name, "wemac");
+	dev->init = sunxi_emac_eth_init;
+	dev->halt = sunxi_emac_eth_halt;
+	dev->send = sunxi_emac_eth_send;
+	dev->recv = sunxi_emac_eth_recv;
+	strcpy(dev->name, "emac");
 
 	eth_register(dev);
 
-	miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
+	miiphy_register(dev->name, emac_phy_read, emac_phy_write);
 
 	return 0;
 }

include/netdev.h +1 -1

index 63481ec..e45dd7a 100644
@@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis);
 int skge_initialize(bd_t *bis);
 int smc91111_initialize(u8 dev_num, int base_addr);
 int smc911x_initialize(u8 dev_num, int base_addr);
+int sunxi_emac_initialize(bd_t *bis);
 int sunxi_gmac_initialize(bd_t *bis);
-int sunxi_wemac_initialize(bd_t *bis);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);

From: Chen-Yu Tsai <[email protected]>

Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII phy together with the GMAC nic found in the A20 SoC, add support for this (this will get used when we add these boards in a later patch).

Quoted 5 lines · Hans de Goede

From: Chen-Yu Tsai <[email protected]>

Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII phy together with the GMAC nic found in the A20 SoC, add support for this (this will get used when we add these boards in a later patch).

FYI I've got a cubieboard2 patch in the works which will use this (I've got a very similar patch locally, I shall rebase onto this).

Note I've added myself as board-maintainer for the cubietruck

since you did
not add yourself, feel free to submit a patch to make you the maintainer instead if you want :)

Quoted 1 line · Hans de Goede

Note I've added myself as board-maintainer for the cubietruck

Which patch was that? I noticed a bunch of boards.cfg which weren't described in the commit logs.

Quoted 1 line · Hans de Goede

Note I've added myself as board-maintainer for the cubietruck

Which patch was that? I noticed a bunch of boards.cfg which weren't described in the commit logs.

Quoted 4 lines

since you did
not add yourself, feel free to submit a patch to make you the maintainer instead if you want :)

Is co-maintainership allowed?

Hi,

Quoted 3 lines · Ian Campbell

Quoted 1 line · Hans de Goede

Note I've added myself as board-maintainer for the cubietruck

Quoted 2 lines

Which patch was that? I noticed a bunch of boards.cfg which weren't described in the commit logs.

In the "sunxi: Add axp209 pmic support" patch, where the commit logs says:

While changing the boards.cfg lines for the Cubietruck, add myself as board maintainer for the Cubietruck.

Quoted 5 lines

Quoted 3 lines

since you did
not add yourself, feel free to submit a patch to make you the maintainer instead if you want :)

Is co-maintainership allowed?

Looking at other boards, yes. It seems the format for co-maintainership would be putting something like this in the last column:

Hans de Goede <[email protected]>:Ian Campbell <[email protected]>

p.s.

Any chance you could review the rest of this series ?

Quoted 9 lines · Hans de Goede

Hi,

Quoted 5 lines · Ian Campbell

Quoted 1 line · Hans de Goede

Note I've added myself as board-maintainer for the cubietruck

Which patch was that? I noticed a bunch of boards.cfg which weren't described in the commit logs.

Quoted 5 lines

In the "sunxi: Add axp209 pmic support" patch, where the commit logs says:

While changing the boards.cfg lines for the Cubietruck, add myself as board maintainer for the Cubietruck.

Yes, I found it later. It was all the other boards.cfg changes which weren't mentioned in their respective logs ;-)

Quoted 7 lines

Quoted 6 lines

Quoted 4 lines

since you did
not add yourself, feel free to submit a patch to make you the maintainer instead if you want :)

Is co-maintainership allowed?

Quoted 4 lines

Looking at other boards, yes. It seems the format for co-maintainership would be putting something like this in the last column:

Hans de Goede <[email protected]>:Ian Campbell <[email protected]>

Let's do that then, at least for the boards which we both have/want to support (for me that is cubieboard2 and cubietruck for the moment).

Quoted 4 lines

p.s.

Any chance you could review the rest of this series ?

Yep, I just did the easy bits which fitted into the time I had available yesterday. I'll try and make time for the more involved bits soon.

Hi,

Quoted 16 lines · Ian Campbell

Quoted 14 lines · Hans de Goede

Hi,

Quoted 5 lines · Ian Campbell

Quoted 1 line · Hans de Goede

Note I've added myself as board-maintainer for the cubietruck

Which patch was that? I noticed a bunch of boards.cfg which weren't described in the commit logs.

In the "sunxi: Add axp209 pmic support" patch, where the commit logs says:

While changing the boards.cfg lines for the Cubietruck, add myself as board maintainer for the Cubietruck.

Quoted 2 lines

Yes, I found it later. It was all the other boards.cfg changes which weren't mentioned in their respective logs ;-)

Right, so for v2 of this series you want me to add a line to the log like this ? :

And enable AXP209 support on boards which have this pmic.

Quoted 9 lines

Quoted 9 lines

Quoted 5 lines

Quoted 3 lines

since you did
not add yourself, feel free to submit a patch to make you the maintainer instead if you want :)

Is co-maintainership allowed?

Looking at other boards, yes. It seems the format for co-maintainership would be putting something like this in the last column:

Quoted 4 lines

Quoted 1 line

Hans de Goede <[email protected]>:Ian Campbell <[email protected]>

Let's do that then, at least for the boards which we both have/want to support (for me that is cubieboard2 and cubietruck for the moment).

Works for me, shall I adjust things in v2 of my series to add you at the same time I add myself for the cubietruck ?

Also please add me as co-maintainer in the cubieboard2 patch you're working on.