mx6: SPL NAND support
v4 cover mx6: SPL NAND support
This series adds some necessary framework for IMX6 SPL support. The series includes support for NAND SPL and has been tested with MMC as well. I have tested this on five differing Ventana baseboards with a variety of memory (32bit 512MB, 32bit 1024MB, 64bit 1024MB) and CPU configurations (IMX6Q, IMX6DL, IMX6S).
This is based on top of Mashahiro Yamada's patch that consolidates arch/arm/include/asm/arch-*/spl.h [1]
v4:
- removed unnecessary parens from a return
- removed patch 1 as it has been merged upstream
v3:
- re-ordered calls in board_init_f
- replace imx_iomux_v3_setup_multiple_pads_array with additional intelligence in imx_iomux_v3_setup_multiple_pads
- added ifdef's around cpu specific mmdc iocfg functions for code-reduction with single-variant board configs
- added checks for IMX6D
- added Freescale copyright to boot device support function
- fixed typo s/IMX6SLD/IMX6SDL
- encorporated cleanups in mxs_nand_spl.c per feedback
v2:
- use compatible linker script instead of creating new one
- remove structure passing data from SPL to u-boot
- remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total
- adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD
- move boot dev detection into imx-common/spl.c
- move macros for using pinmux array into iomux-v3.h
- remove missing/unnecessary include
- revert mtdparts change
- use get_ram_size() to detect memory
- add support for MX6SOLO and MX6DUAL
- set CS0_END for 4GB so get_ram_size() works
- updated DDR3 calibration values for ventana boards
- fixed build issue - only compile spl if doing spl build
- fixed line length issue in README
- remove CONFIG_SPL* conditions and conditionally compile instead
- removed prints for CPU type and DRAM size/width - uboot will print these l
- removed unused gw_ventana_spl.cfg
- use common read_eeprom function
- added MMC support to SPL
- added Masahiro Yamada's boot mode consolidation patch
http://patchwork.ozlabs.org/patch/341817 and rebase on top of it
[1] http://patchwork.ozlabs.org/patch/341817/
Tim Harvey (10):
spl: nand: add support for mxs nand
mx6: add common SPL configuration
mx6: add boot device support for SPL
imx: add comments and remove unused struct fields
mx6: add structs for mmdc and ddr iomux registers
mx6: add mmdc configuration for MX6Q/MX6DL
imx: iomux: add macros to setup iomux for multiple SoC types
imx: ventana: split read_eeprom into standalone file
imx: ventana: auto-configure for IMX6Q vs IMX6DL
imx: ventana: switch to SPL
arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 490 +++++++++++++++++++++++ arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/cpu.c | 16 +- arch/arm/imx-common/iomux-v3.c | 16 +- arch/arm/imx-common/spl.c | 81 ++++ arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231 +++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 25 ++ board/gateworks/gw_ventana/Makefile | 3 +- board/gateworks/gw_ventana/README | 92 +++-- board/gateworks/gw_ventana/eeprom.c | 89 +++++ board/gateworks/gw_ventana/gw_ventana.c | 597 +++++++++++++++------------- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 +++++++++++++++++++ board/gateworks/gw_ventana/ventana_eeprom.h | 11 + boards.cfg | 6 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 +++++++++++ include/configs/gw_ventana.h | 11 + include/configs/imx6_spl.h | 71 ++++ 20 files changed, 2065 insertions(+), 342 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c create mode 100644 arch/arm/imx-common/spl.c create mode 100644 board/gateworks/gw_ventana/eeprom.c create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c create mode 100644 drivers/mtd/nand/mxs_nand_spl.c create mode 100644 include/configs/imx6_spl.h
Signature · 1 line
1.8.3.2
PATCH v4 1/10 spl: nand: add support for mxs nand
This utilizes existing mxs_nand support layer to provide a method to load an image off nand for SPL. The flash device will be detected in order to support multiple flash devices instead of having layout hard coded at build time.
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Cc Scott Wood <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
---
v4:
- removed unnecessary parens from return
v3:
- removed NAND_NCE and NAND_CTRL_CHANGE unused by mxc_nand.c
- return specific error types on errors
- remove register keyword - let compiler do optimizations
v2:
- remove dependence on mtdpart, mtdcore, nand_util, nand_ecc, nand_base and nand_bbt to bring SPL down in size. This reduced codesize by about 32k where now mxs_spl_nand is about 12k total.
--- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 231 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 232 insertions(+) create mode 100644 drivers/mtd/nand/mxs_nand_spl.c
drivers/mtd/nand/Makefile +1 -0
@@ -68,5 +68,6 @@ else # minimal SPL drivers obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o +obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o endif # drivers
drivers/mtd/nand/mxs_nand_spl.c new file +231 -0
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Signature · 1 line
1.8.3.2
PATCH v4 2/10 mx6: add common SPL configuration
In reply to Tim HarveyAdd a common header which can hopefully be shared amon imx6 SPL users
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
Acked-by Stefano Babic <[email protected]>
Acked-by Nikita Kiryanov <[email protected]>
---
v4:
- no changes
v3:
- fixed typo s/IMX6SLD/IMX6SDL
- add acks from Stefano and Nikita
v2:
- adjust CONFIG_SPL_TEXT_BASE, CONFIG_SPL_STACK and CONFIG_SPL_MAX_SIZE to accomodate the IMX6SOLO/DUALLITE which have half the iRAM of the IMX6DUAL/IMX6QUAD
--- include/configs/imx6_spl.h | 71 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 include/configs/imx6_spl.h
include/configs/imx6_spl.h new file +71 -0
@@ -0,0 +1,71 @@ +/* +* Copyright (C) 2014 Gateworks Corporation +* Author: Tim Harvey <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +#ifndef __IMX6_SPL_CONFIG_H +#define __IMX6_SPL_CONFIG_H + +#ifdef CONFIG_SPL + +#define CONFIG_SPL_FRAMEWORK + +/* +* see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals: +* - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF +* - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well +* - BOOT ROM stack is at 0x0091FFB8 +* - if icache/dcache is enabled (eFuse/strapping controlled) then the +* IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to +* fit between 0x00907000 and 0x00918000. +* - Additionally the BOOT ROM loads what they consider the firmware image +* which consists of a 4K header in front of us that contains the IVT, DCD +* and some padding thus 'our' max size is really 0x00908000 - 0x00918000 +* or 64KB +*/ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_TEXT_BASE 0x00908000 +#define CONFIG_SPL_MAX_SIZE (64 * 1024) +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" +#define CONFIG_SPL_STACK 0x0091FFB8 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT + +/* NAND support */ +#if defined(CONFIG_SPL_NAND_SUPPORT ) +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_DMA_SUPPORT +#endif + +/* MMC support */ +#if defined(CONFIG_SPL_MMC_SUPPORT ) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138/* offset 69KB */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800/* 400 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024) +#endif + +/* SATA support */ +#if defined(CONFIG_SPL_SATA_SUPPORT ) +#define CONFIG_SPL_SATA_BOOT_DEVICE 0 +#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 +#endif + +/* Define the payload for FAT/EXT support */ +#if defined(CONFIG_SPL_FAT_SUPPORT ) || defined(CONFIG_SPL_EXT_SUPPORT ) +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_LIBDISK_SUPPORT +#endif + +#define CONFIG_SPL_BSS_START_ADDR 0x18200000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000/* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000/* 50 MB */ +#define CONFIG_SYS_TEXT_BASE 0x17800000 +#endif + +#endif
Signature · 1 line
1.8.3.2
PATCH v4 3/10 mx6: add boot device support for SPL
In reply to Tim HarveyAdd a common spl.c file to support boot device functions needed for SPL such as detecting the boot device.
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
Acked-by Nikita Kiryanov <[email protected]>
---
v4:
- added Nikita's Ack
v3:
- added Freescale copyright
v2:
- re-base on top of Masahiro Yamada's consolidation patch:
http://patchwork.ozlabs.org/patch/341817/
- moved spl_boot_device() and get_boot_mode() into own common imx spl.c file
- use mem-mapped structure for smbr reg access
--- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/spl.c | 81 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/arm/imx-common/spl.c
arch/arm/imx-common/Makefile +1 -0
@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) obj-y += misc.o +obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o
arch/arm/imx-common/spl.c new file +81 -0
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Signature · 1 line
1.8.3.2
PATCH v4 4/10 imx: add comments and remove unused struct fields
In reply to Tim HarveyAdd comment block for the imx_ddr_size function and remove the extra unused fields from struct esd_mmdc_regs which are also not common between IMX53 and IMX6.
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
Acked-by Stefano Babic <[email protected]>
Acked-by Nikita Kiryanov <[email protected]>
---
v4:
- added Nikita's Ack
v3:
- fixed doxygen-style comment block
- added Stefano's Ack
v2:
- new patch in series
--- arch/arm/imx-common/cpu.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-)
arch/arm/imx-common/cpu.c +7 -9
@@ -58,6 +58,7 @@ char *get_reset_cause(void)static const unsigned char col_lookup[] = {9 ,10 ,11 ,8 ,12 ,9 ,9 ,9 };static const unsigned char bank_lookup[] = {3 ,2 }; +/* these MMDC registers are common to the IMX53 and IMX6 */ struct esd_mmdc_regs {uint32_t ctl;uint32_t pdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {uint32_t cfg1;uint32_t cfg2;uint32_t misc; -uint32_t scr; -uint32_t ref; -uint32_t rsvd1; -uint32_t rsvd2; -uint32_t rwd; -uint32_t or; -uint32_t mrr; -uint32_t cfg3lp; -uint32_t mr4; };#define ESD_MMDC_CTL_GET_ROW (mdctl) ((ctl >> 24) & 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {#define ESD_MMDC_CTL_GET_CS1 (mdctl) ((ctl >> 30) & 1)#define ESD_MMDC_MISC_GET_BANK (mdmisc) ((misc >> 5) & 1) +/* +* imx_ddr_size - return size in bytes of DRAM according MMDC config +* The MMDC MDCTL register holds the number of bits for row, col, and data +* width and the MMDC MDMISC register holds the number of banks. Combine +* all these bits to determine the meme size the MMDC has been configured for +*/ unsigned imx_ddr_size (void ) {struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE ;
Signature · 1 line
1.8.3.2
PATCH v4 5/10 mx6: add structs for mmdc and ddr iomux registers
In reply to Tim HarveyAdd memory-mapped structures for MMDC iomux and configuration. Note that whi the MMDC configuration registers are common between the IMX6DQ (IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux registers differ. This requires two sets of structures.
Add structures to describe DDR3 device information, system information (memory layout, etc), and MMDC calibration registers that can be used to configure the MMDC dynamically.
We define these structures for SPL builds instead of including mx6q-ddr.h an mx6dl-ddr.h which use the same namespace and are only useful for imximage cf files.
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
Acked-by Nikita Kiryanov <[email protected]>
---
v4:
- added Nikita's Ack
v3:
- moved portions into following patch
v2:
- split out from original mmdc configuration patch
- only define for SPL build
- do not include mx6q-ddr.h and mx6dl-ddr.h for SPL build - these use the same namespace and are only useful for imximage cfg files
--- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 159 ++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+)
arch/arm/include/asm/arch-mx6/mx6-ddr.h +159 -0
@@ -6,6 +6,7 @@#ifndef __ASM_ARCH_MX6_DDR_H__#define __ASM_ARCH_MX6_DDR_H__ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_MX6Q #include "mx6q-ddr.h" #else
@@ -15,6 +16,164 @@#error "Please select cpu"#endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ +#else + +/* MMDC P0/P1 Registers */ +struct mmdc_p_regs { +u32 mdctl; +u32 mdpdc; +u32 mdotc; +u32 mdcfg0; +u32 mdcfg1; +u32 mdcfg2; +u32 mdmisc; +u32 mdscr; +u32 mdref; +u32 res1[2 ]; +u32 mdrwd; +u32 mdor; +u32 res2[3 ]; +u32 mdasp; +u32 res3[240 ]; +u32 mapsr; +u32 res4[254 ]; +u32 mpzqhwctrl; +u32 res5[2 ]; +u32 mpwldectrl0; +u32 mpwldectrl1; +u32 res6; +u32 mpodtctrl; +u32 mprddqby0dl; +u32 mprddqby1dl; +u32 mprddqby2dl; +u32 mprddqby3dl; +u32 res7[4 ]; +u32 mpdgctrl0; +u32 mpdgctrl1; +u32 res8; +u32 mprddlctl; +u32 res9; +u32 mpwrdlctl; +u32 res10[25 ]; +u32 mpmur0; +}; + +/* +* MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) +*/ +#define MX6DQ_IOM_DDR_BASE 0x020e0500 +struct mx6dq_iomux_ddr_regs { +u32 res1[3 ]; +u32 dram_sdqs5; +u32 dram_dqm5; +u32 dram_dqm4; +u32 dram_sdqs4; +u32 dram_sdqs3; +u32 dram_dqm3; +u32 dram_sdqs2; +u32 dram_dqm2; +u32 res2[16 ]; +u32 dram_cas; +u32 res3[2 ]; +u32 dram_ras; +u32 dram_reset; +u32 res4[2 ]; +u32 dram_sdclk_0; +u32 dram_sdba2; +u32 dram_sdcke0; +u32 dram_sdclk_1; +u32 dram_sdcke1; +u32 dram_sdodt0; +u32 dram_sdodt1; +u32 res5; +u32 dram_sdqs0; +u32 dram_dqm0; +u32 dram_sdqs1; +u32 dram_dqm1; +u32 dram_sdqs6; +u32 dram_dqm6; +u32 dram_sdqs7; +u32 dram_dqm7; +}; + +#define MX6DQ_IOM_GRP_BASE 0x020e0700 +struct mx6dq_iomux_grp_regs { +u32 res1[18 ]; +u32 grp_b7ds; +u32 grp_addds; +u32 grp_ddrmode_ctl; +u32 res2; +u32 grp_ddrpke; +u32 res3[6 ]; +u32 grp_ddrmode; +u32 res4[3 ]; +u32 grp_b0ds; +u32 grp_b1ds; +u32 grp_ctlds; +u32 res5; +u32 grp_b2ds; +u32 grp_ddr_type; +u32 grp_b3ds; +u32 grp_b4ds; +u32 grp_b5ds; +u32 grp_b6ds; +}; + +#define MX6SDL_IOM_DDR_BASE 0x020e0400 +struct mx6sdl_iomux_ddr_regs { +u32 res1[25 ]; +u32 dram_cas; +u32 res2[2 ]; +u32 dram_dqm0; +u32 dram_dqm1; +u32 dram_dqm2; +u32 dram_dqm3; +u32 dram_dqm4; +u32 dram_dqm5; +u32 dram_dqm6; +u32 dram_dqm7; +u32 dram_ras; +u32 dram_reset; +u32 res3[2 ]; +u32 dram_sdba2; +u32 dram_sdcke0; +u32 dram_sdcke1; +u32 dram_sdclk_0; +u32 dram_sdclk_1; +u32 dram_sdodt0; +u32 dram_sdodt1; +u32 dram_sdqs0; +u32 dram_sdqs1; +u32 dram_sdqs2; +u32 dram_sdqs3; +u32 dram_sdqs4; +u32 dram_sdqs5; +u32 dram_sdqs6; +u32 dram_sdqs7; +}; + +#define MX6SDL_IOM_GRP_BASE 0x020e0700 +struct mx6sdl_iomux_grp_regs { +u32 res1[18 ]; +u32 grp_b7ds; +u32 grp_addds; +u32 grp_ddrmode_ctl; +u32 grp_ddrpke; +u32 res2[2 ]; +u32 grp_ddrmode; +u32 grp_b0ds; +u32 res3; +u32 grp_ctlds; +u32 grp_b1ds; +u32 grp_ddr_type; +u32 grp_b2ds; +u32 grp_b3ds; +u32 grp_b4ds; +u32 grp_b5ds; +u32 res4; +u32 grp_b6ds; +}; +#endif /* CONFIG_SPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000#define MX6_MMDC_P0_MDPDC 0x021b0004
Signature · 1 line
1.8.3.2
PATCH v4 6/10 mx6: add mmdc configuration for MX6Q/MX6DL
In reply to Tim Harvey- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and chip-specific data
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
---
v4:
- added delay following configure to allow ZQ calibration to complete
- update MMDC configuration to match Freescale RM
v3:
- added ifdef's around cpu specific iocfg functions for code-reduction with single-variant board configs
- moved portions from previous patch here
- added check for IMX6D
v2:
- split out mmdc and iomux structs into separate patch
--- arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 490 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/mx6-ddr.h | 72 +++++ 3 files changed, 563 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c
arch/arm/cpu/armv7/mx6/Makefile +1 -0
@@ -8,4 +8,5 @@ # obj-y := soc.o clock.o +obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_SECURE_BOOT) += hab.o
arch/arm/cpu/armv7/mx6/ddr.c new file +490 -0
490 lines not on this page · raw message
arch/arm/include/asm/arch-mx6/mx6-ddr.h +72 -0
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Signature · 1 line
1.8.3.2
PATCH v4 7/10 imx: iomux: add macros to setup iomux for multiple SoC types
In reply to Tim HarveyAllow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list and add macros for declaring the pad_list that take into account the SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL iomux).
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
---
v4:
- no changes
v3:
- remove commit msg 2nd paragrap about prior approaches
- re-work to avoid needing to add a new function by making imx_iomux_v3_setup_multiple_pads more intelligent and adding macros that depend on SoC type support
v2:
- moved macros for declaring and using structs for array variant
- removed non-related whitespace cleanup
--- arch/arm/imx-common/iomux-v3.c | 16 ++++++++++++++-- arch/arm/include/asm/imx-common/iomux-v3.h | 25 +++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-)
arch/arm/imx-common/iomux-v3.c +14 -2
@@ -11,6 +11,7 @@#include <common.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <asm/imx-common/iomux-v3.h> static void *base = (void *)IOMUXC_BASE_ADDR ;
@@ -54,12 +55,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)#endif } +/* configures a list of pads within declared with IOMUX_PADS macro */ void imx_iomux_v3_setup_multiple_pads (iomux_v3_cfg_t const *pad_list,unsigned count) {iomux_v3_cfg_t const *p = pad_list; +int stride;int i; -for (i =0 ; i < count; i++) -imx_iomux_v3_setup_pad (*p++); +#if defined(CONFIG_MX6QDL ) + stride =2 ; +if (!is_cpu_type (MXC_CPU_MX6Q ) && !is_cpu_type (MXC_CPU_MX6D )) + p +=1 ; +#else + stride =1 ; +#endif +for (i =0 ; i < count; i++) { +imx_iomux_v3_setup_pad (*p); + p += stride; + } }
arch/arm/include/asm/imx-common/iomux-v3.h +25 -0
@@ -175,4 +175,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);void imx_iomux_v3_setup_multiple_pads (iomux_v3_cfg_t const *pad_list,unsigned count); +/* macros for declaring and using pinmux array */ +#if defined(CONFIG_MX6QDL ) +#define IOMUX_PADS (x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_IOMUX_PAD (def) \ +if (is_cpu_type(MXC_CPU_MX6Q)) { \ + imx_iomux_v3_setup_pad(MX6Q_##def); \ +} else { \ + imx_iomux_v3_setup_pad(MX6DL_##def); \ +} +#define SETUP_IOMUX_PADS (x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) +#elif defined(CONFIG_MX6Q ) || defined(CONFIG_MX6D ) +#define IOMUX_PADS (x) MX6Q_##x +#define SETUP_IOMUX_PAD (def) \ + imx_iomux_v3_setup_pad(MX6Q_##def); +#define SETUP_IOMUX_PADS (x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#else +#define IOMUX_PADS (x) MX6DL_##x +#define SETUP_IOMUX_PAD (def) \ + imx_iomux_v3_setup_pad(MX6DL_##def); +#define SETUP_IOMUX_PADS (x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#endif +#endif /* __MACH_IOMUX_V3_H__*/
Signature · 1 line
1.8.3.2
PATCH v4 8/10 imx: ventana: split read_eeprom into standalone file
In reply to Tim HarveySplit the read_eeprom function out so that it can be shared (ie with SPL)
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
---
v4:
- no changes
v3:
- no changes
v2:
- new patch in series
--- board/gateworks/gw_ventana/Makefile | 2 +- board/gateworks/gw_ventana/eeprom.c | 89 +++++++++++++++++++++++++++++ board/gateworks/gw_ventana/gw_ventana.c | 89 +---------------------------- board/gateworks/gw_ventana/ventana_eeprom.h | 11 ++++ 4 files changed, 102 insertions(+), 89 deletions(-) create mode 100644 board/gateworks/gw_ventana/eeprom.c
board/gateworks/gw_ventana/Makefile +1 -1
@@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := gw_ventana.o gsc.o +obj-y := gw_ventana.o gsc.o eeprom.o
board/gateworks/gw_ventana/eeprom.c new file +89 -0
89 lines not on this page · raw message
board/gateworks/gw_ventana/gw_ventana.c +1 -88
107 lines not on this page · raw message
board/gateworks/gw_ventana/ventana_eeprom.h +11 -0
@@ -103,4 +103,15 @@ enum { EECONFIG_RES15, }; +enum { + GW54proto,/* original GW5400-A prototype */ + GW51xx, + GW52xx, + GW53xx, + GW54xx, +GW_UNKNOWN , +}; + +int read_eeprom (int bus,struct ventana_board_info *); +#endif
Signature · 1 line
1.8.3.2
PATCH v4 9/10 imx: ventana: auto-configure for IMX6Q vs IMX6DL
In reply to Tim Harveyuse the new iomux function and a macros to create a multi-dimensional array of iomux values without duplicating the defintions.
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
---
v4:
- no changes
v3:
- replace use of imx_iomux_v3_setup_multiple_pads_array with imx_iomux_v3_setup_multiple_pads
v2:
- use macros that have been moved to iomux-v3.h
--- board/gateworks/gw_ventana/gw_ventana.c | 498 ++++++++++++++++++++------------ 1 file changed, 312 insertions(+), 186 deletions(-)
board/gateworks/gw_ventana/gw_ventana.c +312 -186
@@ -88,109 +88,149 @@ int board_type;/* UART1: Function varies per baseboard */ iomux_v3_cfg_t const uart1_pads[] = { -MX6_PAD_SD3_DAT6__UART1_RX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL ), -MX6_PAD_SD3_DAT7__UART1_TX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL ), +IOMUX_PADS (PAD_SD3_DAT6__UART1_RX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL )), +IOMUX_PADS (PAD_SD3_DAT7__UART1_TX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL )), };/* UART2: Serial Console */ iomux_v3_cfg_t const uart2_pads[] = { -MX6_PAD_SD4_DAT7__UART2_TX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL ), -MX6_PAD_SD4_DAT4__UART2_RX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL ), +IOMUX_PADS (PAD_SD4_DAT7__UART2_TX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL )), +IOMUX_PADS (PAD_SD4_DAT4__UART2_RX_DATA |MUX_PAD_CTRL (UART_PAD_CTRL )), };#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)/* I2C1: GSC */ -struct i2c_pads_info i2c_pad_info0 = { +struct i2c_pads_info mx6q_i2c_pad_info0 = { .scl = { - .i2c_mode =MX6_PAD_EIM_D21__I2C1_SCL |PC , - .gpio_mode =MX6_PAD_EIM_D21__GPIO3_IO21 |PC , + .i2c_mode =MX6Q_PAD_EIM_D21__I2C1_SCL |PC , + .gpio_mode =MX6Q_PAD_EIM_D21__GPIO3_IO21 |PC , .gp =IMX_GPIO_NR (3 ,21 ) }, .sda = { - .i2c_mode =MX6_PAD_EIM_D28__I2C1_SDA |PC , - .gpio_mode =MX6_PAD_EIM_D28__GPIO3_IO28 |PC , + .i2c_mode =MX6Q_PAD_EIM_D28__I2C1_SDA |PC , + .gpio_mode =MX6Q_PAD_EIM_D28__GPIO3_IO28 |PC , + .gp =IMX_GPIO_NR (3 ,28 ) + } +}; +struct i2c_pads_info mx6dl_i2c_pad_info0 = { + .scl = { + .i2c_mode =MX6DL_PAD_EIM_D21__I2C1_SCL |PC , + .gpio_mode =MX6DL_PAD_EIM_D21__GPIO3_IO21 |PC , + .gp =IMX_GPIO_NR (3 ,21 ) + }, + .sda = { + .i2c_mode =MX6DL_PAD_EIM_D28__I2C1_SDA |PC , + .gpio_mode =MX6DL_PAD_EIM_D28__GPIO3_IO28 |PC , .gp =IMX_GPIO_NR (3 ,28 ) } };/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ -struct i2c_pads_info i2c_pad_info1 = { +struct i2c_pads_info mx6q_i2c_pad_info1 = { .scl = { - .i2c_mode =MX6_PAD_KEY_COL3__I2C2_SCL |PC , - .gpio_mode =MX6_PAD_KEY_COL3__GPIO4_IO12 |PC , + .i2c_mode =MX6Q_PAD_KEY_COL3__I2C2_SCL |PC , + .gpio_mode =MX6Q_PAD_KEY_COL3__GPIO4_IO12 |PC , .gp =IMX_GPIO_NR (4 ,12 ) }, .sda = { - .i2c_mode =MX6_PAD_KEY_ROW3__I2C2_SDA |PC , - .gpio_mode =MX6_PAD_KEY_ROW3__GPIO4_IO13 |PC , + .i2c_mode =MX6Q_PAD_KEY_ROW3__I2C2_SDA |PC , + .gpio_mode =MX6Q_PAD_KEY_ROW3__GPIO4_IO13 |PC , + .gp =IMX_GPIO_NR (4 ,13 ) + } +}; +struct i2c_pads_info mx6dl_i2c_pad_info1 = { + .scl = { + .i2c_mode =MX6DL_PAD_KEY_COL3__I2C2_SCL |PC , + .gpio_mode =MX6DL_PAD_KEY_COL3__GPIO4_IO12 |PC , + .gp =IMX_GPIO_NR (4 ,12 ) + }, + .sda = { + .i2c_mode =MX6DL_PAD_KEY_ROW3__I2C2_SDA |PC , + .gpio_mode =MX6DL_PAD_KEY_ROW3__GPIO4_IO13 |PC , .gp =IMX_GPIO_NR (4 ,13 ) } };/* I2C3: Misc/Expansion */ -struct i2c_pads_info i2c_pad_info2 = { +struct i2c_pads_info mx6q_i2c_pad_info2 = { + .scl = { + .i2c_mode =MX6Q_PAD_GPIO_3__I2C3_SCL |PC , + .gpio_mode =MX6Q_PAD_GPIO_3__GPIO1_IO03 |PC , + .gp =IMX_GPIO_NR (1 ,3 ) + }, + .sda = { + .i2c_mode =MX6Q_PAD_GPIO_6__I2C3_SDA |PC , + .gpio_mode =MX6Q_PAD_GPIO_6__GPIO1_IO06 |PC , + .gp =IMX_GPIO_NR (1 ,6 ) + } +}; +struct i2c_pads_info mx6dl_i2c_pad_info2 = { .scl = { - .i2c_mode =MX6_PAD_GPIO_3__I2C3_SCL |PC , - .gpio_mode =MX6_PAD_GPIO_3__GPIO1_IO03 |PC , + .i2c_mode =MX6DL_PAD_GPIO_3__I2C3_SCL |PC , + .gpio_mode =MX6DL_PAD_GPIO_3__GPIO1_IO03 |PC , .gp =IMX_GPIO_NR (1 ,3 ) }, .sda = { - .i2c_mode =MX6_PAD_GPIO_6__I2C3_SDA |PC , - .gpio_mode =MX6_PAD_GPIO_6__GPIO1_IO06 |PC , + .i2c_mode =MX6DL_PAD_GPIO_6__I2C3_SDA |PC , + .gpio_mode =MX6DL_PAD_GPIO_6__GPIO1_IO06 |PC , .gp =IMX_GPIO_NR (1 ,6 ) } };/* MMC */ iomux_v3_cfg_t const usdhc3_pads[] = { -MX6_PAD_SD3_CLK__SD3_CLK |MUX_PAD_CTRL (USDHC_PAD_CTRL ), -MX6_PAD_SD3_CMD__SD3_CMD |MUX_PAD_CTRL (USDHC_PAD_CTRL ), -MX6_PAD_SD3_DAT0__SD3_DATA0 |MUX_PAD_CTRL (USDHC_PAD_CTRL ), -MX6_PAD_SD3_DAT1__SD3_DATA1 |MUX_PAD_CTRL (USDHC_PAD_CTRL ), -MX6_PAD_SD3_DAT2__SD3_DATA2 |MUX_PAD_CTRL (USDHC_PAD_CTRL ), -MX6_PAD_SD3_DAT3__SD3_DATA3 |MUX_PAD_CTRL (USDHC_PAD_CTRL ), -MX6_PAD_SD3_DAT5__GPIO7_IO00 |MUX_PAD_CTRL (NO_PAD_CTRL ),/* CD */ +IOMUX_PADS (PAD_SD3_CLK__SD3_CLK |MUX_PAD_CTRL (USDHC_PAD_CTRL )), +IOMUX_PADS (PAD_SD3_CMD__SD3_CMD |MUX_PAD_CTRL (USDHC_PAD_CTRL )), +IOMUX_PADS (PAD_SD3_DAT0__SD3_DATA0 |MUX_PAD_CTRL (USDHC_PAD_CTRL )), +IOMUX_PADS (PAD_SD3_DAT1__SD3_DATA1 |MUX_PAD_CTRL (USDHC_PAD_CTRL )), +IOMUX_PADS (PAD_SD3_DAT2__SD3_DATA2 |MUX_PAD_CTRL (USDHC_PAD_CTRL )), +IOMUX_PADS (PAD_SD3_DAT3__SD3_DATA3 |MUX_PAD_CTRL (USDHC_PAD_CTRL )), +/* CD */ +IOMUX_PADS (PAD_SD3_DAT5__GPIO7_IO00 |MUX_PAD_CTRL (NO_PAD_CTRL )), };/* ENET */ iomux_v3_cfg_t const enet_pads[] = { -MX6_PAD_ENET_MDIO__ENET_MDIO |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_ENET_MDC__ENET_MDC |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_TXC__RGMII_TXC |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_TD0__RGMII_TD0 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_TD1__RGMII_TD1 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_TD2__RGMII_TD2 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_TD3__RGMII_TD3 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_ENET_REF_CLK__ENET_TX_CLK |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_RXC__RGMII_RXC |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_RD0__RGMII_RD0 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_RD1__RGMII_RD1 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_RD2__RGMII_RD2 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_RD3__RGMII_RD3 |MUX_PAD_CTRL (ENET_PAD_CTRL ), -MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL |MUX_PAD_CTRL (ENET_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_MDIO__ENET_MDIO |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_ENET_MDC__ENET_MDC |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_TXC__RGMII_TXC |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_TD0__RGMII_TD0 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_TD1__RGMII_TD1 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_TD2__RGMII_TD2 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_TD3__RGMII_TD3 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_TX_CTL__RGMII_TX_CTL | +MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_ENET_REF_CLK__ENET_TX_CLK | +MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_RXC__RGMII_RXC |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_RD0__RGMII_RD0 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_RD1__RGMII_RD1 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_RD2__RGMII_RD2 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_RD3__RGMII_RD3 |MUX_PAD_CTRL (ENET_PAD_CTRL )), +IOMUX_PADS (PAD_RGMII_RX_CTL__RGMII_RX_CTL | +MUX_PAD_CTRL (ENET_PAD_CTRL )),/* PHY nRST */ -MX6_PAD_ENET_TXD0__GPIO1_IO30 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_TXD0__GPIO1_IO30 |MUX_PAD_CTRL (NO_PAD_CTRL )), };/* NAND */ iomux_v3_cfg_t const nfc_pads[] = { -MX6_PAD_NANDF_CLE__NAND_CLE |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_ALE__NAND_ALE |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_WP_B__NAND_WP_B |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_RB0__NAND_READY_B |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_CS0__NAND_CE0_B |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_SD4_CMD__NAND_RE_B |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_SD4_CLK__NAND_WE_B |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D0__NAND_DATA00 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D1__NAND_DATA01 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D2__NAND_DATA02 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D3__NAND_DATA03 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D4__NAND_DATA04 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D5__NAND_DATA05 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D6__NAND_DATA06 |MUX_PAD_CTRL (NO_PAD_CTRL ), -MX6_PAD_NANDF_D7__NAND_DATA07 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_NANDF_CLE__NAND_CLE |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_ALE__NAND_ALE |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_WP_B__NAND_WP_B |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_RB0__NAND_READY_B |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_CS0__NAND_CE0_B |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_SD4_CMD__NAND_RE_B |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_SD4_CLK__NAND_WE_B |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D0__NAND_DATA00 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D1__NAND_DATA01 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D2__NAND_DATA02 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D3__NAND_DATA03 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D4__NAND_DATA04 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D5__NAND_DATA05 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D6__NAND_DATA06 |MUX_PAD_CTRL (NO_PAD_CTRL )), +IOMUX_PADS (PAD_NANDF_D7__NAND_DATA07 |MUX_PAD_CTRL (NO_PAD_CTRL )), };#ifdef CONFIG_CMD_NAND
@@ -199,7 +239,7 @@ static void setup_gpmi_nand(void)struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR ;/* config gpmi nand iomux */ -imx_iomux_v3_setup_multiple_pads (nfc_pads,ARRAY_SIZE (nfc_pads)); +SETUP_IOMUX_PADS (nfc_pads);/* config gpmi and bch clock to 100 MHz */ clrsetbits_le32(&mxc_ccm->cs2cdr,
@@ -225,7 +265,7 @@ static void setup_gpmi_nand(void)static void setup_iomux_enet (void ) { -imx_iomux_v3_setup_multiple_pads (enet_pads,ARRAY_SIZE (enet_pads)); +SETUP_IOMUX_PADS (enet_pads);/* toggle PHY_RST# */ gpio_direction_output (GP_PHY_RST ,0 );
@@ -235,35 +275,36 @@ static void setup_iomux_enet(void)static void setup_iomux_uart (void ) { -imx_iomux_v3_setup_multiple_pads (uart1_pads,ARRAY_SIZE (uart1_pads)); -imx_iomux_v3_setup_multiple_pads (uart2_pads,ARRAY_SIZE (uart2_pads)); +SETUP_IOMUX_PADS (uart1_pads); +SETUP_IOMUX_PADS (uart2_pads); }#ifdef CONFIG_USB_EHCI_MX6 iomux_v3_cfg_t const usb_pads[] = { -MX6_PAD_GPIO_1__USB_OTG_ID |MUX_PAD_CTRL (DIO_PAD_CTRL ), -MX6_PAD_KEY_COL4__USB_OTG_OC |MUX_PAD_CTRL (DIO_PAD_CTRL ), -MX6_PAD_EIM_D22__GPIO3_IO22 |MUX_PAD_CTRL (DIO_PAD_CTRL ),/* OTG PWR */ +IOMUX_PADS (PAD_GPIO_1__USB_OTG_ID |MUX_PAD_CTRL (DIO_PAD_CTRL )), +IOMUX_PADS (PAD_KEY_COL4__USB_OTG_OC |MUX_PAD_CTRL (DIO_PAD_CTRL )), +/* OTG PWR */ +IOMUX_PADS (PAD_EIM_D22__GPIO3_IO22 |MUX_PAD_CTRL (DIO_PAD_CTRL )), };int board_ehci_hcd_init (int port) {struct ventana_board_info *info = &ventana_info; -imx_iomux_v3_setup_multiple_pads (usb_pads,ARRAY_SIZE (usb_pads)); +SETUP_IOMUX_PADS (usb_pads);/* Reset USB HUB (present on GW54xx/GW53xx) */ switch (info->model[3 ]) {case '3' :/* GW53xx */ -imx_iomux_v3_setup_pad (MX6_PAD_GPIO_9__GPIO1_IO09 | -MUX_PAD_CTRL (NO_PAD_CTRL )); +SETUP_IOMUX_PAD (PAD_GPIO_9__GPIO1_IO09 | +MUX_PAD_CTRL (NO_PAD_CTRL ));gpio_direction_output (IMX_GPIO_NR (1 ,9 ),0 );mdelay (2 );gpio_set_value (IMX_GPIO_NR (1 ,9 ),1 );break ;case '4' :/* GW54xx */ -imx_iomux_v3_setup_pad (MX6_PAD_SD1_DAT0__GPIO1_IO16 | -MUX_PAD_CTRL (NO_PAD_CTRL )); +SETUP_IOMUX_PAD (PAD_SD1_DAT0__GPIO1_IO16 | +MUX_PAD_CTRL (NO_PAD_CTRL ));gpio_direction_output (IMX_GPIO_NR (1 ,16 ),0 );mdelay (2 );gpio_set_value (IMX_GPIO_NR (1 ,16 ),1 );
@@ -295,7 +336,7 @@ int board_mmc_getcd(struct mmc *mmc)int board_mmc_init (bd_t *bis) {/* Only one USDHC controller on Ventana */ -imx_iomux_v3_setup_multiple_pads (usdhc3_pads,ARRAY_SIZE (usdhc3_pads)); +SETUP_IOMUX_PADS (usdhc3_pads); usdhc_cfg.sdhc_clk =mxc_get_clock (MXC_ESDHC3_CLK ); usdhc_cfg.max_bus_width =4 ;
@@ -306,17 +347,16 @@ int board_mmc_init(bd_t *bis)#ifdef CONFIG_MXC_SPI iomux_v3_cfg_t const ecspi1_pads[] = {/* SS1 */ -MX6_PAD_EIM_D19__GPIO3_IO19 |MUX_PAD_CTRL (SPI_PAD_CTRL ), -MX6_PAD_EIM_D17__ECSPI1_MISO |MUX_PAD_CTRL (SPI_PAD_CTRL ), -MX6_PAD_EIM_D18__ECSPI1_MOSI |MUX_PAD_CTRL (SPI_PAD_CTRL ), -MX6_PAD_EIM_D16__ECSPI1_SCLK |MUX_PAD_CTRL (SPI_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_D19__GPIO3_IO19 |MUX_PAD_CTRL (SPI_PAD_CTRL )), +IOMUX_PADS (PAD_EIM_D17__ECSPI1_MISO |MUX_PAD_CTRL (SPI_PAD_CTRL )), +IOMUX_PADS (PAD_EIM_D18__ECSPI1_MOSI |MUX_PAD_CTRL (SPI_PAD_CTRL )), +IOMUX_PADS (PAD_EIM_D16__ECSPI1_SCLK |MUX_PAD_CTRL (SPI_PAD_CTRL )), };static void setup_spi (void ) {gpio_direction_output (CONFIG_SF_DEFAULT_CS ,1 ); -imx_iomux_v3_setup_multiple_pads (ecspi1_pads, -ARRAY_SIZE (ecspi1_pads)); +SETUP_IOMUX_PADS (ecspi1_pads); }#endif
@@ -386,8 +426,7 @@ static void enable_lvds(struct display_info_t const *dev)writel (reg, &iomux->gpr[2 ]);/* Enable Backlight */ -imx_iomux_v3_setup_pad (MX6_PAD_SD1_CMD__GPIO1_IO18 | -MUX_PAD_CTRL (NO_PAD_CTRL )); +SETUP_IOMUX_PAD (PAD_SD1_CMD__GPIO1_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL ));gpio_direction_output (IMX_GPIO_NR (1 ,18 ),1 ); }
@@ -484,8 +523,7 @@ static void setup_display(void)writel (reg, &iomux->gpr[3 ]);/* Backlight CABEN on LVDS connector */ -imx_iomux_v3_setup_pad (MX6_PAD_SD2_CLK__GPIO1_IO10 | -MUX_PAD_CTRL (NO_PAD_CTRL )); +SETUP_IOMUX_PAD (PAD_SD2_CLK__GPIO1_IO10 |MUX_PAD_CTRL (NO_PAD_CTRL )); gpio_direction_output(IMX_GPIO_NR(1, 10), 0); }#endif /* CONFIG_VIDEO_IPUV3 */
@@ -497,118 +535,118 @@ static void setup_display(void)/* common to add baseboards */ static iomux_v3_cfg_t const gw_gpio_pads[] = {/* MSATA_EN */ -MX6_PAD_SD4_DAT0__GPIO2_IO08 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_SD4_DAT0__GPIO2_IO08 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* RS232_EN# */ -MX6_PAD_SD4_DAT3__GPIO2_IO11 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_SD4_DAT3__GPIO2_IO11 |MUX_PAD_CTRL (NO_PAD_CTRL )), };/* prototype */ static iomux_v3_cfg_t const gwproto_gpio_pads[] = {/* PANLEDG# */ -MX6_PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PANLEDR# */ -MX6_PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* LOCLED# */ -MX6_PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* RS485_EN */ -MX6_PAD_SD3_DAT4__GPIO7_IO01 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_SD3_DAT4__GPIO7_IO01 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_PWREN# */ -MX6_PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_IRQ# */ -MX6_PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* VID_EN */ -MX6_PAD_EIM_D31__GPIO3_IO31 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_D31__GPIO3_IO31 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* DIOI2C_DIS# */ -MX6_PAD_GPIO_19__GPIO4_IO05 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_GPIO_19__GPIO4_IO05 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCICK_SSON */ -MX6_PAD_SD1_CLK__GPIO1_IO20 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_SD1_CLK__GPIO1_IO20 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCI_RST# */ -MX6_PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL )), };static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {/* PANLEDG# */ -MX6_PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PANLEDR# */ -MX6_PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_PWREN# */ -MX6_PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_IRQ# */ -MX6_PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* GPS_SHDN */ -MX6_PAD_GPIO_2__GPIO1_IO02 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_GPIO_2__GPIO1_IO02 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* VID_PWR */ -MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_CSI0_DATA_EN__GPIO5_IO20 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCI_RST# */ -MX6_PAD_GPIO_0__GPIO1_IO00 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_GPIO_0__GPIO1_IO00 |MUX_PAD_CTRL (NO_PAD_CTRL )), };static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {/* PANLEDG# */ -MX6_PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PANLEDR# */ -MX6_PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_PWREN# */ -MX6_PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_IRQ# */ -MX6_PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* MX6_LOCLED# */ -MX6_PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* GPS_SHDN */ -MX6_PAD_ENET_RXD0__GPIO1_IO27 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_RXD0__GPIO1_IO27 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* USBOTG_SEL */ -MX6_PAD_GPIO_2__GPIO1_IO02 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_GPIO_2__GPIO1_IO02 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* VID_PWR */ -MX6_PAD_EIM_D31__GPIO3_IO31 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_D31__GPIO3_IO31 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCI_RST# */ -MX6_PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL )), };static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {/* PANLEDG# */ -MX6_PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PANLEDR# */ -MX6_PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_PWREN# */ -MX6_PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A19__GPIO2_IO19 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_IRQ# */ -MX6_PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_A20__GPIO2_IO18 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* MX6_LOCLED# */ -MX6_PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* GPS_SHDN */ -MX6_PAD_ENET_RXD0__GPIO1_IO27 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_RXD0__GPIO1_IO27 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* VID_EN */ -MX6_PAD_EIM_D31__GPIO3_IO31 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_D31__GPIO3_IO31 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCI_RST# */ -MX6_PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL )), };static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {/* PANLEDG# */ -MX6_PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_COL0__GPIO4_IO06 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PANLEDR# */ -MX6_PAD_KEY_COL2__GPIO4_IO10 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_COL2__GPIO4_IO10 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* MX6_LOCLED# */ -MX6_PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW4__GPIO4_IO15 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* MIPI_DIO */ -MX6_PAD_SD1_DAT3__GPIO1_IO21 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_SD1_DAT3__GPIO1_IO21 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* RS485_EN */ -MX6_PAD_EIM_D24__GPIO3_IO24 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_EIM_D24__GPIO3_IO24 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_PWREN# */ -MX6_PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW0__GPIO4_IO07 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* IOEXP_IRQ# */ -MX6_PAD_KEY_ROW1__GPIO4_IO09 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_KEY_ROW1__GPIO4_IO09 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* DIOI2C_DIS# */ -MX6_PAD_GPIO_19__GPIO4_IO05 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_GPIO_19__GPIO4_IO05 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* DIOI2C_DIS# */ -MX6_PAD_GPIO_19__GPIO4_IO05 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_GPIO_19__GPIO4_IO05 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCICK_SSON */ -MX6_PAD_SD1_CLK__GPIO1_IO20 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_SD1_CLK__GPIO1_IO20 |MUX_PAD_CTRL (NO_PAD_CTRL )),/* PCI_RST# */ -MX6_PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL ), +IOMUX_PADS (PAD_ENET_TXD1__GPIO1_IO29 |MUX_PAD_CTRL (NO_PAD_CTRL )), };/*
@@ -616,9 +654,9 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {* be pinmuxed as a GPIO or in some cases a PWM */ struct dio_cfg { -iomux_v3_cfg_t gpio_padmux; +iomux_v3_cfg_t gpio_padmux[2 ];unsigned gpio_param; -iomux_v3_cfg_t pwm_padmux; +iomux_v3_cfg_t pwm_padmux[2 ];unsigned pwm_param; };
@@ -645,16 +683,32 @@ struct ventana gpio_cfg[] = {/* GW5400proto */ { .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, .dio_cfg = { - {MX6_PAD_GPIO_9__GPIO1_IO09 ,IMX_GPIO_NR (1 ,9 ), - MX6_PAD_GPIO_9__PWM1_OUT, 1 }, - { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), - MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, - { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), - MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, - { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), - MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, }, .leds = { IMX_GPIO_NR(4, 6),
@@ -672,16 +726,32 @@ struct ventana gpio_cfg[] = {/* GW51xx */ { .gpio_pads = gw51xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw51xx_gpio_pads), + .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, .dio_cfg = { - {MX6_PAD_SD1_DAT0__GPIO1_IO16 ,IMX_GPIO_NR (1 ,16 ), - 0, 0 }, - { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), - MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, - { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), - MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, - { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18), - MX6_PAD_SD1_CMD__PWM4_OUT, 4 }, + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, }, .leds = { IMX_GPIO_NR(4, 6),
@@ -697,16 +767,32 @@ struct ventana gpio_cfg[] = {/* GW52xx */ { .gpio_pads = gw52xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw52xx_gpio_pads), + .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, .dio_cfg = { - {MX6_PAD_SD1_DAT0__GPIO1_IO16 ,IMX_GPIO_NR (1 ,16 ), - 0, 0 }, - { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), - MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, - { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), - MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, - { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), - 0, 0 }, + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, }, .leds = { IMX_GPIO_NR(4, 6),
@@ -724,16 +810,32 @@ struct ventana gpio_cfg[] = {/* GW53xx */ { .gpio_pads = gw53xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw53xx_gpio_pads), + .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, .dio_cfg = { - {MX6_PAD_SD1_DAT0__GPIO1_IO16 ,IMX_GPIO_NR (1 ,16 ), - 0, 0 }, - { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), - MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, - { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17), - MX6_PAD_SD1_DAT1__PWM3_OUT, 3 }, - { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20), - 0, 0 }, + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, }, .leds = { IMX_GPIO_NR(4, 6),
@@ -750,16 +852,32 @@ struct ventana gpio_cfg[] = {/* GW54xx */ { .gpio_pads = gw54xx_gpio_pads, - .num_pads = ARRAY_SIZE(gw54xx_gpio_pads), + .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, .dio_cfg = { - {MX6_PAD_GPIO_9__GPIO1_IO09 ,IMX_GPIO_NR (1 ,9 ), - MX6_PAD_GPIO_9__PWM1_OUT, 1 }, - { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19), - MX6_PAD_SD1_DAT2__PWM2_OUT, 2 }, - { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9), - MX6_PAD_SD4_DAT1__PWM3_OUT, 3 }, - { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10), - MX6_PAD_SD4_DAT2__PWM4_OUT, 4 }, + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, }, .leds = { IMX_GPIO_NR(4, 6),
@@ -905,6 +1023,7 @@ static void setup_board_gpio(int board)for (i =0 ; i <4 ; i++) {struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];unsigned ctrl =DIO_PAD_CTRL ; +unsigned cputype =is_cpu_type (MXC_CPU_MX6Q ) ?0 :1 ;sprintf (arg,"dio%d" , i);if (!hwconfig (arg))
@@ -919,14 +1038,14 @@ static void setup_board_gpio(int board) cfg->gpio_param%32 , cfg->gpio_param); } -imx_iomux_v3_setup_pad (cfg->gpio_padmux | +imx_iomux_v3_setup_pad (cfg->gpio_padmux[cputype] |MUX_PAD_CTRL (ctrl));gpio_direction_input (cfg->gpio_param); }else if (hwconfig_subarg_cmp ("dio2" ,"mode" ,"pwm" ) && cfg->pwm_padmux) {if (!quiet)printf ("DIO%d: pwm%d\n" , i, cfg->pwm_param); -imx_iomux_v3_setup_pad (cfg->pwm_padmux | +imx_iomux_v3_setup_pad (cfg->pwm_padmux[cputype] |MUX_PAD_CTRL (ctrl)); } }
@@ -946,9 +1065,10 @@ static void setup_board_gpio(int board)int imx6_pcie_toggle_reset (void ) {if (board_type <GW_UNKNOWN ) { -gpio_direction_output (gpio_cfg[board_type].pcie_rst,0 ); +uint pin = gpio_cfg[board_type].pcie_rst; +gpio_direction_output (pin,0 );mdelay (50 ); -gpio_direction_output (gpio_cfg[board_type].pcie_rst,1 ); +gpio_direction_output (pin,1 ); }return 0 ; }
@@ -997,7 +1117,6 @@ int dram_init(void) { gd->ram_size =get_ram_size ((void *)PHYS_SDRAM ,CONFIG_DDR_MB *1024 *1024 ); -return 0 ; }
@@ -1019,9 +1138,15 @@ int board_init(void)#ifdef CONFIG_MXC_SPI setup_spi ();#endif -setup_i2c (0 ,CONFIG_SYS_I2C_SPEED ,0x7f , &i2c_pad_info0); -setup_i2c (1 ,CONFIG_SYS_I2C_SPEED ,0x7f , &i2c_pad_info1); -setup_i2c (2 ,CONFIG_SYS_I2C_SPEED ,0x7f , &i2c_pad_info2); +if (is_cpu_type (MXC_CPU_MX6Q )) { +setup_i2c (0 ,CONFIG_SYS_I2C_SPEED ,0x7f , &mx6q_i2c_pad_info0); +setup_i2c (1 ,CONFIG_SYS_I2C_SPEED ,0x7f , &mx6q_i2c_pad_info1); +setup_i2c (2 ,CONFIG_SYS_I2C_SPEED ,0x7f , &mx6q_i2c_pad_info2); + }else { +setup_i2c (0 ,CONFIG_SYS_I2C_SPEED ,0x7f , &mx6dl_i2c_pad_info0); +setup_i2c (1 ,CONFIG_SYS_I2C_SPEED ,0x7f , &mx6dl_i2c_pad_info1); +setup_i2c (2 ,CONFIG_SYS_I2C_SPEED ,0x7f , &mx6dl_i2c_pad_info2); + }#ifdef CONFIG_CMD_SATA setup_sata ();
@@ -1030,11 +1155,12 @@ int board_init(void) board_type =read_eeprom (I2C_GSC , &ventana_info);/* board-specifc GPIO iomux */ +SETUP_IOMUX_PADS (gw_gpio_pads);if (board_type <GW_UNKNOWN ) { -imx_iomux_v3_setup_multiple_pads (gw_gpio_pads, -ARRAY_SIZE (gw_gpio_pads)); -imx_iomux_v3_setup_multiple_pads (gpio_cfg[board_type].gpio_pads, - gpio_cfg[board_type].num_pads); +iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads; +int count = gpio_cfg[board_type].num_pads; + +imx_iomux_v3_setup_multiple_pads (p, count); }return 0 ;
Signature · 1 line
1.8.3.2
PATCH v4 10/10 imx: ventana: switch to SPL
In reply to Tim HarveySwitch to an SPL image. The SPL for Ventana does the following:
- setup i2c and read the factory programmed EEPROM to obtain DRAM config and model for board-specific calibration data
- configure DRAM per CPU/size/layout/devices/calibration
- load u-boot.img from NAND and jump to it
This allows for a single SPL+u-boot.img to replace the previous multiple boa configurations.
Cc Stefan Roese <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Andy Ng <[email protected]>
Cc Eric Nelson <[email protected]>
Cc Tapani Utriainen <[email protected]>
Cc Tom Rini <[email protected]>
Signed-off-by Tim Harvey <[email protected]>
---
v4:
- no changes
v3:
- re-ordered calls in board_init_f
v2:
- remove missing/unnecessary include
- revert mtdparts change
- use imx_ddr_size() which uses MMDC configuration to determine mem size explicitly
- add support for MX6SOLO and MX6DUAL
- set CS0_END for 4GB so get_ram_size() works
- updated DDR3 calibration values for ventana boards
- fixed build issue - only compile spl if doing spl build
- fixed line length issue in README
- remove CONFIG_SPL* conditions and conditionally compile instead
- removed prints for CPU type and DRAM size/width - uboot will print these later
- removed unused gw_ventana_spl.cfg
- use common read_eeprom function
- added MMC support to SPL
--- board/gateworks/gw_ventana/Makefile | 1 + board/gateworks/gw_ventana/README | 92 +++--- board/gateworks/gw_ventana/gw_ventana.c | 10 +- board/gateworks/gw_ventana/gw_ventana.cfg | 15 - board/gateworks/gw_ventana/gw_ventana_spl.c | 419 ++++++++++++++++++++++++++++ boards.cfg | 6 +- include/configs/gw_ventana.h | 11 + 7 files changed, 498 insertions(+), 56 deletions(-) create mode 100644 board/gateworks/gw_ventana/gw_ventana_spl.c
board/gateworks/gw_ventana/Makefile +1 -0
@@ -7,4 +7,5 @@ # obj-y := gw_ventana.o gsc.o eeprom.o +obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
board/gateworks/gw_ventana/README +60 -32
113 lines not on this page · raw message
board/gateworks/gw_ventana/gw_ventana.c +6 -4
@@ -1102,6 +1102,7 @@ void get_board_serial(struct tag_serialnr *serialnr)* Board Support */ +/* called from SPL board_init_f() */ int board_early_init_f (void ) {setup_iomux_uart ();
@@ -1115,8 +1116,7 @@ int board_early_init_f(void)int dram_init (void ) { - gd->ram_size =get_ram_size ((void *)PHYS_SDRAM , -CONFIG_DDR_MB *1024 *1024 ); + gd->ram_size =imx_ddr_size ();return 0 ; }
@@ -1258,9 +1258,11 @@ int misc_init_r(void)* env scripts will try loading each from most specific to * least. */ -if (is_cpu_type (MXC_CPU_MX6Q )) +if (is_cpu_type (MXC_CPU_MX6Q ) || +is_cpu_type (MXC_CPU_MX6D )) cputype ="imx6q" ; -else if (is_cpu_type (MXC_CPU_MX6DL )) +else if (is_cpu_type (MXC_CPU_MX6DL ) || +is_cpu_type (MXC_CPU_MX6SOLO )) cputype ="imx6dl" ;memset (str,0 ,sizeof (str));for (i =0 ; i < (sizeof (str)-1 ) && info->model[i]; i++)
board/gateworks/gw_ventana/gw_ventana.cfg +0 -15
@@ -24,21 +24,6 @@ BOOT_FROM nand #define __ASSEMBLY__ #include <config.h> -#include "asm/arch/mx6-ddr.h" #include "asm/arch/iomux.h" #include "asm/arch/crm_regs.h" - -/* Memory configuration (size is overridden via eeprom config) */ -#include "../../boundary/nitrogen6x/ddr-setup.cfg" -#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024 - #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg" -#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024 - #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg" -#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512 - #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" -#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512 - #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg" -#else - #error "Unsupported CPU/Memory configuration" -#endif #include "clocks.cfg"
board/gateworks/gw_ventana/gw_ventana_spl.c new file +419 -0
419 lines not on this page · raw message
boards.cfg +1 -5
@@ -328,11 +328,7 @@ Active arm armv7 mx6 freescale mx6qsabreauto Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <[email protected]> Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <[email protected]> Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <[email protected]> -Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <[email protected]> -Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <[email protected]> -Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <[email protected]> -Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <[email protected]> -Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <[email protected]> +Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey <[email protected]> Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <[email protected]> Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <[email protected]> Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <[email protected]>
include/configs/gw_ventana.h +11 -0
@@ -7,6 +7,17 @@#ifndef __CONFIG_H#define __CONFIG_H +/* SPL */ +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +/* +#define CONFIG_SPL_SATA_SUPPORT +*/ +/* Location in NAND to read U-Boot from */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) + +#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO /* display cpu info */
Signature · 1 line
1.8.3.2
v4 cover mx6: SPL NAND support
In reply to Tim HarveyHi Tim,
Quoted 6 lines · Tim Harvey
This series adds some necessary framework for IMX6 SPL support. The series includes support for NAND SPL and has been tested with MMC as well. I have tested this on five differing Ventana baseboards with a variety of memory (32bit 512MB, 32bit 1024MB, 64bit 1024MB) and CPU configurations (IMX6Q, IMX6DL, IMX6S).
Whole series applied to u-boot-imx. Many thanks again to have taken the work to add SPL support for the i.MX6 processor !
Best regards,
Stefano Babic
Signature · 5 lines
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