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ARM: tegra: Add device tree nodes for flow controller

PATCH New Thierry Reding 2 participants 4 messages Jun 11, 2014 – Jun 12, 2014

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Device tree bindings Arm (32-bit) Arm sub-architectures Tegra architecture support
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Thierry Reding

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#0 lore raw

PATCH 1/2 ARM: tegra: Add device tree nodes for flow controller

From: Thierry Reding <[email protected]>

These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it.

Signed-off-by Thierry Reding <[email protected]>
---
 arch/arm/boot/dts/tegra114.dtsi | 5 +++++
 arch/arm/boot/dts/tegra124.dtsi | 5 +++++
 arch/arm/boot/dts/tegra20.dtsi  | 5 +++++
 arch/arm/boot/dts/tegra30.dtsi  | 5 +++++
 4 files changed, 20 insertions(+)
arch/arm/boot/dts/tegra114.dtsi +5 -0
index 90982679c161..1953113598b2 100644
@@ -161,6 +161,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller at 60007000 {
+		compatible = "nvidia,tegra114-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
+
 	apbdma: dma at 6000a000 {
 		compatible = "nvidia,tegra114-apbdma";
 		reg = <0x6000a000 0x1400>;
arch/arm/boot/dts/tegra124.dtsi +5 -0
index 057340b980dd..0f3c869a1673 100644
@@ -205,6 +205,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller at 0,60007000 {
+		compatible = "nvidia,tegra124-flowctrl";
+		reg = <0x0 0x60007000 0x0 0x1000>;
+	};
+
 	gpio: gpio at 0,6000d000 {
 		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
 		reg = <0x0 0x6000d000 0x0 0x1000>;
arch/arm/boot/dts/tegra20.dtsi +5 -0
index 81815416e6d3..e47ae7472e7a 100644
@@ -201,6 +201,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller at 60007000 {
+		compatible = "nvidia,tegra20-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
+
 	apbdma: dma at 6000a000 {
 		compatible = "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1200>;
arch/arm/boot/dts/tegra30.dtsi +5 -0
index e88e477bfb2c..d07baa3f840f 100644
@@ -282,6 +282,11 @@
 		#reset-cells = <1>;
 	};
 
+	flow-controller at 60007000 {
+		compatible = "nvidia,tegra30-flowctrl";
+		reg = <0x60007000 0x1000>;
+	};
+
 	apbdma: dma at 6000a000 {
 		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 		reg = <0x6000a000 0x1400>;
Signature · 1 line
1.9.2
author
#1 lore raw

PATCH 2/2 ARM: tegra: Initialize flow controller from DT

From: Thierry Reding <[email protected]>

Use a matching device tree node to initialize the flow controller driver instead of hard-coding the I/O address. This is necessary to get rid of the iomap.h include, which in turn make it easier to share this code with 64-bit Tegra SoCs.

Signed-off-by Thierry Reding <[email protected]>

---
Note that this doesn't provide a fallback option for compatibility with old device trees. Any kind of fallback would require either the iomap.h file to remain included or copying out some parts verbatim, which to a large degree defies the whole purpose of this patch. The ultimate goal is to move this code into drivers/soc/tegra in order to allow sharing between 32- and 64-bit Tegra SoCs.

If we absolutely must have backwards compatibility with device trees that don't have the flow controller node and still want to share this code with ARM64, I don't see any other way than moving iomap.h to drivers/soc/tegra along with all the other code.

 arch/arm/mach-tegra/flowctrl.c | 36 +++++++++++++++++++++++++++---------
 arch/arm/mach-tegra/flowctrl.h |  2 ++
 arch/arm/mach-tegra/tegra.c    |  2 ++
 3 files changed, 31 insertions(+), 9 deletions(-)
arch/arm/mach-tegra/flowctrl.c +27 -9
index ce8ab8abf061..5f84320a91d4 100644
@@ -18,13 +18,14 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/cpumask.h>
 #include <linux/init.h>
-#include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/cpumask.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "flowctrl.h"
-#include "iomap.h"
 #include "fuse.h"
 
 static u8 flowctrl_offset_halt_cpu[] = {

@@ -41,23 +42,22 @@ static u8 flowctrl_offset_cpu_csr[] = {
 	FLOW_CTRL_CPU1_CSR + 16,
 };
 
+static void __iomem *tegra_flowctrl_base;
+
 static void flowctrl_update(u8 offset, u32 value)
 {
-	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
-
-	writel(value, addr);
+	writel(value, tegra_flowctrl_base + offset);
 
 	/* ensure the update has reached the flow controller */
 	wmb();
-	readl_relaxed(addr);
+	readl_relaxed(tegra_flowctrl_base + offset);
 }
 
 u32 flowctrl_read_cpu_csr(unsigned int cpuid)
 {
 	u8 offset = flowctrl_offset_cpu_csr[cpuid];
-	void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
 
-	return readl(addr);
+	return readl(tegra_flowctrl_base + offset);
 }
 
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)

@@ -138,3 +138,21 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
 	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
 	flowctrl_write_cpu_csr(cpuid, reg);
 }
+
+static const struct of_device_id matches[] __initconst = {
+	{ .compatible = "nvidia,tegra124-flowctrl" },
+	{ .compatible = "nvidia,tegra114-flowctrl" },
+	{ .compatible = "nvidia,tegra30-flowctrl" },
+	{ .compatible = "nvidia,tegra20-flowctrl" },
+	{ }
+};
+
+void __init tegra_flowctrl_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, matches);
+	BUG_ON(!np);
+
+	tegra_flowctrl_base = of_iomap(np, 0);
+}
arch/arm/mach-tegra/flowctrl.h +2 -0
index c89aac60a143..73a9c5016c1a 100644
@@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
 
 void flowctrl_cpu_suspend_enter(unsigned int cpuid);
 void flowctrl_cpu_suspend_exit(unsigned int cpuid);
+
+void tegra_flowctrl_init(void);
 #endif
 
 #endif
arch/arm/mach-tegra/tegra.c +2 -0
index 972fc87ec185..d008adf558b8 100644
@@ -46,6 +46,7 @@
 #include "board.h"
 #include "common.h"
 #include "cpuidle.h"
+#include "flowctrl.h"
 #include "fuse.h"
 #include "iomap.h"
 #include "irq.h"

@@ -80,6 +81,7 @@ static void __init tegra_init_early(void)
 	tegra_cpu_reset_handler_init();
 	tegra_powergate_init();
 	tegra_hotplug_init();
+	tegra_flowctrl_init();
 }
 
 static void __init tegra_dt_init_irq(void)
Signature · 1 line
1.9.2
#2 lore raw

PATCH 2/2 ARM: tegra: Initialize flow controller from DT

Quoted 16 lines · Thierry Reding

From: Thierry Reding <[email protected]>

Use a matching device tree node to initialize the flow controller driver instead of hard-coding the I/O address. This is necessary to get rid of the iomap.h include, which in turn make it easier to share this code with 64-bit Tegra SoCs.

Signed-off-by Thierry Reding <[email protected]>

---
Note that this doesn't provide a fallback option for compatibility with old device trees. Any kind of fallback would require either the iomap.h file to remain included or copying out some parts verbatim, which to a large degree defies the whole purpose of this patch. The ultimate goal is to move this code into drivers/soc/tegra in order to allow sharing between 32- and 64-bit Tegra SoCs.

Quoted 4 lines

If we absolutely must have backwards compatibility with device trees that don't have the flow controller node and still want to share this code with ARM64, I don't see any other way than moving iomap.h to drivers/soc/tegra along with all the other code.

We do need a fallback. I think it would be as simple as the following:

np = of_find_matching_node(NULL, matches);
- BUG_ON(!np);
+ if (!np) {
+ base_addr = 0x60007000;
+ iomap(base_addr) // roughly this anyway

In other words, hard-code the fallback right where it's used. No need to keep iomap.h around etc.

arch/arm/mach-tegra/tegra.c static void __init tegra_init_early(void) · line 85

Quoted 8 lines
arch/arm/mach-tegra/tegra.c +1 -0
@@ -80,6 +81,7 @@ static void __init tegra_init_early(void)
 	tegra_cpu_reset_handler_init();
 	tegra_powergate_init();
 	tegra_hotplug_init();
+	tegra_flowctrl_init();
 }

It might make sense to call the function as early as possible; don't some of CPU reset, powergate, hotplug depend on the flow controller? Not that they can likely trigger this early, but it'd still be good if the init order roughly logically followed any runtime dependencies.

#3 lore raw

PATCH 1/2 ARM: tegra: Add device tree nodes for flow controller

In reply to Thierry Reding
Quoted 4 lines · Thierry Reding

From: Thierry Reding <[email protected]>

These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it.

I don't see a file in Documentation/devicetree/bindings that describes these nodes...