devicetree: bindings: separate CPU enable method descriptions

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+==========================
+CPU enable-method bindings
+==========================
+
+The device tree describes the layout of CPUs in a machine in a single "cpus"
+node, which in turn contains a number of "cpu" sub-nodes defining properties
+for each cpu.
+
+For multiprocessing configurations, CPU cores can be individually enabled
+and disabled.  The enabling capability is used for SMP startup as well as
+CPU hotplug.  A CPU enable method--normally specified in the device tree
+using an "enable-method" property--defines how cores are enabled.  If all
+CPUs in a machine use the same enable method and related property values,
+these properties should be defined in the "cpus" node, which associates the
+property values with all CPUs.  Alternatively, every "cpu" node can define
+its "enable-method" separately.
+
+Documents in this directory define how each of the CPU enable methods are to
+be used, as well the names and possible values of related properties that
+are required by or affect each enable method.

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+===========================================================
+Secondary CPU enable-method "marvell,armada-xp-smp" binding
+===========================================================
+
+This document describes the "marvell,armada-xp-smp" method for enabling
+CPUs.  This enable method should be used in the "cpus" node, but can
+also be defined in individual "cpu" nodes.
+
+Enable method name:	"marvell,armada-xp-smp"
+Compatible machines:	"marvell,armadaxp-mv78230"
+			"marvell,armadaxp-mv78260
+			"marvell,armadaxp-mv78460"
+Compatible cpu:		"marvell,sheeva-v7"
+Related properties:	(none)
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,armada-xp-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "marvell,sheeva-v7";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "marvell,sheeva-v7";
+			reg = <1>;
+		};
+	};

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+============================================================
+Secondary CPU enable-method "marvell,armada-375-smp" binding
+============================================================
+
+This document describes the "marvell,armada-375-smp" method for enabling
+CPUs.  This enable method should be used in the "cpus" node, but can
+also be defined in individual "cpu" nodes.
+
+Enable method name:	"marvell,armada-375-smp"
+Compatible machine:	"marvell,armada375"
+Compatible cpu:		"arm,cortex-a9"
+Related properties:	(none)
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,armada-375-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};

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+===========================================================
+Secondary CPU enable-method "marvell,armada380-smp" binding
+===========================================================
+
+This document describes the "marvell,armada380-smp" method for enabling
+CPUs.  This enable method should be used in the "cpus" node, but can
+also be defined in individual "cpu" nodes.
+
+Enable method name:	"marvell,armada-380-smp"
+Compatible machine:	"marvell,armada380"
+			"marvell,armada385"
+Compatible cpu:		"arm,cortex-a9"
+Related properties:	(none)
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,armada-380-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};

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+=========================================================
+Secondary CPU enable-method "rockchip,rk3066-smp" binding
+=========================================================
+
+This document describes the "rockchip,rk3066-smp" method for enabling
+CPUs.  This enable method should be used in the "cpus" node, but can
+also be defined in individual "cpu" nodes.
+
+Enable method name:	"rockchip,rk3066-smp"
+Compatible machine:	"rockchip,rk3066a"
+			"rockchip,rk3188"
+Compatible cpu:		"arm,cortex-a9"
+Related properties:	(none)
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "rockchip,rk3066-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};

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@@ -191,30 +191,8 @@ nodes to be present and contain the properties described below.
 			    "qcom,kpss-acc-v1"
 			    "qcom,kpss-acc-v2"
 			    "rockchip,rk3066-smp"
-
-	- cpu-release-addr
-		Usage: required for systems that have an "enable-method"
-		       property value of "spin-table".
-		Value type: <prop-encoded-array>
-		Definition:
-			# On ARM v8 64-bit systems must be a two cell
-			  property identifying a 64-bit zero-initialised
-			  memory location.
-
-	- qcom,saw
-		Usage: required for systems that have an "enable-method"
-		       property value of "qcom,kpss-acc-v1" or
-		       "qcom,kpss-acc-v2"
-		Value type: <phandle>
-		Definition: Specifies the SAW[1] node associated with this CPU.
-
-	- qcom,acc
-		Usage: required for systems that have an "enable-method"
-		       property value of "qcom,kpss-acc-v1" or
-		       "qcom,kpss-acc-v2"
-		Value type: <phandle>
-		Definition: Specifies the ACC[2] node associated with this CPU.
-
+		Details about use of these CPU enable methods is documented
+		elsewhere[1].
 
 Example 1 (dual-cluster big.LITTLE system 32-bit):
 

@@ -409,5 +387,4 @@ cpus {
 };
 
 --
-[1] arm/msm/qcom,saw2.txt
-[2] arm/msm/qcom,kpss-acc.txt
+[1] arm/cpu-enable-method/