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xen: add Intel IGD passthrough support

PATCH In review Tiejun Chen 10 participants 169 messages Jun 25, 2014 – Jul 29, 2014 Page 1 of 2

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#0 lore raw

v5 cover xen: add Intel IGD passthrough support

V5 is generated just based on Paolo's some comments.

v5:

* Don't set that ISA class property, instead, just fake this ISA bridge with 00:1f.0.
* Don't pass vendor/device ids in igd_pci_read().
* Add to support offset 0x44/0x48.
* Just rebase.

v4:

* Fix some typos in the patch head description.
* Improve some comments.
* Given that xen_pt_register_vga_regions()/xen_pt_unregister_vga_regions() are called unconditionally, so we just return 0 there.
* Remove one spurious change.
* Remove some unnecessary "return" in void foo().
* Given that pci_create_pch() is called unconditionally, so we just return 0 even if its failed to check xen_has_gfx_passthru.
* Use (xen_enabled() && xen_has_gfx_passthru) to make sure we only work in this scenario.

v3:

* In this case, as we discussed we will give priority to devices to reserve a specific devfn by passing "device_model_args_hvm = ['-device', 'xen-platform,addr=0x3']" and "vga=none", so withdraw patch #1, #2 and #4.
* Fix some typos.
* Add more comments to make that readable.
* To unmap igd_opregion when call xen_pt_unregister_vga_regions().
* Improve some return paths.
* Force to convert igd_guest/host_opoegion as an unsigned long type while calling xc_domain_memory_mapping().
* We need to map 3 pages for opregion as hvmloader set.

v2:

* rebase on current qemu tree.
* retrieve VGA bios from sysfs properly.
* redefine some function name.
* introduce bitmap to manage registe/runregister pci dev, and provide a common way to reserve some specific devfn.
* introduce is_igd_passthrough() to make sure we touch physical host bridge only in IGD case.
* We should return zero as an invalid address value while calling igd_read_opregion().

Additionally, now its also not necessary to recompile seabios with some extra steps like v1.

The following patches are ported partially from Xen Qemu-traditional branch which are adding Intel IGD passthrough supporting to Qemu upstream.

To pass through IGD to guest, user need to add following lines in Xen config file:
gfx_passthru=1
pci=['00:02.0@2']

Now successfully boot Ubuntu 14.04/Windows 7 guests with IGD assigned in Haswell desktop with Latest Xen + Qemu upstream.

----------------------------------------------------------------
Tiejun Chen (5):
xen, gfx passthrough: basic graphics passthrough support xen, gfx passthrough: create pseudo intel isa bridge xen, gfx passthrough: support Intel IGD passthrough with VT-D xen, gfx passthrough: create host bridge to passthrough xen, gfx passthrough: add opregion mapping

 hw/pci-host/piix.c           |  56 +++++++++++++++-
 hw/xen/Makefile.objs         |   2 +-
 hw/xen/xen-host-pci-device.c |   5 ++
 hw/xen/xen-host-pci-device.h |   1 +
 hw/xen/xen_pt.c              |  10 +++
 hw/xen/xen_pt.h              |  12 +++-
 hw/xen/xen_pt_config_init.c  |  50 +++++++++++++-
 hw/xen/xen_pt_graphics.c     | 513 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 qemu-options.hx              |   9 +++
 vl.c                         |  10 +++
 10 files changed, 663 insertions(+), 5 deletion

Thanks
Tiejun

#1 lore raw

PATCH v5 1/5 xen, gfx passthrough: basic graphics passthrough support

basic gfx passthrough support:
- add a vga type for gfx passthrough
- retrieve VGA bios from sysfs, then load it to guest at 0xC0000
- register/unregister legacy VGA I/O ports and MMIOs for passthrough GFX

The original patch is from Weidong Han <[email protected]>

---
v5:

* Just rebase.

v4:

* Fix some typos in the patch head description.
* Improve some comments.
* Given that xen_pt_register_vga_regions()/xen_pt_unregister_vga_regions() are called unconditionally, so we just return 0 there.
* Remove one spurious change.

v3:

* Fix some typos.
* Add more comments to make that readable.
* Improve some return paths.

v2:

* retrieve VGA bios from sysfs properly.
* redefine some function name.

 hw/xen/Makefile.objs         |   2 +-
 hw/xen/xen-host-pci-device.c |   5 +
 hw/xen/xen-host-pci-device.h |   1 +
 hw/xen/xen_pt.c              |  10 ++
 hw/xen/xen_pt.h              |   4 +
 hw/xen/xen_pt_graphics.c     | 232 +++++++++++++++++++++++++++++++++++++++++++
 qemu-options.hx              |   9 ++
 vl.c                         |  10 ++
 8 files changed, 272 insertions(+), 1 deletion(-)
 create mode 100644 hw/xen/xen_pt_graphics.c
hw/xen/Makefile.objs +1 -1
index a0ca0aa..77b7dae 100644
@@ -2,4 +2,4 @@
 common-obj-$(CONFIG_XEN_BACKEND) += xen_backend.o xen_devconfig.o
 
 obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
-obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
+obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o xen_pt_graphics.o
hw/xen/xen-host-pci-device.c +5 -0
index 743b37b..a54b7de 100644
@@ -376,6 +376,11 @@ int xen_host_pci_device_get(XenHostPCIDevice *d, uint16_t domain,
         goto error;
     }
     d->irq = v;
+    rc = xen_host_pci_get_hex_value(d, "class", &v);
+    if (rc) {
+        goto error;
+    }
+    d->class_code = v;
     d->is_virtfn = xen_host_pci_dev_is_virtfn(d);
 
     return 0;
hw/xen/xen-host-pci-device.h +1 -0
index c2486f0..f1e1c30 100644
@@ -25,6 +25,7 @@ typedef struct XenHostPCIDevice {
 
     uint16_t vendor_id;
     uint16_t device_id;
+    uint32_t class_code;
     int irq;
 
     XenHostPCIIORegion io_regions[PCI_NUM_REGIONS - 1];
hw/xen/xen_pt.c +10 -0
index be4220b..dac4238 100644
@@ -450,6 +450,7 @@ static int xen_pt_register_regions(XenPCIPassthroughState *s)
                    d->rom.size, d->rom.base_addr);
     }
 
+    xen_pt_register_vga_regions(d);
     return 0;
 }
 
@@ -470,6 +471,8 @@ static void xen_pt_unregister_regions(XenPCIPassthroughState *s)
     if (d->rom.base_addr && d->rom.size) {
         memory_region_destroy(&s->rom);
     }
+
+    xen_pt_unregister_vga_regions(d);
 }
 
 /* region mapping */
@@ -693,6 +696,13 @@ static int xen_pt_initfn(PCIDevice *d)
     /* Handle real device's MMIO/PIO BARs */
     xen_pt_register_regions(s);
 
+    /* Setup VGA bios for passthrough GFX */
+    if (xen_pt_setup_vga(&s->real_device) < 0) {
+        XEN_PT_ERR(d, "Setup VGA BIOS of passthrough GFX failed!\n");
+        xen_host_pci_device_put(&s->real_device);
+        return -1;
+    }
+
     /* reinitialize each config register to be emulated */
     if (xen_pt_config_init(s)) {
         XEN_PT_ERR(d, "PCI Config space initialisation failed.\n");
hw/xen/xen_pt.h +4 -0
index 942dc60..4d3a18d 100644
@@ -298,5 +298,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
     return s->msix && s->msix->bar_index == bar;
 }
 
+extern int xen_has_gfx_passthru;
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_setup_vga(XenHostPCIDevice *dev);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c new file +232 -0

232 lines not on this page · raw message

qemu-options.hx +9 -0
index ff76ad4..1c77baa 100644
@@ -1066,6 +1066,15 @@ STEXI
 Rotate graphical output some deg left (only PXA LCD).
 ETEXI
 
+DEF("gfx_passthru", 0, QEMU_OPTION_gfx_passthru,
+    "-gfx_passthru   enable Intel IGD passthrough by XEN\n",
+    QEMU_ARCH_ALL)
+STEXI
+@item -gfx_passthru
+@findex -gfx_passthru
+Enable Intel IGD passthrough by XEN
+ETEXI
+
 DEF("vga", HAS_ARG, QEMU_OPTION_vga,
     "-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|none]\n"
     "                select video card type\n", QEMU_ARCH_ALL)
vl.c +10 -0
index a1686ef..c5b572d 100644
@@ -1418,6 +1418,13 @@ static void configure_msg(QemuOpts *opts)
     enable_timestamp_msg = qemu_opt_get_bool(opts, "timestamp", true);
 }
 
+/* We still need this for compatibility with XEN. */
+int xen_has_gfx_passthru;
+static void xen_gfx_passthru(const char *optarg)
+{
+    xen_has_gfx_passthru = 1;
+}
+
 /***********************************************************/
 /* USB devices */
 
@@ -3945,6 +3952,9 @@ int main(int argc, char **argv, char **envp)
                     exit(1);
                 }
                 break;
+            case QEMU_OPTION_gfx_passthru:
+                xen_gfx_passthru(optarg);
+                break;
             default:
                 os_parse_cmd_args(popt->index, optarg);
             }
Signature · 1 line
1.9.1
#2 lore raw

Re: [Qemu-devel] [v5][PATCH 1/5] xen, gfx passthrough: basic graphics passthrough support

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 13 lines
hw/xen/xen_pt_graphics.c new file +13 -0
+static int get_vgabios(unsigned char *buf, XenHostPCIDevice *dev)
+{
+    char rom_file[64];
+    FILE *fp;
+    uint8_t val;
+    struct stat st;
+    uint16_t magic = 0;
+    int ret = 0;
+
+    snprintf(rom_file, sizeof(rom_file),
+             "/sys/bus/pci/devices/%04x:%02x:%02x.%d/rom",
+             dev->domain, dev->bus, dev->dev,
+             dev->func);

hw/xen/xen_pt_graphics.c line 141

Quoted 10 lines
hw/xen/xen_pt_graphics.c new file +10 -0
+
+    if (stat(rom_file, &st)) {
+        return -ENODEV;
+    }
+
+    if (access(rom_file, F_OK)) {
+        XEN_PT_ERR(NULL, "pci-assign: Insufficient privileges for %s",
+                    rom_file);
+        return -ENODEV;
+    }

These two checks (stat and access) are useless.

Quoted 26 lines
hw/xen/xen_pt_graphics.c new file +26 -0
+    /* Write "1" to the ROM file to enable it */
+    fp = fopen(rom_file, "r+");
+    if (fp == NULL) {
+        return -EACCES;
+    }
+    val = 1;
+    if (fwrite(&val, 1, 1, fp) != 1) {
+        XEN_PT_LOG("%s\n", "Failed to enable pci-sysfs rom file");
+        ret = -EIO;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    /*
+     * Check if it a real bios extension.
+     * The magic number is 0xAA55.
+     */
+    if (!fread(&magic, sizeof(magic), 1, fp)) {
+        XEN_PT_ERR(NULL, "VGA: can't get magic.\n");
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    if (magic != 0xAA55) {
+        XEN_PT_ERR(NULL, "VGA: wrong magic %x.\n", magic);
+        ret = -ENODEV;
+        goto close_rom;

hw/xen/xen_pt_graphics.c line 178

Quoted 10 lines
hw/xen/xen_pt_graphics.c new file +10 -0
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    if (!fread(buf, 1, st.st_size, fp)) {
+        XEN_PT_ERR(NULL, "VGA: pci-assign: Cannot read from host %s", rom_file);
+        XEN_PT_LOG(NULL, "VGA: Device option ROM contents are probably invalid "
+                     "(check dmesg).\nSkip option ROM probe with rombar=0, "
+                     "or load from file with romfile=\n");
+    }
+

Why is this graphics passthrough specific? Should QEMU's Xen PCI passthrough read ROM BAR contents from network cards too, for example?

Paolo

#3 lore raw

Re: [Qemu-devel] [v5][PATCH 1/5] xen, gfx passthrough: basic graphics passthrough support

Quoted 18 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 17 lines
hw/xen/xen_pt_graphics.c new file +17 -0
+static int get_vgabios(unsigned char *buf, XenHostPCIDevice *dev)
+{
+    char rom_file[64];
+    FILE *fp;
+    uint8_t val;
+    struct stat st;
+    uint16_t magic = 0;
+    int ret = 0;
+
+    snprintf(rom_file, sizeof(rom_file),
+             "/sys/bus/pci/devices/%04x:%02x:%02x.%d/rom",
+             dev->domain, dev->bus, dev->dev,
+             dev->func);
+
+    if (stat(rom_file, &st)) {
+        return -ENODEV;
+    }
Quoted 8 lines

hw/xen/xen_pt_graphics.c line 141

Quoted 6 lines
hw/xen/xen_pt_graphics.c new file +6 -0
+
+    if (access(rom_file, F_OK)) {
+        XEN_PT_ERR(NULL, "pci-assign: Insufficient privileges for %s",
+                    rom_file);
+        return -ENODEV;
+    }

These two checks (stat and access) are useless.

Will remove this.

Quoted 35 lines
Quoted 35 lines
hw/xen/xen_pt_graphics.c new file +31 -0
+    /* Write "1" to the ROM file to enable it */
+    fp = fopen(rom_file, "r+");
+    if (fp == NULL) {
+        return -EACCES;
+    }
+    val = 1;
+    if (fwrite(&val, 1, 1, fp) != 1) {
+        XEN_PT_LOG("%s\n", "Failed to enable pci-sysfs rom file");
+        ret = -EIO;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    /*
+     * Check if it a real bios extension.
+     * The magic number is 0xAA55.
+     */
+    if (!fread(&magic, sizeof(magic), 1, fp)) {
+        XEN_PT_ERR(NULL, "VGA: can't get magic.\n");
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    if (magic != 0xAA55) {
+        XEN_PT_ERR(NULL, "VGA: wrong magic %x.\n", magic);
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    if (!fread(buf, 1, st.st_size, fp)) {
+        XEN_PT_ERR(NULL, "VGA: pci-assign: Cannot read from host %s",

rom_file);
+ XEN_PT_LOG(NULL, "VGA: Device option ROM contents are
probably invalid "

Quoted 9 lines

hw/xen/xen_pt_graphics.c line 178

Quoted 5 lines

+ "(check dmesg).\nSkip option ROM probe with
rombar=0, "

hw/xen/xen_pt_graphics.c new file +3 -0
+                     "or load from file with romfile=\n");
+    }
+

Why is this graphics passthrough specific? Should QEMU's Xen PCI passthrough read ROM BAR contents from network cards too, for example?

I think this should not be same simply since we need to call VBIOS from RAM, not a ROM BAR of the device.

Thanks
Tiejun

#4 lore raw

Re: [Qemu-devel] [v5][PATCH 1/5] xen, gfx passthrough: basic graphics passthrough support

In reply to Tiejun Chen
Quoted 10 lines · Tiejun Chen

basic gfx passthrough support:
- add a vga type for gfx passthrough
- retrieve VGA bios from sysfs, then load it to guest at 0xC0000
- register/unregister legacy VGA I/O ports and MMIOs for passthrough GFX

The original patch is from Weidong Han <[email protected]>

ROM loading code is duplicated from assigned_dev_load_option_rom. Would it be a problem for you to create a memory region holding the ROM?
You won't need cpu_physical_memory_rw then, either, or need the VGA_BIOS_DEFAULT_SIZE hack.

Quoted 336 lines

---
v5:

* Just rebase.

v4:

* Fix some typos in the patch head description.
* Improve some comments.
* Given that xen_pt_register_vga_regions()/xen_pt_unregister_vga_regions() are called unconditionally, so we just return 0 there.
* Remove one spurious change.

v3:

* Fix some typos.
* Add more comments to make that readable.
* Improve some return paths.

v2:

* retrieve VGA bios from sysfs properly.
* redefine some function name.

 hw/xen/Makefile.objs         |   2 +-
 hw/xen/xen-host-pci-device.c |   5 +
 hw/xen/xen-host-pci-device.h |   1 +
 hw/xen/xen_pt.c              |  10 ++
 hw/xen/xen_pt.h              |   4 +
 hw/xen/xen_pt_graphics.c     | 232 +++++++++++++++++++++++++++++++++++++++++++
 qemu-options.hx              |   9 ++
 vl.c                         |  10 ++
 8 files changed, 272 insertions(+), 1 deletion(-)
 create mode 100644 hw/xen/xen_pt_graphics.c
hw/xen/Makefile.objs +1 -1
index a0ca0aa..77b7dae 100644
@@ -2,4 +2,4 @@
 common-obj-$(CONFIG_XEN_BACKEND) += xen_backend.o xen_devconfig.o
 
 obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
-obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
+obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o xen_pt_graphics.o
hw/xen/xen-host-pci-device.c +5 -0
index 743b37b..a54b7de 100644
@@ -376,6 +376,11 @@ int xen_host_pci_device_get(XenHostPCIDevice *d, uint16_t domain,
         goto error;
     }
     d->irq = v;
+    rc = xen_host_pci_get_hex_value(d, "class", &v);
+    if (rc) {
+        goto error;
+    }
+    d->class_code = v;
     d->is_virtfn = xen_host_pci_dev_is_virtfn(d);
 
     return 0;
hw/xen/xen-host-pci-device.h +1 -0
index c2486f0..f1e1c30 100644
@@ -25,6 +25,7 @@ typedef struct XenHostPCIDevice {
 
     uint16_t vendor_id;
     uint16_t device_id;
+    uint32_t class_code;
     int irq;
 
     XenHostPCIIORegion io_regions[PCI_NUM_REGIONS - 1];
hw/xen/xen_pt.c +10 -0
index be4220b..dac4238 100644
@@ -450,6 +450,7 @@ static int xen_pt_register_regions(XenPCIPassthroughState *s)
                    d->rom.size, d->rom.base_addr);
     }
 
+    xen_pt_register_vga_regions(d);
     return 0;
 }
 
@@ -470,6 +471,8 @@ static void xen_pt_unregister_regions(XenPCIPassthroughState *s)
     if (d->rom.base_addr && d->rom.size) {
         memory_region_destroy(&s->rom);
     }
+
+    xen_pt_unregister_vga_regions(d);
 }
 
 /* region mapping */
@@ -693,6 +696,13 @@ static int xen_pt_initfn(PCIDevice *d)
     /* Handle real device's MMIO/PIO BARs */
     xen_pt_register_regions(s);
 
+    /* Setup VGA bios for passthrough GFX */
+    if (xen_pt_setup_vga(&s->real_device) < 0) {
+        XEN_PT_ERR(d, "Setup VGA BIOS of passthrough GFX failed!\n");
+        xen_host_pci_device_put(&s->real_device);
+        return -1;
+    }
+
     /* reinitialize each config register to be emulated */
     if (xen_pt_config_init(s)) {
         XEN_PT_ERR(d, "PCI Config space initialisation failed.\n");
hw/xen/xen_pt.h +4 -0
index 942dc60..4d3a18d 100644
@@ -298,5 +298,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
     return s->msix && s->msix->bar_index == bar;
 }
 
+extern int xen_has_gfx_passthru;
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_setup_vga(XenHostPCIDevice *dev);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c new file +208 -0
new file mode 100644
index 0000000..461e526
@@ -0,0 +1,232 @@
+/*
+ * graphics passthrough
+ */
+#include "xen_pt.h"
+#include "xen-host-pci-device.h"
+#include "hw/xen/xen_backend.h"
+
+static int is_vga_passthrough(XenHostPCIDevice *dev)
+{
+    return (xen_has_gfx_passthru
+            && ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
+}
+
+typedef struct VGARegion {
+    int type;           /* Memory or port I/O */
+    uint64_t guest_base_addr;
+    uint64_t machine_base_addr;
+    uint64_t size;    /* size of the region */
+    int rc;
+} VGARegion;
+
+#define IORESOURCE_IO           0x00000100
+#define IORESOURCE_MEM          0x00000200
+
+static struct VGARegion vga_args[] = {
+    {
+        .type = IORESOURCE_IO,
+        .guest_base_addr = 0x3B0,
+        .machine_base_addr = 0x3B0,
+        .size = 0xC,
+        .rc = -1,
+    },
+    {
+        .type = IORESOURCE_IO,
+        .guest_base_addr = 0x3C0,
+        .machine_base_addr = 0x3C0,
+        .size = 0x20,
+        .rc = -1,
+    },
+    {
+        .type = IORESOURCE_MEM,
+        .guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
+        .machine_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
+        .size = 0x20,
+        .rc = -1,
+    },
+};
+
+/*
+ * register VGA resources for the domain with assigned gfx
+ */
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev)
+{
+    int i = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return 0;
+    }
+
+    for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
+        if (vga_args[i].type == IORESOURCE_IO) {
+            vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_ADD_MAPPING);
+        } else {
+            vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_ADD_MAPPING);
+        }
+
+        if (vga_args[i].rc) {
+            XEN_PT_ERR(NULL, "VGA %s mapping failed! (rc: %i)\n",
+                    vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
+                    vga_args[i].rc);
+            return vga_args[i].rc;
+        }
+    }
+
+    return 0;
+}
+
+/*
+ * unregister VGA resources for the domain with assigned gfx
+ */
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
+{
+    int i = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return 0;
+    }
+
+    for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
+        if (vga_args[i].type == IORESOURCE_IO) {
+            vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_REMOVE_MAPPING);
+        } else {
+            vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_REMOVE_MAPPING);
+        }
+
+        if (vga_args[i].rc) {
+            XEN_PT_ERR(NULL, "VGA %s unmapping failed! (rc: %i)\n",
+                    vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
+                    vga_args[i].rc);
+            return vga_args[i].rc;
+        }
+    }
+
+    return 0;
+}
+
+static int get_vgabios(unsigned char *buf, XenHostPCIDevice *dev)
+{
+    char rom_file[64];
+    FILE *fp;
+    uint8_t val;
+    struct stat st;
+    uint16_t magic = 0;
+    int ret = 0;
+
+    snprintf(rom_file, sizeof(rom_file),
+             "/sys/bus/pci/devices/%04x:%02x:%02x.%d/rom",
+             dev->domain, dev->bus, dev->dev,
+             dev->func);
+
+    if (stat(rom_file, &st)) {
+        return -ENODEV;
+    }
+
+    if (access(rom_file, F_OK)) {
+        XEN_PT_ERR(NULL, "pci-assign: Insufficient privileges for %s",
+                    rom_file);
+        return -ENODEV;
+    }
+
+    /* Write "1" to the ROM file to enable it */
+    fp = fopen(rom_file, "r+");
+    if (fp == NULL) {
+        return -EACCES;
+    }
+    val = 1;
+    if (fwrite(&val, 1, 1, fp) != 1) {
+        XEN_PT_LOG("%s\n", "Failed to enable pci-sysfs rom file");
+        ret = -EIO;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    /*
+     * Check if it a real bios extension.
+     * The magic number is 0xAA55.
+     */
+    if (!fread(&magic, sizeof(magic), 1, fp)) {
+        XEN_PT_ERR(NULL, "VGA: can't get magic.\n");
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    if (magic != 0xAA55) {
+        XEN_PT_ERR(NULL, "VGA: wrong magic %x.\n", magic);
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    if (!fread(buf, 1, st.st_size, fp)) {
+        XEN_PT_ERR(NULL, "VGA: pci-assign: Cannot read from host %s", rom_file);
+        XEN_PT_LOG(NULL, "VGA: Device option ROM contents are probably invalid "
+                     "(check dmesg).\nSkip option ROM probe with rombar=0, "
+                     "or load from file with romfile=\n");
+    }
+
+close_rom:
+    /* Write "0" to disable ROM */
+    fseek(fp, 0, SEEK_SET);
+    val = 0;
+    if (!fwrite(&val, 1, 1, fp)) {
+        ret = -EIO;
+        XEN_PT_LOG("%s\n", "Failed to disable pci-sysfs rom file");
+    }
+    fclose(fp);
+    return ret;
+}
+
+/* Allocated 128K for the vga bios */
+#define VGA_BIOS_DEFAULT_SIZE (0x20000)
+
+int xen_pt_setup_vga(XenHostPCIDevice *dev)
+{
+    unsigned char *bios = NULL;
+    int bios_size = 0;
+    char *c = NULL;
+    char checksum = 0;
+    int rc = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return rc;
+    }
+
+    bios = g_malloc0(VGA_BIOS_DEFAULT_SIZE);
+
+    bios_size = get_vgabios(bios, dev);

hw/xen/xen_pt_graphics.c line 218

Quoted 10 lines
hw/xen/xen_pt_graphics.c new file +10 -0
+    if (bios_size) {
+        XEN_PT_ERR(NULL, "VGA: Error %d getting VBIOS!\n", bios_size);
+        if (bios_size < 0) {
+            XEN_PT_ERR(NULL, "VGA: Error (%s).\n", strerror(bios_size));
+        }
+        rc = -1;
+        goto out;
+    }
+
+    /* Adjust the bios checksum */

It's easy to see that you do this here, but *why* do you do it? That's what the comment should explain.
Do you see many ROMs with an invalid checksum
in the field?

Quoted 64 lines
hw/xen/xen_pt_graphics.c new file +14 -0
+    for (c = (char *)bios; c < ((char *)bios + bios_size); c++) {
+        checksum += *c;
+    }
+    if (checksum) {
+        bios[bios_size - 1] -= checksum;
+        XEN_PT_LOG(NULL, "vga bios checksum is adjusted!\n");
+    }
+
+    /* Currently we fixed this address as a primary. */
+    cpu_physical_memory_rw(0xc0000, bios, bios_size, 1);
+out:
+    g_free(bios);
+    return rc;
+}
qemu-options.hx +9 -0
index ff76ad4..1c77baa 100644
@@ -1066,6 +1066,15 @@ STEXI
 Rotate graphical output some deg left (only PXA LCD).
 ETEXI
 
+DEF("gfx_passthru", 0, QEMU_OPTION_gfx_passthru,
+    "-gfx_passthru   enable Intel IGD passthrough by XEN\n",
+    QEMU_ARCH_ALL)
+STEXI
+@item -gfx_passthru
+@findex -gfx_passthru
+Enable Intel IGD passthrough by XEN
+ETEXI
+
 DEF("vga", HAS_ARG, QEMU_OPTION_vga,
     "-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|none]\n"
     "                select video card type\n", QEMU_ARCH_ALL)
vl.c +10 -0
index a1686ef..c5b572d 100644
@@ -1418,6 +1418,13 @@ static void configure_msg(QemuOpts *opts)
     enable_timestamp_msg = qemu_opt_get_bool(opts, "timestamp", true);
 }
 
+/* We still need this for compatibility with XEN. */
+int xen_has_gfx_passthru;
+static void xen_gfx_passthru(const char *optarg)
+{
+    xen_has_gfx_passthru = 1;
+}
+
 /***********************************************************/
 /* USB devices */
 
@@ -3945,6 +3952,9 @@ int main(int argc, char **argv, char **envp)
                     exit(1);
                 }
                 break;
+            case QEMU_OPTION_gfx_passthru:
+                xen_gfx_passthru(optarg);
+                break;
             default:
                 os_parse_cmd_args(popt->index, optarg);
             }
Signature · 1 line
1.9.1
#5 lore raw

Re: [Qemu-devel] [v5][PATCH 1/5] xen, gfx passthrough: basic graphics passthrough support

Quoted 6 lines · Michael S. Tsirkin
Quoted 5 lines · Tiejun Chen

basic gfx passthrough support:
- add a vga type for gfx passthrough
- retrieve VGA bios from sysfs, then load it to guest at 0xC0000
- register/unregister legacy VGA I/O ports and MMIOs for passthrough GFX

Quoted 7 lines
Quoted 5 lines

The original patch is from Weidong Han <[email protected]>

ROM loading code is duplicated from assigned_dev_load_option_rom.

Yes. Do you hint we need to split this?

Quoted 2 lines

Would it be a problem for you to create a memory region holding the ROM?

Sorry, could you tell me what should do exactly?

Quoted 1 line

You won't need cpu_physical_memory_rw then, either, or need

How to make sure this is fixed at 0xc0000?

Thanks
Tiejun

Quoted 423 lines

the VGA_BIOS_DEFAULT_SIZE hack.

Quoted 336 lines

---
v5:

* Just rebase.

v4:

* Fix some typos in the patch head description.
* Improve some comments.
* Given that xen_pt_register_vga_regions()/xen_pt_unregister_vga_regions() are called unconditionally, so we just return 0 there.
* Remove one spurious change.

v3:

* Fix some typos.
* Add more comments to make that readable.
* Improve some return paths.

v2:

* retrieve VGA bios from sysfs properly.
* redefine some function name.

  hw/xen/Makefile.objs         |   2 +-
  hw/xen/xen-host-pci-device.c |   5 +
  hw/xen/xen-host-pci-device.h |   1 +
  hw/xen/xen_pt.c              |  10 ++
  hw/xen/xen_pt.h              |   4 +
  hw/xen/xen_pt_graphics.c     | 232 +++++++++++++++++++++++++++++++++++++++++++
  qemu-options.hx              |   9 ++
  vl.c                         |  10 ++
  8 files changed, 272 insertions(+), 1 deletion(-)

create mode 100644 hw/xen/xen_pt_graphics.c

hw/xen/Makefile.objs +1 -1
index a0ca0aa..77b7dae 100644
@@ -2,4 +2,4 @@
  common-obj-$(CONFIG_XEN_BACKEND) += xen_backend.o xen_devconfig.o
 
  obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
-obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
+obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o xen_pt_graphics.o
hw/xen/xen-host-pci-device.c +5 -0
index 743b37b..a54b7de 100644
@@ -376,6 +376,11 @@ int xen_host_pci_device_get(XenHostPCIDevice *d, uint16_t domain,
          goto error;
      }
      d->irq = v;
+    rc = xen_host_pci_get_hex_value(d, "class", &v);
+    if (rc) {
+        goto error;
+    }
+    d->class_code = v;
      d->is_virtfn = xen_host_pci_dev_is_virtfn(d);
 
      return 0;
hw/xen/xen-host-pci-device.h +1 -0
index c2486f0..f1e1c30 100644
@@ -25,6 +25,7 @@ typedef struct XenHostPCIDevice {
 
      uint16_t vendor_id;
      uint16_t device_id;
+    uint32_t class_code;
      int irq;
 
      XenHostPCIIORegion io_regions[PCI_NUM_REGIONS - 1];
hw/xen/xen_pt.c +10 -0
index be4220b..dac4238 100644
@@ -450,6 +450,7 @@ static int xen_pt_register_regions(XenPCIPassthroughState *s)
                     d->rom.size, d->rom.base_addr);
      }
 
+    xen_pt_register_vga_regions(d);
      return 0;
  }
 
@@ -470,6 +471,8 @@ static void xen_pt_unregister_regions(XenPCIPassthroughState *s)
      if (d->rom.base_addr && d->rom.size) {
          memory_region_destroy(&s->rom);
      }
+
+    xen_pt_unregister_vga_regions(d);
  }
 
  /* region mapping */
@@ -693,6 +696,13 @@ static int xen_pt_initfn(PCIDevice *d)
      /* Handle real device's MMIO/PIO BARs */
      xen_pt_register_regions(s);
 
+    /* Setup VGA bios for passthrough GFX */
+    if (xen_pt_setup_vga(&s->real_device) < 0) {
+        XEN_PT_ERR(d, "Setup VGA BIOS of passthrough GFX failed!\n");
+        xen_host_pci_device_put(&s->real_device);
+        return -1;
+    }
+
      /* reinitialize each config register to be emulated */
      if (xen_pt_config_init(s)) {
          XEN_PT_ERR(d, "PCI Config space initialisation failed.\n");
hw/xen/xen_pt.h +4 -0
index 942dc60..4d3a18d 100644
@@ -298,5 +298,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
      return s->msix && s->msix->bar_index == bar;
  }
 
+extern int xen_has_gfx_passthru;
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_setup_vga(XenHostPCIDevice *dev);
 
  #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c new file +208 -0
new file mode 100644
index 0000000..461e526
@@ -0,0 +1,232 @@
+/*
+ * graphics passthrough
+ */
+#include "xen_pt.h"
+#include "xen-host-pci-device.h"
+#include "hw/xen/xen_backend.h"
+
+static int is_vga_passthrough(XenHostPCIDevice *dev)
+{
+    return (xen_has_gfx_passthru
+            && ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
+}
+
+typedef struct VGARegion {
+    int type;           /* Memory or port I/O */
+    uint64_t guest_base_addr;
+    uint64_t machine_base_addr;
+    uint64_t size;    /* size of the region */
+    int rc;
+} VGARegion;
+
+#define IORESOURCE_IO           0x00000100
+#define IORESOURCE_MEM          0x00000200
+
+static struct VGARegion vga_args[] = {
+    {
+        .type = IORESOURCE_IO,
+        .guest_base_addr = 0x3B0,
+        .machine_base_addr = 0x3B0,
+        .size = 0xC,
+        .rc = -1,
+    },
+    {
+        .type = IORESOURCE_IO,
+        .guest_base_addr = 0x3C0,
+        .machine_base_addr = 0x3C0,
+        .size = 0x20,
+        .rc = -1,
+    },
+    {
+        .type = IORESOURCE_MEM,
+        .guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
+        .machine_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
+        .size = 0x20,
+        .rc = -1,
+    },
+};
+
+/*
+ * register VGA resources for the domain with assigned gfx
+ */
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev)
+{
+    int i = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return 0;
+    }
+
+    for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
+        if (vga_args[i].type == IORESOURCE_IO) {
+            vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_ADD_MAPPING);
+        } else {
+            vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_ADD_MAPPING);
+        }
+
+        if (vga_args[i].rc) {
+            XEN_PT_ERR(NULL, "VGA %s mapping failed! (rc: %i)\n",
+                    vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
+                    vga_args[i].rc);
+            return vga_args[i].rc;
+        }
+    }
+
+    return 0;
+}
+
+/*
+ * unregister VGA resources for the domain with assigned gfx
+ */
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
+{
+    int i = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return 0;
+    }
+
+    for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
+        if (vga_args[i].type == IORESOURCE_IO) {
+            vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_REMOVE_MAPPING);
+        } else {
+            vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_REMOVE_MAPPING);
+        }
+
+        if (vga_args[i].rc) {
+            XEN_PT_ERR(NULL, "VGA %s unmapping failed! (rc: %i)\n",
+                    vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
+                    vga_args[i].rc);
+            return vga_args[i].rc;
+        }
+    }
+
+    return 0;
+}
+
+static int get_vgabios(unsigned char *buf, XenHostPCIDevice *dev)
+{
+    char rom_file[64];
+    FILE *fp;
+    uint8_t val;
+    struct stat st;
+    uint16_t magic = 0;
+    int ret = 0;
+
+    snprintf(rom_file, sizeof(rom_file),
+             "/sys/bus/pci/devices/%04x:%02x:%02x.%d/rom",
+             dev->domain, dev->bus, dev->dev,
+             dev->func);
+
+    if (stat(rom_file, &st)) {
+        return -ENODEV;
+    }
+
+    if (access(rom_file, F_OK)) {
+        XEN_PT_ERR(NULL, "pci-assign: Insufficient privileges for %s",
+                    rom_file);
+        return -ENODEV;
+    }
+
+    /* Write "1" to the ROM file to enable it */
+    fp = fopen(rom_file, "r+");
+    if (fp == NULL) {
+        return -EACCES;
+    }
+    val = 1;
+    if (fwrite(&val, 1, 1, fp) != 1) {
+        XEN_PT_LOG("%s\n", "Failed to enable pci-sysfs rom file");
+        ret = -EIO;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    /*
+     * Check if it a real bios extension.
+     * The magic number is 0xAA55.
+     */
+    if (!fread(&magic, sizeof(magic), 1, fp)) {
+        XEN_PT_ERR(NULL, "VGA: can't get magic.\n");
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    if (magic != 0xAA55) {
+        XEN_PT_ERR(NULL, "VGA: wrong magic %x.\n", magic);
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    if (!fread(buf, 1, st.st_size, fp)) {
+        XEN_PT_ERR(NULL, "VGA: pci-assign: Cannot read from host %s", rom_file);
+        XEN_PT_LOG(NULL, "VGA: Device option ROM contents are probably invalid "
+                     "(check dmesg).\nSkip option ROM probe with rombar=0, "
+                     "or load from file with romfile=\n");
+    }
+
+close_rom:
+    /* Write "0" to disable ROM */
+    fseek(fp, 0, SEEK_SET);
+    val = 0;
+    if (!fwrite(&val, 1, 1, fp)) {
+        ret = -EIO;
+        XEN_PT_LOG("%s\n", "Failed to disable pci-sysfs rom file");
+    }
+    fclose(fp);
+    return ret;
+}
+
+/* Allocated 128K for the vga bios */
+#define VGA_BIOS_DEFAULT_SIZE (0x20000)
+
+int xen_pt_setup_vga(XenHostPCIDevice *dev)
+{
+    unsigned char *bios = NULL;
+    int bios_size = 0;
+    char *c = NULL;
+    char checksum = 0;
+    int rc = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return rc;
+    }
+
+    bios = g_malloc0(VGA_BIOS_DEFAULT_SIZE);
+
+    bios_size = get_vgabios(bios, dev);

hw/xen/xen_pt_graphics.c line 218

Quoted 10 lines
hw/xen/xen_pt_graphics.c new file +10 -0
+    if (bios_size) {
+        XEN_PT_ERR(NULL, "VGA: Error %d getting VBIOS!\n", bios_size);
+        if (bios_size < 0) {
+            XEN_PT_ERR(NULL, "VGA: Error (%s).\n", strerror(bios_size));
+        }
+        rc = -1;
+        goto out;
+    }
+
+    /* Adjust the bios checksum */

It's easy to see that you do this here, but *why* do you do it? That's what the comment should explain.
Do you see many ROMs with an invalid checksum
in the field?

Quoted 64 lines
hw/xen/xen_pt_graphics.c new file +14 -0
+    for (c = (char *)bios; c < ((char *)bios + bios_size); c++) {
+        checksum += *c;
+    }
+    if (checksum) {
+        bios[bios_size - 1] -= checksum;
+        XEN_PT_LOG(NULL, "vga bios checksum is adjusted!\n");
+    }
+
+    /* Currently we fixed this address as a primary. */
+    cpu_physical_memory_rw(0xc0000, bios, bios_size, 1);
+out:
+    g_free(bios);
+    return rc;
+}
qemu-options.hx +9 -0
index ff76ad4..1c77baa 100644
@@ -1066,6 +1066,15 @@ STEXI
  Rotate graphical output some deg left (only PXA LCD).
  ETEXI
 
+DEF("gfx_passthru", 0, QEMU_OPTION_gfx_passthru,
+    "-gfx_passthru   enable Intel IGD passthrough by XEN\n",
+    QEMU_ARCH_ALL)
+STEXI
+@item -gfx_passthru
+@findex -gfx_passthru
+Enable Intel IGD passthrough by XEN
+ETEXI
+
  DEF("vga", HAS_ARG, QEMU_OPTION_vga,
      "-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|none]\n"
      "                select video card type\n", QEMU_ARCH_ALL)
vl.c +10 -1
index a1686ef..c5b572d 100644
@@ -1418,6 +1418,13 @@ static void configure_msg(QemuOpts *opts)
      enable_timestamp_msg = qemu_opt_get_bool(opts, "timestamp", true);
  }
 
+/* We still need this for compatibility with XEN. */
+int xen_has_gfx_passthru;
+static void xen_gfx_passthru(const char *optarg)
+{
+    xen_has_gfx_passthru = 1;
+}
+
  /***********************************************************/
  /* USB devices */
 
@@ -3945,6 +3952,9 @@ int main(int argc, char **argv, char **envp)
                      exit(1);
                  }
                  break;
+            case QEMU_OPTION_gfx_passthru:
+                xen_gfx_passthru(optarg);
+                break;
              default:
                  os_parse_cmd_args(popt->index, optarg);
              }
--

1.9.1

#6 lore raw

Re: [Qemu-devel] [v5][PATCH 1/5] xen, gfx passthrough: basic graphics passthrough support

Quoted 9 lines · Tiejun
Quoted 8 lines · Michael S. Tsirkin
Quoted 7 lines · Tiejun Chen

basic gfx passthrough support:
- add a vga type for gfx passthrough
- retrieve VGA bios from sysfs, then load it to guest at 0xC0000
- register/unregister legacy VGA I/O ports and MMIOs for passthrough GFX

The original patch is from Weidong Han <[email protected]>

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines

ROM loading code is duplicated from assigned_dev_load_option_rom.

Yes. Do you hint we need to split this?

Absolutely. These two drivers need to start sharing code.

Quoted 4 lines
Quoted 2 lines

Would it be a problem for you to create a memory region holding the ROM?

Sorry, could you tell me what should do exactly?

Split common code out and reuse :)

Quoted 6 lines
Quoted 1 line

You won't need cpu_physical_memory_rw then, either, or need

How to make sure this is fixed at 0xc0000?

Thanks
Tiejun

I guess you just add it as subregion of system memory at this offset, maybe with a higher priority than RAM.
Right, Paolo?

Quoted 423 lines
Quoted 423 lines

the VGA_BIOS_DEFAULT_SIZE hack.

Quoted 336 lines

---
v5:

* Just rebase.

v4:

* Fix some typos in the patch head description.
* Improve some comments.
* Given that xen_pt_register_vga_regions()/xen_pt_unregister_vga_regions() are called unconditionally, so we just return 0 there.
* Remove one spurious change.

v3:

* Fix some typos.
* Add more comments to make that readable.
* Improve some return paths.

v2:

* retrieve VGA bios from sysfs properly.
* redefine some function name.

 hw/xen/Makefile.objs         |   2 +-
 hw/xen/xen-host-pci-device.c |   5 +
 hw/xen/xen-host-pci-device.h |   1 +
 hw/xen/xen_pt.c              |  10 ++
 hw/xen/xen_pt.h              |   4 +
 hw/xen/xen_pt_graphics.c     | 232 +++++++++++++++++++++++++++++++++++++++++++
 qemu-options.hx              |   9 ++
 vl.c                         |  10 ++
 8 files changed, 272 insertions(+), 1 deletion(-)
 create mode 100644 hw/xen/xen_pt_graphics.c
hw/xen/Makefile.objs +1 -1
index a0ca0aa..77b7dae 100644
@@ -2,4 +2,4 @@
 common-obj-$(CONFIG_XEN_BACKEND) += xen_backend.o xen_devconfig.o
 
 obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
-obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
+obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o xen_pt_graphics.o
hw/xen/xen-host-pci-device.c +5 -0
index 743b37b..a54b7de 100644
@@ -376,6 +376,11 @@ int xen_host_pci_device_get(XenHostPCIDevice *d, uint16_t domain,
         goto error;
     }
     d->irq = v;
+    rc = xen_host_pci_get_hex_value(d, "class", &v);
+    if (rc) {
+        goto error;
+    }
+    d->class_code = v;
     d->is_virtfn = xen_host_pci_dev_is_virtfn(d);
 
     return 0;
hw/xen/xen-host-pci-device.h +1 -0
index c2486f0..f1e1c30 100644
@@ -25,6 +25,7 @@ typedef struct XenHostPCIDevice {
 
     uint16_t vendor_id;
     uint16_t device_id;
+    uint32_t class_code;
     int irq;
 
     XenHostPCIIORegion io_regions[PCI_NUM_REGIONS - 1];
hw/xen/xen_pt.c +10 -0
index be4220b..dac4238 100644
@@ -450,6 +450,7 @@ static int xen_pt_register_regions(XenPCIPassthroughState *s)
                    d->rom.size, d->rom.base_addr);
     }
 
+    xen_pt_register_vga_regions(d);
     return 0;
 }
 
@@ -470,6 +471,8 @@ static void xen_pt_unregister_regions(XenPCIPassthroughState *s)
     if (d->rom.base_addr && d->rom.size) {
         memory_region_destroy(&s->rom);
     }
+
+    xen_pt_unregister_vga_regions(d);
 }
 
 /* region mapping */
@@ -693,6 +696,13 @@ static int xen_pt_initfn(PCIDevice *d)
     /* Handle real device's MMIO/PIO BARs */
     xen_pt_register_regions(s);
 
+    /* Setup VGA bios for passthrough GFX */
+    if (xen_pt_setup_vga(&s->real_device) < 0) {
+        XEN_PT_ERR(d, "Setup VGA BIOS of passthrough GFX failed!\n");
+        xen_host_pci_device_put(&s->real_device);
+        return -1;
+    }
+
     /* reinitialize each config register to be emulated */
     if (xen_pt_config_init(s)) {
         XEN_PT_ERR(d, "PCI Config space initialisation failed.\n");
hw/xen/xen_pt.h +4 -0
index 942dc60..4d3a18d 100644
@@ -298,5 +298,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
     return s->msix && s->msix->bar_index == bar;
 }
 
+extern int xen_has_gfx_passthru;
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
+int xen_pt_setup_vga(XenHostPCIDevice *dev);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c new file +208 -0
new file mode 100644
index 0000000..461e526
@@ -0,0 +1,232 @@
+/*
+ * graphics passthrough
+ */
+#include "xen_pt.h"
+#include "xen-host-pci-device.h"
+#include "hw/xen/xen_backend.h"
+
+static int is_vga_passthrough(XenHostPCIDevice *dev)
+{
+    return (xen_has_gfx_passthru
+            && ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
+}
+
+typedef struct VGARegion {
+    int type;           /* Memory or port I/O */
+    uint64_t guest_base_addr;
+    uint64_t machine_base_addr;
+    uint64_t size;    /* size of the region */
+    int rc;
+} VGARegion;
+
+#define IORESOURCE_IO           0x00000100
+#define IORESOURCE_MEM          0x00000200
+
+static struct VGARegion vga_args[] = {
+    {
+        .type = IORESOURCE_IO,
+        .guest_base_addr = 0x3B0,
+        .machine_base_addr = 0x3B0,
+        .size = 0xC,
+        .rc = -1,
+    },
+    {
+        .type = IORESOURCE_IO,
+        .guest_base_addr = 0x3C0,
+        .machine_base_addr = 0x3C0,
+        .size = 0x20,
+        .rc = -1,
+    },
+    {
+        .type = IORESOURCE_MEM,
+        .guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
+        .machine_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
+        .size = 0x20,
+        .rc = -1,
+    },
+};
+
+/*
+ * register VGA resources for the domain with assigned gfx
+ */
+int xen_pt_register_vga_regions(XenHostPCIDevice *dev)
+{
+    int i = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return 0;
+    }
+
+    for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
+        if (vga_args[i].type == IORESOURCE_IO) {
+            vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_ADD_MAPPING);
+        } else {
+            vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_ADD_MAPPING);
+        }
+
+        if (vga_args[i].rc) {
+            XEN_PT_ERR(NULL, "VGA %s mapping failed! (rc: %i)\n",
+                    vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
+                    vga_args[i].rc);
+            return vga_args[i].rc;
+        }
+    }
+
+    return 0;
+}
+
+/*
+ * unregister VGA resources for the domain with assigned gfx
+ */
+int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
+{
+    int i = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return 0;
+    }
+
+    for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
+        if (vga_args[i].type == IORESOURCE_IO) {
+            vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_REMOVE_MAPPING);
+        } else {
+            vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
+                            vga_args[i].guest_base_addr,
+                            vga_args[i].machine_base_addr,
+                            vga_args[i].size, DPCI_REMOVE_MAPPING);
+        }
+
+        if (vga_args[i].rc) {
+            XEN_PT_ERR(NULL, "VGA %s unmapping failed! (rc: %i)\n",
+                    vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
+                    vga_args[i].rc);
+            return vga_args[i].rc;
+        }
+    }
+
+    return 0;
+}
+
+static int get_vgabios(unsigned char *buf, XenHostPCIDevice *dev)
+{
+    char rom_file[64];
+    FILE *fp;
+    uint8_t val;
+    struct stat st;
+    uint16_t magic = 0;
+    int ret = 0;
+
+    snprintf(rom_file, sizeof(rom_file),
+             "/sys/bus/pci/devices/%04x:%02x:%02x.%d/rom",
+             dev->domain, dev->bus, dev->dev,
+             dev->func);
+
+    if (stat(rom_file, &st)) {
+        return -ENODEV;
+    }
+
+    if (access(rom_file, F_OK)) {
+        XEN_PT_ERR(NULL, "pci-assign: Insufficient privileges for %s",
+                    rom_file);
+        return -ENODEV;
+    }
+
+    /* Write "1" to the ROM file to enable it */
+    fp = fopen(rom_file, "r+");
+    if (fp == NULL) {
+        return -EACCES;
+    }
+    val = 1;
+    if (fwrite(&val, 1, 1, fp) != 1) {
+        XEN_PT_LOG("%s\n", "Failed to enable pci-sysfs rom file");
+        ret = -EIO;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    /*
+     * Check if it a real bios extension.
+     * The magic number is 0xAA55.
+     */
+    if (!fread(&magic, sizeof(magic), 1, fp)) {
+        XEN_PT_ERR(NULL, "VGA: can't get magic.\n");
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    if (magic != 0xAA55) {
+        XEN_PT_ERR(NULL, "VGA: wrong magic %x.\n", magic);
+        ret = -ENODEV;
+        goto close_rom;
+    }
+    fseek(fp, 0, SEEK_SET);
+
+    if (!fread(buf, 1, st.st_size, fp)) {
+        XEN_PT_ERR(NULL, "VGA: pci-assign: Cannot read from host %s", rom_file);
+        XEN_PT_LOG(NULL, "VGA: Device option ROM contents are probably invalid "
+                     "(check dmesg).\nSkip option ROM probe with rombar=0, "
+                     "or load from file with romfile=\n");
+    }
+
+close_rom:
+    /* Write "0" to disable ROM */
+    fseek(fp, 0, SEEK_SET);
+    val = 0;
+    if (!fwrite(&val, 1, 1, fp)) {
+        ret = -EIO;
+        XEN_PT_LOG("%s\n", "Failed to disable pci-sysfs rom file");
+    }
+    fclose(fp);
+    return ret;
+}
+
+/* Allocated 128K for the vga bios */
+#define VGA_BIOS_DEFAULT_SIZE (0x20000)
+
+int xen_pt_setup_vga(XenHostPCIDevice *dev)
+{
+    unsigned char *bios = NULL;
+    int bios_size = 0;
+    char *c = NULL;
+    char checksum = 0;
+    int rc = 0;
+
+    if (!is_vga_passthrough(dev)) {
+        return rc;
+    }
+
+    bios = g_malloc0(VGA_BIOS_DEFAULT_SIZE);
+
+    bios_size = get_vgabios(bios, dev);

hw/xen/xen_pt_graphics.c line 218

Quoted 10 lines
hw/xen/xen_pt_graphics.c new file +10 -0
+    if (bios_size) {
+        XEN_PT_ERR(NULL, "VGA: Error %d getting VBIOS!\n", bios_size);
+        if (bios_size < 0) {
+            XEN_PT_ERR(NULL, "VGA: Error (%s).\n", strerror(bios_size));
+        }
+        rc = -1;
+        goto out;
+    }
+
+    /* Adjust the bios checksum */

It's easy to see that you do this here, but *why* do you do it? That's what the comment should explain.
Do you see many ROMs with an invalid checksum
in the field?

Quoted 64 lines
hw/xen/xen_pt_graphics.c new file +14 -0
+    for (c = (char *)bios; c < ((char *)bios + bios_size); c++) {
+        checksum += *c;
+    }
+    if (checksum) {
+        bios[bios_size - 1] -= checksum;
+        XEN_PT_LOG(NULL, "vga bios checksum is adjusted!\n");
+    }
+
+    /* Currently we fixed this address as a primary. */
+    cpu_physical_memory_rw(0xc0000, bios, bios_size, 1);
+out:
+    g_free(bios);
+    return rc;
+}
qemu-options.hx +9 -0
index ff76ad4..1c77baa 100644
@@ -1066,6 +1066,15 @@ STEXI
 Rotate graphical output some deg left (only PXA LCD).
 ETEXI
 
+DEF("gfx_passthru", 0, QEMU_OPTION_gfx_passthru,
+    "-gfx_passthru   enable Intel IGD passthrough by XEN\n",
+    QEMU_ARCH_ALL)
+STEXI
+@item -gfx_passthru
+@findex -gfx_passthru
+Enable Intel IGD passthrough by XEN
+ETEXI
+
 DEF("vga", HAS_ARG, QEMU_OPTION_vga,
     "-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|none]\n"
     "                select video card type\n", QEMU_ARCH_ALL)
vl.c +10 -1
index a1686ef..c5b572d 100644
@@ -1418,6 +1418,13 @@ static void configure_msg(QemuOpts *opts)
     enable_timestamp_msg = qemu_opt_get_bool(opts, "timestamp", true);
 }
 
+/* We still need this for compatibility with XEN. */
+int xen_has_gfx_passthru;
+static void xen_gfx_passthru(const char *optarg)
+{
+    xen_has_gfx_passthru = 1;
+}
+
 /***********************************************************/
 /* USB devices */
 
@@ -3945,6 +3952,9 @@ int main(int argc, char **argv, char **envp)
                     exit(1);
                 }
                 break;
+            case QEMU_OPTION_gfx_passthru:
+                xen_gfx_passthru(optarg);
+                break;
             default:
                 os_parse_cmd_args(popt->index, optarg);
             }
--

1.9.1

#7 lore raw

PATCH v5 2/5 xen, gfx passthrough: create pseudo intel isa bridge

In reply to Tiejun Chen

ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0 to make graphics device passthrough work well for VMM, that only need to expose this pseudo ISA bridge to let driver know the real hardware underneath.

The original patch is from Allen Kay <[email protected]>

---
v5:

* Don't set this ISA class property, instead, just fake this ISA bridge with 00:1f.0.

v4:

* Remove some unnecessary "return" in void foo().

v3:

* Fix some typos.
* Improve some return paths.

v2:

* Nothing is changed.

 hw/xen/xen_pt_graphics.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
hw/xen/xen_pt_graphics.c +61 -0
index 461e526..974b7e9 100644
@@ -230,3 +230,64 @@ out:
     g_free(bios);
     return rc;
 }
+
+static uint32_t isa_bridge_read_config(PCIDevice *d, uint32_t addr, int len)
+{
+    return pci_default_read_config(d, addr, len);
+}
+
+static void isa_bridge_write_config(PCIDevice *d, uint32_t addr, uint32_t v,
+                                    int len)
+{
+    pci_default_write_config(d, addr, v, len);
+}
+
+static void isa_bridge_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_read = isa_bridge_read_config;
+    k->config_write = isa_bridge_write_config;
+};
+
+typedef struct {
+    PCIDevice dev;
+} ISABridgeState;
+
+static TypeInfo isa_bridge_info = {
+    .name          = "pseudo-intel-pch-isa-bridge",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(ISABridgeState),
+    .class_init = isa_bridge_class_init,
+};
+
+static void xen_pt_graphics_register_types(void)
+{
+    type_register_static(&isa_bridge_info);
+}
+
+type_init(xen_pt_graphics_register_types)
+
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+    qdev_init_nofail(&dev->qdev);
+
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}
Signature · 1 line
1.9.1
#8 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+    qdev_init_nofail(&dev->qdev);
+

hw/xen/xen_pt_graphics.c out: · line 293

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

This patch doesn't compile on its own (this static function is unused).

pci_create_pch should be moved in this patch.

Paolo

#9 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 29 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 15 lines

+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

hw/xen/xen_pt_graphics.c +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

hw/xen/xen_pt_graphics.c +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

hw/xen/xen_pt_graphics.c out: · line 293

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

This patch doesn't compile on its own (this static function is unused).

Quoted 2 lines

pci_create_pch should be moved in this patch.

Okay I will try this.

Thanks
Tiejun

#10 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

In reply to Tiejun Chen
Quoted 49 lines · Tiejun Chen

ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0 to make graphics device passthrough work well for VMM, that only need to expose this pseudo ISA bridge to let driver know the real hardware underneath.

The original patch is from Allen Kay <[email protected]>

---
v5:

* Don't set this ISA class property, instead, just fake this ISA bridge with 00:1f.0.

v4:

* Remove some unnecessary "return" in void foo().

v3:

* Fix some typos.
* Improve some return paths.

v2:

* Nothing is changed.

 hw/xen/xen_pt_graphics.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
hw/xen/xen_pt_graphics.c +9 -0
index 461e526..974b7e9 100644
@@ -230,3 +230,64 @@ out:
     g_free(bios);
     return rc;
 }
+
+static uint32_t isa_bridge_read_config(PCIDevice *d, uint32_t addr, int len)
+{
+    return pci_default_read_config(d, addr, len);
+}
+
+static void isa_bridge_write_config(PCIDevice *d, uint32_t addr, uint32_t v,
+                                    int len)
+{

hw/xen/xen_pt_graphics.c out: · line 251

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+    pci_default_write_config(d, addr, v, len);
+}
+
+static void isa_bridge_class_init(ObjectClass *klass, void *data)
+{
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_read = isa_bridge_read_config;
+    k->config_write = isa_bridge_write_config;
+};

You don't need these stubs, just don't fill anything, pci core will use defaults then.

hw/xen/xen_pt_graphics.c out: · line 256

Quoted 5 lines
hw/xen/xen_pt_graphics.c +5 -0
+
+typedef struct {
+    PCIDevice dev;
+} ISABridgeState;
+

Nor do you need an empty structure if it has no state.

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+static TypeInfo isa_bridge_info = {
+    .name          = "pseudo-intel-pch-isa-bridge",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(ISABridgeState),
+    .class_init = isa_bridge_class_init,
+};
+
+static void xen_pt_graphics_register_types(void)
+{
+    type_register_static(&isa_bridge_info);
+}
+
+type_init(xen_pt_graphics_register_types)

hw/xen/xen_pt_graphics.c out: · line 279

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */

A typo and confusing wording above, I'm not really sure what this comment means.
Maybe:

/* Create a fake ISA bridge device at the location expected by guests. */

hw/xen/xen_pt_graphics.c out: · line 287

Quoted 8 lines
hw/xen/xen_pt_graphics.c +8 -0
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+    qdev_init_nofail(&dev->qdev);
+
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);

Host PCI device is the VGA card?
So why does it make sense to get it's vendor/device/revision and stick in the ISA bridge?

Also change rid to uint8_t, you won't need to cast then.

Quoted 8 lines
hw/xen/xen_pt_graphics.c +6 -0
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}
Signature · 1 line
1.9.1
#11 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun Chen

ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0 to make graphics device passthrough work well for VMM, that only need to expose this pseudo ISA bridge to let driver know the real hardware underneath.

The original patch is from Allen Kay <[email protected]>

---
v5:

* Don't set this ISA class property, instead, just fake this ISA bridge with 00:1f.0.

v4:

* Remove some unnecessary "return" in void foo().

v3:

* Fix some typos.
* Improve some return paths.

v2:

* Nothing is changed.

  hw/xen/xen_pt_graphics.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
  1 file changed, 61 insertions(+)
hw/xen/xen_pt_graphics.c +14 -0
index 461e526..974b7e9 100644
@@ -230,3 +230,64 @@ out:
      g_free(bios);
      return rc;
  }
+
+static uint32_t isa_bridge_read_config(PCIDevice *d, uint32_t addr, int len)
+{
+    return pci_default_read_config(d, addr, len);
+}
+
+static void isa_bridge_write_config(PCIDevice *d, uint32_t addr, uint32_t v,
+                                    int len)
+{
+    pci_default_write_config(d, addr, v, len);
+}
+
+static void isa_bridge_class_init(ObjectClass *klass, void *data)
+{
Quoted 8 lines

hw/xen/xen_pt_graphics.c out: · line 251

Quoted 5 lines
hw/xen/xen_pt_graphics.c +5 -0
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_read = isa_bridge_read_config;
+    k->config_write = isa_bridge_write_config;
+};

You don't need these stubs, just don't fill anything, pci core will use defaults then.

I guess these stubs are left to extend something in the future. But maybe we can remove them now.

Quoted 37 lines

hw/xen/xen_pt_graphics.c out: · line 256

Quoted 6 lines
hw/xen/xen_pt_graphics.c +5 -0
+
+typedef struct {
+    PCIDevice dev;
+} ISABridgeState;
+

Nor do you need an empty structure if it has no state.

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+static TypeInfo isa_bridge_info = {
+    .name          = "pseudo-intel-pch-isa-bridge",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(ISABridgeState),
+    .class_init = isa_bridge_class_init,
+};
+
+static void xen_pt_graphics_register_types(void)
+{
+    type_register_static(&isa_bridge_info);
+}
+
+type_init(xen_pt_graphics_register_types)

hw/xen/xen_pt_graphics.c out: · line 279

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */

A typo and confusing wording above, I'm not really sure what this comment means.
Maybe:

Quoted 2 lines

/* Create a fake ISA bridge device at the location expected by guests. */

Good comments so thanks so much.

Quoted 11 lines

hw/xen/xen_pt_graphics.c out: · line 287

Quoted 9 lines
hw/xen/xen_pt_graphics.c +8 -0
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+    qdev_init_nofail(&dev->qdev);
+
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);

Host PCI device is the VGA card?

This is a real ISA bridge.

Quoted 2 lines

So why does it make sense to get it's vendor/device/revision and stick in the ISA bridge?

The Intel generation of integrated graphics needs to probe this ISA bridge to initialize the i915 driver properly.

Thanks
Tiejun

Quoted 13 lines

Also change rid to uint8_t, you won't need to cast then.

Quoted 8 lines
hw/xen/xen_pt_graphics.c +6 -1
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}
--

1.9.1

#12 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 124 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun Chen

ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0 to make graphics device passthrough work well for VMM, that only need to expose this pseudo ISA bridge to let driver know the real hardware underneath.

The original patch is from Allen Kay <[email protected]>

---
v5:

* Don't set this ISA class property, instead, just fake this ISA bridge with 00:1f.0.

v4:

* Remove some unnecessary "return" in void foo().

v3:

* Fix some typos.
* Improve some return paths.

v2:

* Nothing is changed.

 hw/xen/xen_pt_graphics.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
hw/xen/xen_pt_graphics.c +14 -0
index 461e526..974b7e9 100644
@@ -230,3 +230,64 @@ out:
     g_free(bios);
     return rc;
 }
+
+static uint32_t isa_bridge_read_config(PCIDevice *d, uint32_t addr, int len)
+{
+    return pci_default_read_config(d, addr, len);
+}
+
+static void isa_bridge_write_config(PCIDevice *d, uint32_t addr, uint32_t v,
+                                    int len)
+{
+    pci_default_write_config(d, addr, v, len);
+}
+
+static void isa_bridge_class_init(ObjectClass *klass, void *data)
+{
Quoted 8 lines

hw/xen/xen_pt_graphics.c out: · line 251

Quoted 5 lines
hw/xen/xen_pt_graphics.c +5 -0
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_read = isa_bridge_read_config;
+    k->config_write = isa_bridge_write_config;
+};

You don't need these stubs, just don't fill anything, pci core will use defaults then.

I guess these stubs are left to extend something in the future. But maybe we can remove them now.

Quoted 37 lines

hw/xen/xen_pt_graphics.c out: · line 256

Quoted 6 lines
hw/xen/xen_pt_graphics.c +5 -0
+
+typedef struct {
+    PCIDevice dev;
+} ISABridgeState;
+

Nor do you need an empty structure if it has no state.

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+static TypeInfo isa_bridge_info = {
+    .name          = "pseudo-intel-pch-isa-bridge",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(ISABridgeState),
+    .class_init = isa_bridge_class_init,
+};
+
+static void xen_pt_graphics_register_types(void)
+{
+    type_register_static(&isa_bridge_info);
+}
+
+type_init(xen_pt_graphics_register_types)

hw/xen/xen_pt_graphics.c out: · line 279

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */

A typo and confusing wording above, I'm not really sure what this comment means.
Maybe:

Quoted 2 lines

/* Create a fake ISA bridge device at the location expected by guests. */

Good comments so thanks so much.

Quoted 11 lines

hw/xen/xen_pt_graphics.c out: · line 287

Quoted 9 lines
hw/xen/xen_pt_graphics.c +8 -0
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+    qdev_init_nofail(&dev->qdev);
+
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);

Host PCI device is the VGA card?

This is a real ISA bridge.

Quoted 8 lines
Quoted 2 lines

So why does it make sense to get it's vendor/device/revision and stick in the ISA bridge?

The Intel generation of integrated graphics needs to probe this ISA bridge to initialize the i915 driver properly.

Thanks
Tiejun

So vendor/device/revision IDs must match real device then? Stick this in the comment then.

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 13 lines
Quoted 13 lines

Also change rid to uint8_t, you won't need to cast then.

Quoted 8 lines
hw/xen/xen_pt_graphics.c +6 -1
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}
--

1.9.1

#13 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 128 lines · Michael S. Tsirkin
Quoted 127 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun Chen

ISA bridge is needed since Intel gfx drive will probe with Dev31:Fun0 to make graphics device passthrough work well for VMM, that only need to expose this pseudo ISA bridge to let driver know the real hardware underneath.

The original patch is from Allen Kay <[email protected]>

---
v5:

* Don't set this ISA class property, instead, just fake this ISA bridge with 00:1f.0.

v4:

* Remove some unnecessary "return" in void foo().

v3:

* Fix some typos.
* Improve some return paths.

v2:

* Nothing is changed.

  hw/xen/xen_pt_graphics.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++
  1 file changed, 61 insertions(+)
hw/xen/xen_pt_graphics.c +14 -0
index 461e526..974b7e9 100644
@@ -230,3 +230,64 @@ out:
      g_free(bios);
      return rc;
  }
+
+static uint32_t isa_bridge_read_config(PCIDevice *d, uint32_t addr, int len)
+{
+    return pci_default_read_config(d, addr, len);
+}
+
+static void isa_bridge_write_config(PCIDevice *d, uint32_t addr, uint32_t v,
+                                    int len)
+{
+    pci_default_write_config(d, addr, v, len);
+}
+
+static void isa_bridge_class_init(ObjectClass *klass, void *data)
+{
Quoted 8 lines

hw/xen/xen_pt_graphics.c out: · line 251

Quoted 5 lines
hw/xen/xen_pt_graphics.c +5 -0
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->config_read = isa_bridge_read_config;
+    k->config_write = isa_bridge_write_config;
+};

You don't need these stubs, just don't fill anything, pci core will use defaults then.

I guess these stubs are left to extend something in the future. But maybe we can remove them now.

Quoted 37 lines

hw/xen/xen_pt_graphics.c out: · line 256

Quoted 6 lines
hw/xen/xen_pt_graphics.c +5 -0
+
+typedef struct {
+    PCIDevice dev;
+} ISABridgeState;
+

Nor do you need an empty structure if it has no state.

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+static TypeInfo isa_bridge_info = {
+    .name          = "pseudo-intel-pch-isa-bridge",
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(ISABridgeState),
+    .class_init = isa_bridge_class_init,
+};
+
+static void xen_pt_graphics_register_types(void)
+{
+    type_register_static(&isa_bridge_info);
+}
+
+type_init(xen_pt_graphics_register_types)

hw/xen/xen_pt_graphics.c out: · line 279

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */

A typo and confusing wording above, I'm not really sure what this comment means.
Maybe:

Quoted 2 lines

/* Create a fake ISA bridge device at the location expected by guests. */

Good comments so thanks so much.

Quoted 11 lines

hw/xen/xen_pt_graphics.c out: · line 287

Quoted 9 lines
hw/xen/xen_pt_graphics.c +8 -0
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+    qdev_init_nofail(&dev->qdev);
+
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);

Host PCI device is the VGA card?

This is a real ISA bridge.

Quoted 2 lines

So why does it make sense to get it's vendor/device/revision and stick in the ISA bridge?

Quoted 7 lines
Quoted 5 lines

The Intel generation of integrated graphics needs to probe this ISA bridge to initialize the i915 driver properly.

Thanks
Tiejun

So vendor/device/revision IDs must match real device then?

Yes, the i915 driver needs these information of PCH to determine how to work. And this is just why we expose this ISA bridge to guest ugly :(

Quoted 2 lines

Stick this in the comment then.

Sure.

Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Yes, sysfs.

Thanks
Tiejun

Quoted 19 lines
Quoted 16 lines
Quoted 16 lines

Also change rid to uint8_t, you won't need to cast then.

Quoted 8 lines
hw/xen/xen_pt_graphics.c +6 -1
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}
--

1.9.1

#14 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 8 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

#15 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Thanks
Tiejun

Quoted 4 lines
#16 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 15 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Quoted 5 lines

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Quoted 4 lines
Quoted 4 lines
#17 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 19 lines · Michael S. Tsirkin
Quoted 18 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)

	|
	+ xen_host_pci_config_read(d, pos, buf, len)
		|
		+ pread(d->config_fd, buf, len, pos)

I thinks this should be same as kvm.

Thanks
Tiejun

#18 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 37 lines · Tiejun
Quoted 19 lines · Michael S. Tsirkin
Quoted 18 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)

	|
	+ xen_host_pci_config_read(d, pos, buf, len)
		|
		+ pread(d->config_fd, buf, len, pos)
Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Signature · 1 line
MST
#19 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 45 lines · Michael S. Tsirkin
Quoted 37 lines · Tiejun
Quoted 19 lines · Michael S. Tsirkin
Quoted 18 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)

	|
	+ xen_host_pci_config_read(d, pos, buf, len)
		|
		+ pread(d->config_fd, buf, len, pos)
Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen inside qemu. But I'm afraid its not easy to do in a short time, so maybe we can queue this as next phase.

Thanks
Tiejun

#20 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 56 lines · Tiejun
Quoted 45 lines · Michael S. Tsirkin
Quoted 37 lines · Tiejun
Quoted 19 lines · Michael S. Tsirkin
Quoted 18 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)

	|
	+ xen_host_pci_config_read(d, pos, buf, len)
		|
		+ pread(d->config_fd, buf, len, pos)
Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Quoted 6 lines

Looks you mean we can unify the entire PT infrastructure between kvm and xen inside qemu. But I'm afraid its not easy to do in a short time, so maybe we can queue this as next phase.

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

At least, don't add duplicate code for ROM.

Signature · 1 line
MST
#21 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 57 lines · Michael S. Tsirkin
Quoted 56 lines · Tiejun
Quoted 54 lines · Michael S. Tsirkin
Quoted 37 lines · Tiejun
Quoted 19 lines · Michael S. Tsirkin
Quoted 18 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)

	|
	+ xen_host_pci_config_read(d, pos, buf, len)
		|
		+ pread(d->config_fd, buf, len, pos)
Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Quoted 9 lines
Quoted 6 lines

Looks you mean we can unify the entire PT infrastructure between kvm and xen inside qemu. But I'm afraid its not easy to do in a short time, so maybe we can queue this as next phase.

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Thanks
Tiejun

#22 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

Thanks
Tiejun

#23 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 97 lines · Tiejun
Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

Quoted 6 lines

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

The Xen PT code came first. At the time Anthony Liguori and I argued for sharing the PT code with KVM going forward but Avi wanted to retain the KVM PT code as is in order not to introduce any regressions on KVM.

Ah.. the good old times :-)

http://lists.xen.org/archives/html/xen-devel/2011-10/msg00195.html

#24 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 102 lines · Stefano Stabellini
Quoted 101 lines · Tiejun
Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Quoted 8 lines
Quoted 2 lines

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

The Xen PT code came first. At the time Anthony Liguori and I argued for sharing the PT code with KVM going forward but Avi wanted to retain the KVM PT code as is in order not to introduce any regressions on KVM.

Ah.. the good old times :-)

Thanks for your information. So now what's next I should do now?

Thanks
Tiejun

Quoted 4 lines

http://lists.xen.org/archives/html/xen-devel/2011-10/msg00195.html

#25 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

In reply to Stefano Stabellini
Quoted 105 lines · Stefano Stabellini
Quoted 97 lines · Tiejun
Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

Quoted 6 lines

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

Quoted 7 lines

The Xen PT code came first. At the time Anthony Liguori and I argued for sharing the PT code with KVM going forward but Avi wanted to retain the KVM PT code as is in order not to introduce any regressions on KVM.

Ah.. the good old times :-)

http://lists.xen.org/archives/html/xen-devel/2011-10/msg00195.html

Right, I remember that there was an idea to first make the code reusable before merging either Xen or KVM PT, but in the end the plan to merge both and then abstract it out, won. We never got to abstracting it out but we should!

Yet, I do not think we should require abstracting all of Xen PT as a pre-requisite for this work, but I think we can
avoid adding to the duplication without a lot of effort. To start sharing with ROM code, I think we should rename AssignedDevice->KvmAssignedDevice, and move fields that can be shared with Xen from there to AssignedDevice.

Signature · 1 line
MST
#26 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 119 lines · Michael S. Tsirkin
Quoted 105 lines · Stefano Stabellini
Quoted 97 lines · Tiejun
Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c
can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

Quoted 6 lines

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

Quoted 7 lines

The Xen PT code came first. At the time Anthony Liguori and I argued for sharing the PT code with KVM going forward but Avi wanted to retain the KVM PT code as is in order not to introduce any regressions on KVM.

Ah.. the good old times :-)

http://lists.xen.org/archives/html/xen-devel/2011-10/msg00195.html

Right, I remember that there was an idea to first make the code reusable before merging either Xen or KVM PT, but in the end the plan to merge both and then abstract it out, won. We never got to abstracting it out but we should!

Quoted 6 lines

Yet, I do not think we should require abstracting all of Xen PT as a pre-requisite for this work, but I think we can
avoid adding to the duplication without a lot of effort. To start sharing with ROM code, I think we should rename AssignedDevice->KvmAssignedDevice, and move fields that can be shared with Xen from there to AssignedDevice.

Its not simple to share something between AssignedDevice and the similar structure, XenHostPCIDevice.

As I said previously AssignedDevice is just activated in kvm_enabled(), then set all properties to this structure.

But kvm_enabled() is zero since we always disable this in xen scenario. So this means we have to invoke pci-assign framework completely if we try to force to use this. So actually this would be equal to merge kvm and xen.

Or if you already figure out to avoid this happened let me know.

Thanks
Tiejun

#27 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

Quoted 133 lines · Tiejun
Quoted 119 lines · Michael S. Tsirkin
Quoted 105 lines · Stefano Stabellini
Quoted 97 lines · Tiejun
Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c
can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

Quoted 6 lines

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

Quoted 7 lines

The Xen PT code came first. At the time Anthony Liguori and I argued for sharing the PT code with KVM going forward but Avi wanted to retain the KVM PT code as is in order not to introduce any regressions on KVM.

Ah.. the good old times :-)

http://lists.xen.org/archives/html/xen-devel/2011-10/msg00195.html

Right, I remember that there was an idea to first make the code reusable before merging either Xen or KVM PT, but in the end the plan to merge both and then abstract it out, won. We never got to abstracting it out but we should!

Quoted 6 lines

Yet, I do not think we should require abstracting all of Xen PT as a pre-requisite for this work, but I think we can
avoid adding to the duplication without a lot of effort. To start sharing with ROM code, I think we should rename AssignedDevice->KvmAssignedDevice, and move fields that can be shared with Xen from there to AssignedDevice.

Its not simple to share something between AssignedDevice and the similar structure, XenHostPCIDevice.

As I said previously AssignedDevice is just activated in kvm_enabled(), then set all properties to this structure.

Quoted 8 lines

But kvm_enabled() is zero since we always disable this in xen scenario. So this means we have to invoke pci-assign framework completely if we try to force to use this. So actually this would be equal to merge kvm and xen.

Or if you already figure out to avoid this happened let me know.

Thanks
Tiejun

For now fill in the structure separately in xen.

Signature · 1 line
MST
#28 lore raw

Re: [Qemu-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge

In reply to Michael S. Tsirkin
Quoted 110 lines · Michael S. Tsirkin
Quoted 109 lines · Stefano Stabellini
Quoted 97 lines · Tiejun
Quoted 77 lines · Tiejun
Quoted 66 lines · Michael S. Tsirkin
Quoted 65 lines · Tiejun
Quoted 48 lines · Michael S. Tsirkin
Quoted 40 lines · Tiejun
Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 5 lines · Michael S. Tsirkin
Quoted 4 lines · Tiejun
Quoted 3 lines

In fact it's exactly what passthrough does.
I wonder if more bits from ./hw/i386/kvm/pci-assign.c
can be reused. How do you poke at the host device? sysfs?

Quoted 8 lines
Quoted 4 lines

Yes, sysfs.

Thanks
Tiejun

Then you should be able to re-use large chunks of
./hw/i386/kvm/pci-assign.c: basically everything
that deals with emulation.

Do you mean those hooks to get info from the real device? Xen have its own
wrapper, xen_host_pci_get_block(), so we always go there in xen scenario.

Quoted 8 lines
Quoted 2 lines

Thanks
Tiejun

Yes and that's not good. We have two pieces of code doing mostly identical things slightly differently. hw/i386/kvm/pci-assign.c is a bit younger so it's cleaner, but these really need to be unified.

Sorry, take a look at this again,

xen_host_pci_get_block(XenHostPCIDevice *d, int pos, uint8_t *buf, int len)
|
+ xen_host_pci_config_read(d, pos, buf, len)
|
+ pread(d->config_fd, buf, len, pos)

Quoted 4 lines

I thinks this should be same as kvm.

Thanks
Tiejun

get_block is trivial.

Quoted 9 lines

I really mean the whole PT infrastructure for
- discovering host devices through sysfs
- virtualizing devices

rom, bars, msi ...
the list goes on.

logic is mostly the same.

Looks you mean we can unify the entire PT infrastructure between kvm and xen
inside qemu. But I'm afraid its not easy to do in a short time, so maybe we
can queue this as next phase.

Quoted 5 lines
Quoted 2 lines

Thanks
Tiejun

I'm afraid once we merge your code, you'll lose interest :)

Currently we have to push this feature into upstream as our first priority, so unless something is really needed to address. Of course I hope this point what we're talking is not such a thing :)

Quoted 8 lines

But I can promise here I'd like to do this optimization with your guide next :)

Quoted 2 lines

At least, don't add duplicate code for ROM.

Let me try this.

Its not easy as expected.

kvm always work with this structure, AssignedDevice, and especially this is just activated in kvm_enabled(). And then set all properties to this structure.

In xen case, the similar structure, XenHostPCIDevice, is not easy transferred into the structure, AssignedDevice. So this mean we have to split assigned_dev_load_option_rom() as line by line for xen and kvm, respectively.

Quoted 6 lines

I really agree we definitely need to unify PT infrastructure between kvm and xen after this try since I can't understand why we originally introduce same way to do same thing :(

Do you have better idea? If not, I prefer we open this completely as next action to follow-up. But this time I'm afraid I can't get in this.

The Xen PT code came first. At the time Anthony Liguori and I argued for sharing the PT code with KVM going forward but Avi wanted to retain the KVM PT code as is in order not to introduce any regressions on KVM.

Quoted 8 lines
Quoted 3 lines

Ah.. the good old times :-)

http://lists.xen.org/archives/html/xen-devel/2011-10/msg00195.html

Right, I remember that there was an idea to first make the code reusable before merging either Xen or KVM PT, but in the end the plan to merge both and then abstract it out, won. We never got to abstracting it out but we should!

I agree

Quoted 3 lines

Yet, I do not think we should require abstracting all of Xen PT as a pre-requisite for this work, but I think we can
avoid adding to the duplication without a lot of effort.

It seems like a good idea

Quoted 7 lines

To start sharing with ROM code, I think we should rename AssignedDevice->KvmAssignedDevice, and move fields that can be shared with Xen from there to AssignedDevice.

Signature · 1 line
MST
#29 lore raw

PATCH v5 3/5 xen, gfx passthrough: support Intel IGD passthrough with VT-D

In reply to Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to passthrough these registers of physical host bridge to guest because emulated host bridge in guest doesn't have these mappings.

The original patch is from Weidong Han <[email protected]>

---
v5:

* Don't pass vendor/device ids in igd_pci_read().
* Add to support offset 0x44/0x48.

v4:

* Given that pci_create_pch() is called unconditionally, so we just return 0 even if its failed to check xen_has_gfx_passthru.
* Remove one spurious change.

v3:

* Improve comments to make that readable.

v2:

* To introduce is_igd_passthrough() to make sure we touch physical host bridge only in IGD case.

 hw/xen/xen_pt.h          |   4 ++
 hw/xen/xen_pt_graphics.c | 156 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 160 insertions(+)
hw/xen/xen_pt.h +4 -0
index 4d3a18d..507165c 100644
@@ -302,5 +302,9 @@ extern int xen_has_gfx_passthru;
 int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
 int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
 int xen_pt_setup_vga(XenHostPCIDevice *dev);
+int pci_create_pch(PCIBus *bus);
+void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
+                   uint32_t val, int len);
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c +156 -0

165 lines not on this page · raw message

Signature · 1 line
1.9.1
#30 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 304

Quoted 9 lines
hw/xen/xen_pt_graphics.c +9 -0
+int pci_create_pch(PCIBus *bus)
+{
+    XenHostPCIDevice hdev;
+    int r = 0;
+
+    if (!xen_has_gfx_passthru) {
+        return r;
+    }
+

You could make this an assertion, since the function is never called with xen_has_gfx_passthru == 0. Or just drop the check completely, so the function can be moved in patch 2.

Paolo

#31 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

Quoted 13 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 304

Quoted 9 lines
hw/xen/xen_pt_graphics.c +9 -0
+int pci_create_pch(PCIBus *bus)
+{
+    XenHostPCIDevice hdev;
+    int r = 0;
+
+    if (!xen_has_gfx_passthru) {
+        return r;
+    }
+

You could make this an assertion, since the function is never called with xen_has_gfx_passthru == 0. Or just drop the check completely, so

I will drop this completely.

Thanks
Tiejun

Quoted 5 lines

the function can be moved in patch 2.

Paolo

#32 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

In reply to Tiejun Chen
Quoted 61 lines · Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to passthrough these registers of physical host bridge to guest because emulated host bridge in guest doesn't have these mappings.

The original patch is from Weidong Han <[email protected]>

---
v5:

* Don't pass vendor/device ids in igd_pci_read().
* Add to support offset 0x44/0x48.

v4:

* Given that pci_create_pch() is called unconditionally, so we just return 0 even if its failed to check xen_has_gfx_passthru.
* Remove one spurious change.

v3:

* Improve comments to make that readable.

v2:

* To introduce is_igd_passthrough() to make sure we touch physical host bridge only in IGD case.

 hw/xen/xen_pt.h          |   4 ++
 hw/xen/xen_pt_graphics.c | 156 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 160 insertions(+)
hw/xen/xen_pt.h +4 -0
index 4d3a18d..507165c 100644
@@ -302,5 +302,9 @@ extern int xen_has_gfx_passthru;
 int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
 int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
 int xen_pt_setup_vga(XenHostPCIDevice *dev);
+int pci_create_pch(PCIBus *bus);
+void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
+                   uint32_t val, int len);
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c +1 -0
index 974b7e9..f3fbfed 100644
@@ -4,6 +4,7 @@
 #include "xen_pt.h"
 #include "xen-host-pci-device.h"
 #include "hw/xen/xen_backend.h"
+#include "hw/pci/pci_bus.h"
 
 static int is_vga_passthrough(XenHostPCIDevice *dev)
 {

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 296

Quoted 5 lines
hw/xen/xen_pt_graphics.c +2 -0
@@ -291,3 +292,158 @@ static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
     XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
     return 0;
 }
+
+int pci_create_pch(PCIBus *bus)

Please prefix all xen specific non static functions with xen_ or something like this.
pci_ is for pci core.

In fact it's a good idea to do this for static functions as well, in case we add a conflicting function in some header.

Quoted 11 lines
hw/xen/xen_pt_graphics.c +11 -0
+{
+    XenHostPCIDevice hdev;
+    int r = 0;
+
+    if (!xen_has_gfx_passthru) {
+        return r;
+    }
+
+    r = xen_host_pci_device_get(&hdev, 0, 0, 0x1f, 0);
+    if (r) {
+        XEN_PT_ERR(NULL, "Failed to find Intel PCH on host\n");

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 317

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+        goto err;
+    }
+
+    if (hdev.vendor_id == PCI_VENDOR_ID_INTEL) {
+        r = create_pseudo_pch_isa_bridge(bus, &hdev);
+        if (r) {
+            XEN_PT_ERR(NULL, "Failed to create PCH ISA bridge.\n");
+            goto err;
+        }
+    }

Does it work on non intel?
It seems to return success.
Maybe you should just verify that vendor and device ID have the expected values on the host, and fail otherwise.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 330

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+
+    xen_host_pci_device_put(&hdev);
+
+err:
+    return r;
+}
+
+/*
+ * Currently we just pass this physical host bridge for IGD, 00:02.0.
+ *
+ * Here pci_dev is just that host bridge, so we have to get that real
+ * passthrough device by that given devfn to further confirm.
+ */

confirm what?
Comments like this need to document what function does.

Maybe

/* Can we support IGD passthrough for this device?
* We require ... <XYZ - fill in here>
*/

Quoted 4 lines
hw/xen/xen_pt_graphics.c +4 -0
+static int is_igd_passthrough(PCIDevice *pci_dev)
+{
+    PCIDevice *f = pci_dev->bus->devices[PCI_DEVFN(2, 0)];
+    if (pci_dev->bus->devices[PCI_DEVFN(2, 0)]) {

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 344

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+        XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, f);
+        return (is_vga_passthrough(&s->real_device)
+                    && (s->real_device.vendor_id == PCI_VENDOR_ID_INTEL));
+    } else {
+        return 0;
+    }
+}
+
+void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
+                   uint32_t val, int len)

Same here, xen_ everywhere please.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 352

Quoted 8 lines
hw/xen/xen_pt_graphics.c +8 -0
+{
+    XenHostPCIDevice dev;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().

You mean in linux kernel I guess?

Quoted 19 lines
hw/xen/xen_pt_graphics.c +19 -0
+     */
+
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto write_default;
+    }
+
+    /* Just work for the i915 driver. */
+    switch (config_addr) {
+    case 0x58:      /* PAVPC Offset */
+        break;
+    default:
+        /* Just sets the emulated values. */
+        goto write_default;
+    }
+
+    /* Host write */
+    r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 381

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+    if (r) {
+        XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+        abort();
+    }
+
+    r = xen_host_pci_set_block(&dev, config_addr, (uint8_t *)&val, len);
+    if (r) {
+        XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+        abort();
+    }

Cleaner:

	if (config_addr == 0x58) {
	     /* Host write */
	     r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);
	     if (r) {
	         XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
	         abort();
	     }
	 
	     r = xen_host_pci_set_block(&dev, config_addr, (uint8_t *)&val, len);
	     if (r) {
	         XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
	         abort();
	     }
	}

Note this does not work on e.g. BE.
The best way is really to make the register writeable in wmask. Then

    pci_default_write_config(pci_dev, config_addr, val, len);
    if (range_covers_byte(addr, len, 0x58)) {
		....

	     r = xen_host_pci_set_block(&dev, config_addr,
		 pci_dev->config + config_addr, len);
    }
Quoted 21 lines
hw/xen/xen_pt_graphics.c +21 -0
+
+    xen_host_pci_device_put(&dev);
+
+    return;
+
+write_default:
+    pci_default_write_config(pci_dev, config_addr, val, len);
+}
+
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len)
+{
+    XenHostPCIDevice dev;
+    uint32_t val;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+    assert(pci_dev->devfn == 0x00);

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 412

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto read_default;
+    }
+
+    /* Just work for the i915 driver. */
+    switch (config_addr) {
+    case 0x08:        /* revision id */
+    case 0x2c:        /* sybsystem vendor id */
+    case 0x2e:        /* sybsystem id */

Since you set them to match host previously,
should be no need to override now.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 421

Quoted 9 lines
hw/xen/xen_pt_graphics.c +9 -0
+    case 0x44:        /* MCHBAR I915 */
+    case 0x48:        /* MCHBAR I965 */
+    case 0x50:        /* SNB: processor graphics control register */
+    case 0x52:        /* processor graphics control register */
+    case 0xa0:        /* top of memory */
+    case 0xb0:        /* ILK: BSM: should read from dev 2 offset 0x5c */
+    case 0x58:        /* SNB: PAVPC Offset */
+    case 0xa4:        /* SNB: graphics base of stolen memory */
+    case 0xa8:        /* SNB: base of GTT stolen memory */

Move the actual code here.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 424

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+        break;
+    default:
+        /* Just gets the emulated values. */

and here.

Quoted 27 lines
hw/xen/xen_pt_graphics.c +25 -0
+        goto read_default;
+    }
+
+    /* Host read */
+    r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);
+    if (r) {
+        goto err_out;
+    }
+
+    r = xen_host_pci_get_block(&dev, config_addr, (uint8_t *)&val, len);
+    if (r) {
+        goto err_out;
+    }
+
+    xen_host_pci_device_put(&dev);
+
+    return val;
+
+read_default:
+    return pci_default_read_config(pci_dev, config_addr, len);
+
+err_out:
+    XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+    return -1;
+}
Signature · 1 line
1.9.1
#33 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

Quoted 2 lines · Michael S. Tsirkin
Quoted 1 line · Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to

[snip]

Quoted 4 lines
Quoted 4 lines
  static int is_vga_passthrough(XenHostPCIDevice *dev)
  {
hw/xen/xen_pt_graphics.c +0 -0
@@ -291,3 +292,158 @@ static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
      XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
Quoted 8 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 296

Quoted 4 lines
hw/xen/xen_pt_graphics.c +2 -0
      return 0;
  }
+
+int pci_create_pch(PCIBus *bus)

Please prefix all xen specific non static functions with xen_ or something like this.

Okay.

Quoted 21 lines

pci_ is for pci core.

In fact it's a good idea to do this for static functions as well, in case we add a conflicting function in some header.

Quoted 15 lines
hw/xen/xen_pt_graphics.c +15 -0
+{
+    XenHostPCIDevice hdev;
+    int r = 0;
+
+    if (!xen_has_gfx_passthru) {
+        return r;
+    }
+
+    r = xen_host_pci_device_get(&hdev, 0, 0, 0x1f, 0);
+    if (r) {
+        XEN_PT_ERR(NULL, "Failed to find Intel PCH on host\n");
+        goto err;
+    }
+
+    if (hdev.vendor_id == PCI_VENDOR_ID_INTEL) {
Quoted 8 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 317

Quoted 6 lines
hw/xen/xen_pt_graphics.c +6 -0
+        r = create_pseudo_pch_isa_bridge(bus, &hdev);
+        if (r) {
+            XEN_PT_ERR(NULL, "Failed to create PCH ISA bridge.\n");
+            goto err;
+        }
+    }

Does it work on non intel?

IGD means this should work on Intel platform.

Quoted 1 line

It seems to return success.

Okay, I'd like to change this a void.

Quoted 2 lines

Maybe you should just verify that vendor and device ID have the expected values on the host, and

Vendor id is enough.

Quoted 18 lines

fail otherwise.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 330

Quoted 13 lines
hw/xen/xen_pt_graphics.c +13 -0
+
+    xen_host_pci_device_put(&hdev);
+
+err:
+    return r;
+}
+
+/*
+ * Currently we just pass this physical host bridge for IGD, 00:02.0.
+ *
+ * Here pci_dev is just that host bridge, so we have to get that real
+ * passthrough device by that given devfn to further confirm.
+ */

confirm what?

So change like:

* passthrough device by that given devfn to avoid other devices access.

Quoted 8 lines

Comments like this need to document what function does.

Maybe

/* Can we support IGD passthrough for this device?
* We require ... <XYZ - fill in here>
*/

Quoted 16 lines
Quoted 4 lines
hw/xen/xen_pt_graphics.c +4 -0
+static int is_igd_passthrough(PCIDevice *pci_dev)
+{
+    PCIDevice *f = pci_dev->bus->devices[PCI_DEVFN(2, 0)];
+    if (pci_dev->bus->devices[PCI_DEVFN(2, 0)]) {

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 344

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+        XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, f);
+        return (is_vga_passthrough(&s->real_device)
+                    && (s->real_device.vendor_id == PCI_VENDOR_ID_INTEL));
+    } else {
+        return 0;
+    }
+}
+
+void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
+                   uint32_t val, int len)

Same here, xen_ everywhere please.

Okay.

Quoted 11 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 352

Quoted 9 lines
hw/xen/xen_pt_graphics.c +8 -0
+{
+    XenHostPCIDevice dev;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().

You mean in linux kernel I guess?

So change like,

* probe ISA bridge to discover the IGD, see comment in Linux:i915_drv.c:

Quoted 34 lines
Quoted 20 lines
hw/xen/xen_pt_graphics.c +19 -0
+     */
+
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto write_default;
+    }
+
+    /* Just work for the i915 driver. */
+    switch (config_addr) {
+    case 0x58:      /* PAVPC Offset */
+        break;
+    default:
+        /* Just sets the emulated values. */
+        goto write_default;
+    }
+
+    /* Host write */
+    r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 381

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+    if (r) {
+        XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+        abort();
+    }
+
+    r = xen_host_pci_set_block(&dev, config_addr, (uint8_t *)&val, len);
+    if (r) {
+        XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+        abort();
+    }

Cleaner:

Quoted 1 line
	if (config_addr == 0x58) {

Maybe we add other offset in the future, so we'd better keep in them in switch().

Quoted 14 lines
	     /* Host write */
	     r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);
	     if (r) {
	         XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
	         abort();
	     }
	
	     r = xen_host_pci_set_block(&dev, config_addr, (uint8_t *)&val, len);
	     if (r) {
	         XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
	         abort();
	     }
	}
Quoted 1 line

Note this does not work on e.g. BE.

Why do we need take BE into consideration here? Shouldn't PCI already be LE?

Quoted 40 lines

The best way is really to make the register writeable in wmask. Then

     pci_default_write_config(pci_dev, config_addr, val, len);
     if (range_covers_byte(addr, len, 0x58)) {
		....

	     r = xen_host_pci_set_block(&dev, config_addr,
		 pci_dev->config + config_addr, len);
     }
Quoted 26 lines
hw/xen/xen_pt_graphics.c +26 -0
+
+    xen_host_pci_device_put(&dev);
+
+    return;
+
+write_default:
+    pci_default_write_config(pci_dev, config_addr, val, len);
+}
+
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len)
+{
+    XenHostPCIDevice dev;
+    uint32_t val;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto read_default;
+    }
+
Quoted 8 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 412

Quoted 5 lines
hw/xen/xen_pt_graphics.c +5 -0
+    /* Just work for the i915 driver. */
+    switch (config_addr) {
+    case 0x08:        /* revision id */
+    case 0x2c:        /* sybsystem vendor id */
+    case 0x2e:        /* sybsystem id */

Since you set them to match host previously, should be no need to override now.

Just *read* the host bridge, no *write* here.

Quoted 11 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 421

Quoted 10 lines
hw/xen/xen_pt_graphics.c +9 -0
+    case 0x44:        /* MCHBAR I915 */
+    case 0x48:        /* MCHBAR I965 */
+    case 0x50:        /* SNB: processor graphics control register */
+    case 0x52:        /* processor graphics control register */
+    case 0xa0:        /* top of memory */
+    case 0xb0:        /* ILK: BSM: should read from dev 2 offset 0x5c */
+    case 0x58:        /* SNB: PAVPC Offset */
+    case 0xa4:        /* SNB: graphics base of stolen memory */
+    case 0xa8:        /* SNB: base of GTT stolen memory */
Quoted 2 lines

Move the actual code here.

Sorry, whats the actual code? Are you saying we can read all values from the host bridge in advance then restore them here?

Thanks
Tiejun

Quoted 35 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 424

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+        break;
+    default:
+        /* Just gets the emulated values. */

and here.

Quoted 27 lines
hw/xen/xen_pt_graphics.c +25 -1
+        goto read_default;
+    }
+
+    /* Host read */
+    r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);
+    if (r) {
+        goto err_out;
+    }
+
+    r = xen_host_pci_get_block(&dev, config_addr, (uint8_t *)&val, len);
+    if (r) {
+        goto err_out;
+    }
+
+    xen_host_pci_device_put(&dev);
+
+    return val;
+
+read_default:
+    return pci_default_read_config(pci_dev, config_addr, len);
+
+err_out:
+    XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+    return -1;
+}
--

1.9.1

#34 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

In reply to Tiejun Chen
Quoted 174 lines · Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to passthrough these registers of physical host bridge to guest because emulated host bridge in guest doesn't have these mappings.

The original patch is from Weidong Han <[email protected]>

---
v5:

* Don't pass vendor/device ids in igd_pci_read().
* Add to support offset 0x44/0x48.

v4:

* Given that pci_create_pch() is called unconditionally, so we just return 0 even if its failed to check xen_has_gfx_passthru.
* Remove one spurious change.

v3:

* Improve comments to make that readable.

v2:

* To introduce is_igd_passthrough() to make sure we touch physical host bridge only in IGD case.

 hw/xen/xen_pt.h          |   4 ++
 hw/xen/xen_pt_graphics.c | 156 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 160 insertions(+)
hw/xen/xen_pt.h +4 -0
index 4d3a18d..507165c 100644
@@ -302,5 +302,9 @@ extern int xen_has_gfx_passthru;
 int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
 int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
 int xen_pt_setup_vga(XenHostPCIDevice *dev);
+int pci_create_pch(PCIBus *bus);
+void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
+                   uint32_t val, int len);
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_graphics.c +111 -0
index 974b7e9..f3fbfed 100644
@@ -4,6 +4,7 @@
 #include "xen_pt.h"
 #include "xen-host-pci-device.h"
 #include "hw/xen/xen_backend.h"
+#include "hw/pci/pci_bus.h"
 
 static int is_vga_passthrough(XenHostPCIDevice *dev)
 {
@@ -291,3 +292,158 @@ static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
     XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
     return 0;
 }
+
+int pci_create_pch(PCIBus *bus)
+{
+    XenHostPCIDevice hdev;
+    int r = 0;
+
+    if (!xen_has_gfx_passthru) {
+        return r;
+    }
+
+    r = xen_host_pci_device_get(&hdev, 0, 0, 0x1f, 0);
+    if (r) {
+        XEN_PT_ERR(NULL, "Failed to find Intel PCH on host\n");
+        goto err;
+    }
+
+    if (hdev.vendor_id == PCI_VENDOR_ID_INTEL) {
+        r = create_pseudo_pch_isa_bridge(bus, &hdev);
+        if (r) {
+            XEN_PT_ERR(NULL, "Failed to create PCH ISA bridge.\n");
+            goto err;
+        }
+    }
+
+    xen_host_pci_device_put(&hdev);
+
+err:
+    return r;
+}
+
+/*
+ * Currently we just pass this physical host bridge for IGD, 00:02.0.
+ *
+ * Here pci_dev is just that host bridge, so we have to get that real
+ * passthrough device by that given devfn to further confirm.
+ */
+static int is_igd_passthrough(PCIDevice *pci_dev)
+{
+    PCIDevice *f = pci_dev->bus->devices[PCI_DEVFN(2, 0)];
+    if (pci_dev->bus->devices[PCI_DEVFN(2, 0)]) {
+        XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, f);
+        return (is_vga_passthrough(&s->real_device)
+                    && (s->real_device.vendor_id == PCI_VENDOR_ID_INTEL));
+    } else {
+        return 0;
+    }
+}
+
+void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
+                   uint32_t val, int len)
+{
+    XenHostPCIDevice dev;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto write_default;
+    }
+
+    /* Just work for the i915 driver. */
+    switch (config_addr) {
+    case 0x58:      /* PAVPC Offset */
+        break;
+    default:
+        /* Just sets the emulated values. */
+        goto write_default;
+    }
+
+    /* Host write */
+    r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);
+    if (r) {
+        XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+        abort();
+    }
+
+    r = xen_host_pci_set_block(&dev, config_addr, (uint8_t *)&val, len);
+    if (r) {
+        XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+        abort();
+    }
+
+    xen_host_pci_device_put(&dev);
+
+    return;
+
+write_default:
+    pci_default_write_config(pci_dev, config_addr, val, len);
+}
+
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len)
+{
+    XenHostPCIDevice dev;
+    uint32_t val;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 414

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+        goto read_default;
+    }
+
+    /* Just work for the i915 driver. */
+    switch (config_addr) {
+    case 0x08:        /* revision id */
+    case 0x2c:        /* sybsystem vendor id */
+    case 0x2e:        /* sybsystem id */
+    case 0x44:        /* MCHBAR I915 */
+    case 0x48:        /* MCHBAR I965 */

In fact, this is returning host addresses to guest, right? Don't see how this can work except by luck.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 417

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0x50:        /* SNB: processor graphics control register */
+    case 0x52:        /* processor graphics control register */
+    case 0xa0:        /* top of memory */

which memory? Could be similar.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 420

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0xb0:        /* ILK: BSM: should read from dev 2 offset 0x5c */
+    case 0x58:        /* SNB: PAVPC Offset */
+    case 0xa4:        /* SNB: graphics base of stolen memory */

Same thing.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 421

Quoted 1 line
hw/xen/xen_pt_graphics.c +1 -0
+    case 0xa8:        /* SNB: base of GTT stolen memory */

Here too.

Quoted 30 lines
hw/xen/xen_pt_graphics.c +28 -0
+        break;
+    default:
+        /* Just gets the emulated values. */
+        goto read_default;
+    }
+
+    /* Host read */
+    r = xen_host_pci_device_get(&dev, 0, 0, 0, 0);
+    if (r) {
+        goto err_out;
+    }
+
+    r = xen_host_pci_get_block(&dev, config_addr, (uint8_t *)&val, len);
+    if (r) {
+        goto err_out;
+    }
+
+    xen_host_pci_device_put(&dev);
+
+    return val;
+
+read_default:
+    return pci_default_read_config(pci_dev, config_addr, len);
+
+err_out:
+    XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
+    return -1;
+}
Signature · 1 line
1.9.1
#35 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

Quoted 11 lines · Michael S. Tsirkin
Quoted 10 lines · Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to passthrough these registers of physical host bridge to guest because emulated host bridge in guest doesn't have these mappings.

The original patch is from Weidong Han <[email protected]>

---

[snip]

Quoted 19 lines
Quoted 19 lines
hw/xen/xen_pt_graphics.c +19 -0
+
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len)
+{
+    XenHostPCIDevice dev;
+    uint32_t val;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto read_default;
+    }
+
+    /* Just work for the i915 driver. */
Quoted 8 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 414

Quoted 6 lines
hw/xen/xen_pt_graphics.c +6 -0
+    switch (config_addr) {
+    case 0x08:        /* revision id */
+    case 0x2c:        /* sybsystem vendor id */
+    case 0x2e:        /* sybsystem id */
+    case 0x44:        /* MCHBAR I915 */
+    case 0x48:        /* MCHBAR I965 */

In fact, this is returning host addresses to guest, right?

Yes. These two registers includes the address and some bits to control something. And the i915 driver just need to *read* address to reserve for PHP, but actually we don't support PHP now. So these address space are just be reserved.

And then it will *write* them with the PCI resources allocated in guest. And update those bits to enable or disable something in different occasions.

Actually we didn't introduce 0x44/0x48 originally but when Paolo saw the i915 driver will access them, so ask me what will be occurred. So I just add them simply to test again. But now looks they should be emulated, so I think we can get them out now. Then this should be enough to make sense.

Quoted 7 lines

Don't see how this can work except by luck.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 417

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0x50:        /* SNB: processor graphics control register */
+    case 0x52:        /* processor graphics control register */
+    case 0xa0:        /* top of memory */

which memory? Could be similar.

This is just a total memory used to the video device so we call top of memory. And this is used to limit that range, but as you know we never go over this so we can always live here.

Quoted 11 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 420

Quoted 4 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0xb0:        /* ILK: BSM: should read from dev 2 offset 0x5c */
+    case 0x58:        /* SNB: PAVPC Offset */
+    case 0xa4:        /* SNB: graphics base of stolen memory */

Same thing.

Quoted 1 line

+ case 0xa8: /* SNB: base of GTT stolen memory */

Here too.

We have 1:1 mapping for these two ranges so its fine.

These info are known to Linux. For Windows, it is opaque to us so we can't know what will be happened to Windows exactly, but I think this should be similar with Linux i915 driver mostly. And especially we also validate this on Windows 7 to confirm everything can work under Windows.

Thanks
Tiejun

#36 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

Quoted 48 lines · Tiejun
Quoted 11 lines · Michael S. Tsirkin
Quoted 10 lines · Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to passthrough these registers of physical host bridge to guest because emulated host bridge in guest doesn't have these mappings.

The original patch is from Weidong Han <[email protected]>

---

[snip]

Quoted 19 lines
Quoted 19 lines
hw/xen/xen_pt_graphics.c +19 -0
+
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len)
+{
+    XenHostPCIDevice dev;
+    uint32_t val;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto read_default;
+    }
+
+    /* Just work for the i915 driver. */
Quoted 8 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 414

Quoted 6 lines
hw/xen/xen_pt_graphics.c +6 -0
+    switch (config_addr) {
+    case 0x08:        /* revision id */
+    case 0x2c:        /* sybsystem vendor id */
+    case 0x2e:        /* sybsystem id */
+    case 0x44:        /* MCHBAR I915 */
+    case 0x48:        /* MCHBAR I965 */

In fact, this is returning host addresses to guest, right?

Yes. These two registers includes the address and some bits to control something. And the i915 driver just need to *read* address to reserve for PHP, but actually we don't support PHP now. So these address space are just be reserved.

Quoted 7 lines

And then it will *write* them with the PCI resources allocated in guest. And update those bits to enable or disable something in different occasions.

Actually we didn't introduce 0x44/0x48 originally but when Paolo saw the i915 driver will access them, so ask me what will be occurred. So I just add them simply to test again. But now looks they should be emulated, so I think we can get them out now. Then this should be enough to make sense.

Yes.

Quoted 11 lines
Quoted 7 lines

Don't see how this can work except by luck.

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 417

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0x50:        /* SNB: processor graphics control register */
+    case 0x52:        /* processor graphics control register */
+    case 0xa0:        /* top of memory */

which memory? Could be similar.

This is just a total memory used to the video device so we call top of memory. And this is used to limit that range, but as you know we never go over this so we can always live here.

Sorry I don't understand what you are saying here.

Quoted 5 lines
Quoted 5 lines
Quoted 4 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0xb0:        /* ILK: BSM: should read from dev 2 offset 0x5c */
+    case 0x58:        /* SNB: PAVPC Offset */
+    case 0xa4:        /* SNB: graphics base of stolen memory */
Quoted 8 lines
Quoted 6 lines

Same thing.

Quoted 1 line

+ case 0xa8: /* SNB: base of GTT stolen memory */

Here too.

We have 1:1 mapping for these two ranges so its fine.

Could you clarify? My question, again, is whether this is returning host addresses to guest.

Quoted 7 lines

These info are known to Linux. For Windows, it is opaque to us so we can't know what will be happened to Windows exactly, but I think this should be similar with Linux i915 driver mostly. And especially we also validate this on Windows 7 to confirm everything can work under Windows.

Thanks
Tiejun

#37 lore raw

Re: [Qemu-devel] [v5][PATCH 3/5] xen, gfx passthrough: support Intel IGD passthrough with VT-D

Quoted 65 lines · Michael S. Tsirkin
Quoted 48 lines · Tiejun
Quoted 11 lines · Michael S. Tsirkin
Quoted 10 lines · Tiejun Chen

Some registers of Intel IGD are mapped in host bridge, so it needs to passthrough these registers of physical host bridge to guest because emulated host bridge in guest doesn't have these mappings.

The original patch is from Weidong Han <[email protected]>

---

[snip]

Quoted 19 lines
Quoted 19 lines
hw/xen/xen_pt_graphics.c +19 -0
+
+uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len)
+{
+    XenHostPCIDevice dev;
+    uint32_t val;
+    int r;
+
+    /* IGD read/write is through the host bridge.
+     * ISA bridge is only for detect purpose. In i915 driver it will
+     * probe ISA bridge to discover the IGD, see comment in i915_drv.c:
+     * intel_detect_pch().
+     */
+    assert(pci_dev->devfn == 0x00);
+
+    if (!is_igd_passthrough(pci_dev)) {
+        goto read_default;
+    }
+
+    /* Just work for the i915 driver. */
Quoted 8 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 414

Quoted 6 lines
hw/xen/xen_pt_graphics.c +6 -0
+    switch (config_addr) {
+    case 0x08:        /* revision id */
+    case 0x2c:        /* sybsystem vendor id */
+    case 0x2e:        /* sybsystem id */
+    case 0x44:        /* MCHBAR I915 */
+    case 0x48:        /* MCHBAR I965 */

In fact, this is returning host addresses to guest, right?

Yes. These two registers includes the address and some bits to control something. And the i915 driver just need to *read* address to reserve for PHP, but actually we don't support PHP now. So these address space are just be reserved.

Quoted 7 lines

And then it will *write* them with the PCI resources allocated in guest. And update those bits to enable or disable something in different occasions.

Actually we didn't introduce 0x44/0x48 originally but when Paolo saw the i915 driver will access them, so ask me what will be occurred. So I just add them simply to test again. But now looks they should be emulated, so I think we can get them out now. Then this should be enough to make sense.

Yes.

Quoted 6 lines
Quoted 6 lines

Don't see how this can work except by luck.

Quoted 3 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0x50:        /* SNB: processor graphics control register */
+    case 0x52:        /* processor graphics control register */
+    case 0xa0:        /* top of memory */
Quoted 7 lines
Quoted 5 lines
Quoted 1 line

which memory? Could be similar.

This is just a total memory used to the video device so we call top of memory. And this is used to limit that range, but as you know we never go over this so we can always live here.

Sorry I don't understand what you are saying here.

Gfx guy told me the memory here is indicating the total amount of populated physical memory that can be allocated to VGA, so this is fine to guest as a amount.

Quoted 10 lines
Quoted 10 lines
Quoted 10 lines

hw/xen/xen_pt_graphics.c static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) · line 420

Quoted 5 lines
hw/xen/xen_pt_graphics.c +3 -0
+    case 0xb0:        /* ILK: BSM: should read from dev 2 offset 0x5c */
+    case 0x58:        /* SNB: PAVPC Offset */
+    case 0xa4:        /* SNB: graphics base of stolen memory */

Same thing.

Quoted 1 line

+ case 0xa8: /* SNB: base of GTT stolen memory */

Quoted 7 lines
Quoted 4 lines
Quoted 2 lines

Here too.

We have 1:1 mapping for these two ranges so its fine.

Could you clarify? My question, again, is whether this is returning host addresses to guest.

I means the host address is equal to the guest address and then 1:1 map between them.

Thanks
Tiejun

Quoted 10 lines
Quoted 8 lines

These info are known to Linux. For Windows, it is opaque to us so we can't know what will be happened to Windows exactly, but I think this should be similar with Linux i915 driver mostly. And especially we also validate this on Windows 7 to confirm everything can work under Windows.

Thanks
Tiejun

#38 lore raw

PATCH v5 4/5 xen, gfx passthrough: create host bridge to passthrough

In reply to Tiejun Chen

Implement that pci host bridge to specific to passthrough. Actually this just inherit the standard one.

---
v5:

* Nothing is changed.

v4:

* Fix one typo in the patch head description.
* Use (xen_enabled() && xen_has_gfx_passthru) to make sure we only work in this scenario.

v3:

* Just fix this patch head description typo.

v2:

* New patch.

 hw/pci-host/piix.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 54 insertions(+), 2 deletions(-)
hw/pci-host/piix.c +54 -2
index e0e0946..9acf901 100644
@@ -34,6 +34,7 @@
 #include "sysemu/sysemu.h"
 #include "hw/i386/ioapic.h"
 #include "qapi/visitor.h"
+#include "hw/xen/xen_pt.h"
 
 /*
  * I440FX chipset data sheet.
@@ -95,6 +96,10 @@ typedef struct PIIX3State {
 #define I440FX_PCI_DEVICE(obj) \
     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
 
+#define TYPE_I440FX_XEN_PCI_DEVICE "i440FX-xen"
+#define I440FX_XEN_PCI_DEVICE(obj) \
+    OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_XEN_PCI_DEVICE)
+
 struct PCII440FXState {
     /*< private >*/
     PCIDevice parent_obj;
@@ -305,6 +310,16 @@ static int i440fx_initfn(PCIDevice *dev)
     return 0;
 }
 
+static int i440fx_xen_initfn(PCIDevice *dev)
+{
+    PCII440FXState *d = I440FX_XEN_PCI_DEVICE(dev);
+
+    dev->config[I440FX_SMRAM] = 0x02;
+
+    cpu_smm_register(&i440fx_set_smm, d);
+    return 0;
+}
+
 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
                     int *piix3_devfn,
                     ISABus **isa_bus, qemu_irq *pic,
@@ -333,8 +348,15 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
     qdev_init_nofail(dev);
 
-    d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
-    *pi440fx_state = I440FX_PCI_DEVICE(d);
+    if (xen_enabled() && xen_has_gfx_passthru) {
+        d = pci_create_simple(b, 0, TYPE_I440FX_XEN_PCI_DEVICE);
+        *pi440fx_state = I440FX_XEN_PCI_DEVICE(d);
+        pci_create_pch(b);
+    } else {
+        d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
+        *pi440fx_state = I440FX_PCI_DEVICE(d);
+    }
+
     f = *pi440fx_state;
     f->system_memory = address_space_mem;
     f->pci_address_space = pci_address_space;
@@ -704,6 +726,35 @@ static const TypeInfo i440fx_info = {
     .class_init    = i440fx_class_init,
 };
 
+static void i440fx_xen_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->init = i440fx_xen_initfn;
+    k->config_write = igd_pci_write;
+    k->config_read = igd_pci_read;
+    k->vendor_id = PCI_VENDOR_ID_INTEL;
+    k->device_id = PCI_DEVICE_ID_INTEL_82441;
+    k->revision = 0x02;
+    k->class_id = PCI_CLASS_BRIDGE_ISA;
+    dc->desc = "XEN Host bridge";
+    dc->vmsd = &vmstate_i440fx;
+    /*
+     * PCI-facing part of the host bridge, not usable without the
+     * host-facing part, which can't be device_add'ed, yet.
+     */
+    dc->cannot_instantiate_with_device_add_yet = true;
+    dc->hotpluggable   = false;
+}
+
+static const TypeInfo i440fx_xen_info = {
+    .name          = TYPE_I440FX_XEN_PCI_DEVICE,
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(PCII440FXState),
+    .class_init    = i440fx_xen_class_init,
+};
+
 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
                                                 PCIBus *rootbus)
 {
@@ -745,6 +796,7 @@ static const TypeInfo i440fx_pcihost_info = {
 static void i440fx_register_types(void)
 {
     type_register_static(&i440fx_info);
+    type_register_static(&i440fx_xen_info);
     type_register_static(&piix3_info);
     type_register_static(&piix3_xen_info);
     type_register_static(&i440fx_pcihost_info);
Signature · 1 line
1.9.1
#39 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

hw/pci-host/piix.c PCIBus *i440fx_init(PCII440FXState **pi440fx_state, · line 358

Quoted 8 lines
hw/pci-host/piix.c +8 -0
+    if (xen_enabled() && xen_has_gfx_passthru) {
+        d = pci_create_simple(b, 0, TYPE_I440FX_XEN_PCI_DEVICE);
+        *pi440fx_state = I440FX_XEN_PCI_DEVICE(d);
+        pci_create_pch(b);
+    } else {
+        d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
+        *pi440fx_state = I440FX_PCI_DEVICE(d);
+    }

As mentioned in the review of v4, this should be a separate, Xen-specific machine. pci_create_pch should not be called in generic PC code.

Paolo

#40 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 10 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

hw/pci-host/piix.c PCIBus *i440fx_init(PCII440FXState **pi440fx_state, · line 358

Quoted 8 lines
hw/pci-host/piix.c +8 -0
+    if (xen_enabled() && xen_has_gfx_passthru) {
+        d = pci_create_simple(b, 0, TYPE_I440FX_XEN_PCI_DEVICE);
+        *pi440fx_state = I440FX_XEN_PCI_DEVICE(d);
+        pci_create_pch(b);
+    } else {
+        d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
+        *pi440fx_state = I440FX_PCI_DEVICE(d);
+    }
Quoted 4 lines

As mentioned in the review of v4, this should be a separate, Xen-specific machine. pci_create_pch should not be called in generic PC code.

I track this path:

qemu_register_pc_machine(&xenfv_machine);
	|
	+ .init = pc_xen_hvm_init,
		|
		+ pc_init_pci(machine);
			|
			+ pc_init1(machine, 1, 1);
				|
				+ i440fx_init()

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

If you don't like this involve other cases, we may drop this chunk of codes as a function to tweak with CONFIG_XEN. But this is not good as well since this is device feature, so kvm may need this one day.

Thanks
Tiejun

#41 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 5 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Paolo

#42 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 9 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 5 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 4 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Yes, Xen can use 'pc'.

Thanks
Tiejun

#43 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 16 lines · Tiejun
Quoted 9 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 5 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 1 line
Quoted 8 lines
Quoted 3 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Yes, Xen can use 'pc'.

Thanks
Tiejun

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

Signature · 1 line
MST
#44 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 21 lines · Michael S. Tsirkin
Quoted 20 lines · Tiejun
Quoted 9 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 5 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 4 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Quoted 7 lines
Quoted 4 lines

Yes, Xen can use 'pc'.

Thanks
Tiejun

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

Quoted 15 lines

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

#45 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 27 lines · Tiejun
Quoted 26 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 9 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 5 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 4 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Yes, Xen can use 'pc'.

Thanks
Tiejun

Quoted 6 lines
Quoted 2 lines

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

Anthony,

Any comments to address this in xen case?

Having a separate machine for this is reasonable. You can select the right one from libxl anyway. From the name point of view I would go with "xenigd".
Just take a look at xenfv and introduce something similar but specific to your IGD PT use case.

Quoted 19 lines

Thanks
Tiejun

Quoted 15 lines

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

#46 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Tiejun
Quoted 28 lines · Michael S. Tsirkin
Quoted 16 lines · Tiejun
Quoted 9 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 5 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 1 line
Quoted 8 lines
Quoted 3 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Yes, Xen can use 'pc'.

Thanks
Tiejun

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

Quoted 7 lines
Quoted 3 lines

Anthony,

Any comments to address this in xen case?

Having a separate machine for this is reasonable. You can select the right one from libxl anyway. From the name point of view I would go with "xenigd".

Do this mean we need to change something libxl?

Quoted 3 lines

Just take a look at xenfv and introduce something similar but specific to your IGD PT use case.

Which PCIe machine should I refer? i440fx or q35?

Thanks
Tiejun

Quoted 21 lines
Quoted 20 lines

Thanks
Tiejun

Quoted 15 lines

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

#47 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 36 lines · Tiejun
Quoted 35 lines · Stefano Stabellini
Quoted 34 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 22 lines · Tiejun
Quoted 10 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 6 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is
same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think
even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 4 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Quoted 7 lines
Quoted 4 lines

Yes, Xen can use 'pc'.

Thanks
Tiejun

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

Anthony,

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

Any comments to address this in xen case?

Having a separate machine for this is reasonable. You can select the right one from libxl anyway. From the name point of view I would go with "xenigd".

Do this mean we need to change something libxl?

Yes: you would need to pass a different -machine option, see tools/libxl/libxl_dm.c:libxl__build_device_model_args_new. It would be a pretty small change.

Quoted 5 lines
Quoted 3 lines

Just take a look at xenfv and introduce something similar but specific to your IGD PT use case.

Which PCIe machine should I refer? i440fx or q35?

I'd say i440fx.

Quoted 25 lines

Thanks
Tiejun

Quoted 21 lines
Quoted 20 lines

Thanks
Tiejun

Quoted 15 lines

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

#48 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 49 lines · Stefano Stabellini
Quoted 36 lines · Tiejun
Quoted 35 lines · Stefano Stabellini
Quoted 34 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 22 lines · Tiejun
Quoted 10 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 6 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is
same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think
even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 4 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Quoted 7 lines
Quoted 4 lines

Yes, Xen can use 'pc'.

Thanks
Tiejun

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

Anthony,

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

Any comments to address this in xen case?

Having a separate machine for this is reasonable. You can select the right one from libxl anyway. From the name point of view I would go with "xenigd".

Do this mean we need to change something libxl?

Yes: you would need to pass a different -machine option, see tools/libxl/libxl_dm.c:libxl__build_device_model_args_new. It would be a pretty small change.

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines

Just take a look at xenfv and introduce something similar but specific to your IGD PT use case.

Which PCIe machine should I refer? i440fx or q35?

I'd say i440fx.

I have some doubts this can work cleanly, but if you want to attempt this, be my guest.

So what you want is really franken-i440fx which has this fake isa bridge and a mixed config from piix and mch.
The idea seems to be to make existing guests work, in light of this I really don't see the point of pushing any guest changes.

So first step is just to implement these two, they should have nothing to do with xen specifically, should work fine on all hosts, with tcg,kvm etc. ISA bridge would just appearing as dummy device there. Get flags as features for now.
Optionally, as an extra user-friendly feature, you can add a flag that lets you poke at host and get device IDs etc from sysfs there. Pls make this a separate patch though, and we'll discuss this separately.

Same requirement would apply to q35 really - it's not specific to i440fx.

Also please don't push more guest code upstream until qemu has something merged or close to being merged. You are just creating more messy configurations that have to be supported.

Quoted 26 lines
Quoted 26 lines

Thanks
Tiejun

Quoted 21 lines
Quoted 20 lines

Thanks
Tiejun

Quoted 15 lines

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

#49 lore raw

Re: [Qemu-devel] [v5][PATCH 4/5] xen, gfx passthrough: create host bridge to passthrough

Quoted 66 lines · Michael S. Tsirkin
Quoted 49 lines · Stefano Stabellini
Quoted 36 lines · Tiejun
Quoted 35 lines · Stefano Stabellini
Quoted 34 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 22 lines · Tiejun
Quoted 10 lines · Paolo Bonzini

Il 27/06/2014 10:34, Chen, Tiejun ha scritto:

Quoted 6 lines

So how to separate this to specific to xen? Or you mean we need to create an new machine to address this scenario? But actually this is
same as xenfv_machine except for these little codes.

Yes, please create a new machine so that "-M pc" doesn't have any of these hacks.

But regardless of the machine is 'xenfv' or 'pc', we always call pc_init_pci(), then inside, i440fx_init() is always performed. So I think
even we create a new machine, shouldn't we still call pc_init_pci()?

Quoted 4 lines

Note that "-M xenfv" is obsolete, Xen can now use "-M pc" (i.e. the default).

Quoted 7 lines
Quoted 4 lines

Yes, Xen can use 'pc'.

Thanks
Tiejun

You are creating a new machine type where the pci host looks like MCH but a bunch of other things are from i440fx.

Anthony,

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

Any comments to address this in xen case?

Having a separate machine for this is reasonable. You can select the right one from libxl anyway. From the name point of view I would go with "xenigd".

Do this mean we need to change something libxl?

Yes: you would need to pass a different -machine option, see tools/libxl/libxl_dm.c:libxl__build_device_model_args_new. It would be a pretty small change.

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines

Just take a look at xenfv and introduce something similar but specific to your IGD PT use case.

Which PCIe machine should I refer? i440fx or q35?

I'd say i440fx.

I have some doubts this can work cleanly, but if you want to attempt this, be my guest.

So what you want is really franken-i440fx which has this fake isa bridge and a mixed config from piix and mch.
The idea seems to be to make existing guests work, in light of this I really don't see the point of pushing any guest changes.

Quoted 8 lines

So first step is just to implement these two, they should have nothing to do with xen specifically, should work fine on all hosts, with tcg,kvm etc. ISA bridge would just appearing as dummy device there. Get flags as features for now.
Optionally, as an extra user-friendly feature, you can add a flag that lets you poke at host and get device IDs etc from sysfs there. Pls make this a separate patch though, and we'll discuss this separately.

Clarification: that's not a promise that it's mergeable if done that way, we'll have to evaluate the registers that franken-piix overrides and weight the chances that
1. guest will start poking at more registers in the future or
2. piix will want to use them in the future
leading to maintainance problems.

What I saw so far seems too fragile, I hope most of it isn't actually required.

And this is why I was saying start with an MCH based chipset instead.

Quoted 34 lines

Same requirement would apply to q35 really - it's not specific to i440fx.

Also please don't push more guest code upstream until qemu has something merged or close to being merged. You are just creating more messy configurations that have to be supported.

Quoted 26 lines
Quoted 26 lines

Thanks
Tiejun

Quoted 21 lines
Quoted 20 lines

Thanks
Tiejun

Quoted 15 lines

I have some doubts about this combination being worth supporting - it does not seem useful for anything except xen from the code you posted, but maybe you can whittle down the number of places where you poke at the host to make it reasonable: I can imagine that, if you are lucky and the registers that i915 wants to poke to make it work on real hardware happen to fall on top of reserved registers in the i440FX/PIIX3 pci bridge. OTOH it would be much more likely if you just start with something that does have MCH, like Q35, or emulate a newer machine type. This is the path that people who wanted
to boot iOS on QEMU took, and the result is pretty good.

But regardless, this is clearly not a i440fx nor a q35 pc so it needs a separate name.

#50 lore raw

PATCH v5 5/5 xen, gfx passthrough: add opregion mapping

In reply to Tiejun Chen

The OpRegion shouldn't be mapped 1:1 because the address in the host can't be used in the guest directly.

This patch traps read and write access to the opregion of the Intel GPU config space (offset 0xfc).

The original patch is from Jean Guyader <[email protected]>

---
v5:

* Nothing is changed.

v4:

* Nothing is changed.

v3:

* Fix some typos.
* Add more comments to make that readable.
* To unmap igd_opregion when call xen_pt_unregister_vga_regions().
* Improve some return paths.
* We need to map 3 pages for opregion as hvmloader set.
* Force to convert igd_guest/host_opoegion as an unsigned long type while calling xc_domain_memory_mapping().

v2:

* We should return zero as an invalid address value while calling igd_read_opregion().

 hw/xen/xen_pt.h             |  4 ++-
 hw/xen/xen_pt_config_init.c | 50 ++++++++++++++++++++++++++++++++++-
 hw/xen/xen_pt_graphics.c    | 64 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+), 2 deletions(-)
hw/xen/xen_pt.h +3 -1
index 507165c..25147cf 100644
@@ -63,7 +63,7 @@ typedef int (*xen_pt_conf_byte_read)
 #define XEN_PT_BAR_UNMAPPED (-1)
 
 #define PCI_CAP_MAX 48
-
+#define PCI_INTEL_OPREGION 0xfc
 
 typedef enum {
     XEN_PT_GRP_TYPE_HARDWIRED = 0,  /* 0 Hardwired reg group */
@@ -306,5 +306,7 @@ int pci_create_pch(PCIBus *bus);
 void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
                    uint32_t val, int len);
 uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len);
+uint32_t igd_read_opregion(XenPCIPassthroughState *s);
+void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_config_init.c +49 -1

80 lines not on this page · raw message

hw/xen/xen_pt_graphics.c +64 -0

85 lines not on this page · raw message

Signature · 1 line
1.9.1
#51 lore raw

Re: [Qemu-devel] [v5][PATCH 5/5] xen, gfx passthrough: add opregion mapping

Quoted 45 lines · Tiejun Chen

The OpRegion shouldn't be mapped 1:1 because the address in the host can't be used in the guest directly.

This patch traps read and write access to the opregion of the Intel GPU config space (offset 0xfc).

The original patch is from Jean Guyader <[email protected]>

---
v5:

* Nothing is changed.

v4:

* Nothing is changed.

v3:

* Fix some typos.
* Add more comments to make that readable.
* To unmap igd_opregion when call xen_pt_unregister_vga_regions().
* Improve some return paths.
* We need to map 3 pages for opregion as hvmloader set.
* Force to convert igd_guest/host_opoegion as an unsigned long type while calling xc_domain_memory_mapping().

v2:

* We should return zero as an invalid address value while calling igd_read_opregion().

 hw/xen/xen_pt.h             |  4 ++-
 hw/xen/xen_pt_config_init.c | 50 ++++++++++++++++++++++++++++++++++-
 hw/xen/xen_pt_graphics.c    | 64 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+), 2 deletions(-)
hw/xen/xen_pt.h +0 -0
index 507165c..25147cf 100644

hw/xen/xen_pt.h typedef int (*xen_pt_conf_byte_read) · line 67

Quoted 6 lines
hw/xen/xen_pt.h +1 -1
@@ -63,7 +63,7 @@ typedef int (*xen_pt_conf_byte_read)
 #define XEN_PT_BAR_UNMAPPED (-1)
 
 #define PCI_CAP_MAX 48
-
+#define PCI_INTEL_OPREGION 0xfc
 

XEN_.... please

PCI_CAP_MAX should be fixed too.

Quoted 122 lines
hw/xen/xen_pt.h +2 -0
 typedef enum {
     XEN_PT_GRP_TYPE_HARDWIRED = 0,  /* 0 Hardwired reg group */
@@ -306,5 +306,7 @@ int pci_create_pch(PCIBus *bus);
 void igd_pci_write(PCIDevice *pci_dev, uint32_t config_addr,
                    uint32_t val, int len);
 uint32_t igd_pci_read(PCIDevice *pci_dev, uint32_t config_addr, int len);
+uint32_t igd_read_opregion(XenPCIPassthroughState *s);
+void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
 
 #endif /* !XEN_PT_H */
hw/xen/xen_pt_config_init.c +49 -1
index de9a20f..6eaaa9a 100644
@@ -575,6 +575,22 @@ static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
     return 0;
 }
 
+static int xen_pt_intel_opregion_read(XenPCIPassthroughState *s,
+                                      XenPTReg *cfg_entry,
+                                      uint32_t *value, uint32_t valid_mask)
+{
+    *value = igd_read_opregion(s);
+    return 0;
+}
+
+static int xen_pt_intel_opregion_write(XenPCIPassthroughState *s,
+                                       XenPTReg *cfg_entry, uint32_t *value,
+                                       uint32_t dev_value, uint32_t valid_mask)
+{
+    igd_write_opregion(s, *value);
+    return 0;
+}
+
 /* Header Type0 reg static information table */
 static XenPTRegInfo xen_pt_emu_reg_header0[] = {
     /* Vendor ID reg */
@@ -1440,6 +1456,20 @@ static XenPTRegInfo xen_pt_emu_reg_msix[] = {
     },
 };
 
+static XenPTRegInfo xen_pt_emu_reg_igd_opregion[] = {
+    /* Intel IGFX OpRegion reg */
+    {
+        .offset     = 0x0,
+        .size       = 4,
+        .init_val   = 0,
+        .no_wb      = 1,
+        .u.dw.read   = xen_pt_intel_opregion_read,
+        .u.dw.write  = xen_pt_intel_opregion_write,
+    },
+    {
+        .size = 0,
+    },
+};
 
 /****************************
  * Capabilities
@@ -1677,6 +1707,14 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
         .size_init   = xen_pt_msix_size_init,
         .emu_regs = xen_pt_emu_reg_msix,
     },
+    /* Intel IGD Opregion group */
+    {
+        .grp_id      = PCI_INTEL_OPREGION,
+        .grp_type    = XEN_PT_GRP_TYPE_EMU,
+        .grp_size    = 0x4,
+        .size_init   = xen_pt_reg_grp_size_init,
+        .emu_regs    = xen_pt_emu_reg_igd_opregion,
+    },
     {
         .grp_size = 0,
     },
@@ -1806,7 +1844,8 @@ int xen_pt_config_init(XenPCIPassthroughState *s)
         uint32_t reg_grp_offset = 0;
         XenPTRegGroup *reg_grp_entry = NULL;
 
-        if (xen_pt_emu_reg_grps[i].grp_id != 0xFF) {
+        if (xen_pt_emu_reg_grps[i].grp_id != 0xFF
+            && xen_pt_emu_reg_grps[i].grp_id != PCI_INTEL_OPREGION) {
             if (xen_pt_hide_dev_cap(&s->real_device,
                                     xen_pt_emu_reg_grps[i].grp_id)) {
                 continue;
@@ -1819,6 +1858,15 @@ int xen_pt_config_init(XenPCIPassthroughState *s)
             }
         }
 
+        /*
+         * By default we will trap up to 0x40 in the cfg space.
+         * If an intel device is pass through we need to trap 0xfc,
+         * therefore the size should be 0xff.
+         */
+        if (xen_pt_emu_reg_grps[i].grp_id == PCI_INTEL_OPREGION) {
+            reg_grp_offset = PCI_INTEL_OPREGION;
+        }
+
         reg_grp_entry = g_new0(XenPTRegGroup, 1);
         QLIST_INIT(&reg_grp_entry->reg_tbl_list);
         QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
hw/xen/xen_pt_graphics.c +4 -0
index f3fbfed..fa341ad 100644
@@ -6,6 +6,9 @@
 #include "hw/xen/xen_backend.h"
 #include "hw/pci/pci_bus.h"
 
+static unsigned long igd_guest_opregion;
+static unsigned long igd_host_opregion;
+
 static int is_vga_passthrough(XenHostPCIDevice *dev)
 {
     return (xen_has_gfx_passthru
@@ -88,6 +91,7 @@ int xen_pt_register_vga_regions(XenHostPCIDevice *dev)
 int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
 {
     int i = 0;
+    int ret = 0;
 
     if (!is_vga_passthrough(dev)) {
         return 0;

hw/xen/xen_pt_graphics.c int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev) · line 124

Quoted 7 lines
hw/xen/xen_pt_graphics.c +4 -0
@@ -114,6 +118,17 @@ int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
         }
     }
 
+    if (igd_guest_opregion) {
+        ret = xc_domain_memory_mapping(xen_xc, xen_domid,
+                (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
+                (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),

don't spread casts all around.
Should be a last resort.

Quoted 11 lines
hw/xen/xen_pt_graphics.c +7 -0
+                3,
+                DPCI_REMOVE_MAPPING);
+        if (ret) {
+            return ret;
+        }
+    }
+
     return 0;
 }
 

hw/xen/xen_pt_graphics.c err_out: · line 470

Quoted 9 lines
hw/xen/xen_pt_graphics.c +6 -0
@@ -447,3 +462,52 @@ err_out:
     XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
     return -1;
 }
+
+uint32_t igd_read_opregion(XenPCIPassthroughState *s)
+{
+    uint32_t val = 0;
+
+    if (igd_guest_opregion == 0) {

!igd_guest_opregion is shorter and does the same,

Quoted 14 lines
hw/xen/xen_pt_graphics.c +14 -0
+        return val;
+    }
+
+    val = igd_guest_opregion;
+
+    XEN_PT_LOG(&s->dev, "Read opregion val=%x\n", val);
+    return val;
+}
+
+void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val)
+{
+    int ret;
+
+    if (igd_guest_opregion) {

hw/xen/xen_pt_graphics.c err_out: · line 494

Quoted 10 lines
hw/xen/xen_pt_graphics.c +10 -0
+        XEN_PT_LOG(&s->dev, "opregion register already been set, ignoring %x\n",
+                   val);
+        return;
+    }
+
+    xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
+            (uint8_t *)&igd_host_opregion, 4);
+    igd_guest_opregion = (unsigned long)(val & ~0xfff)
+                            | (igd_host_opregion & 0xfff);
+

Clearly broken on BE.
Maybe not important here but writing clean code is just as easy.
uint8_t igd_host_opregion[4];

...

    xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
			   igd_host_opregion, sizeof igd_host_opregion);

    igd_guest_opregion = (val & ~0xfff) |
	    (pci_get_word(igd_host_opregion) & 0xfff);

0xfff should be a macro too to avoid duplication.

Quoted 21 lines
hw/xen/xen_pt_graphics.c +19 -0
+    ret = xc_domain_memory_mapping(xen_xc, xen_domid,
+            (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
+            (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
+            3,
+            DPCI_ADD_MAPPING);
+
+    if (ret) {
+        XEN_PT_ERR(&s->dev, "[%d]:Can't map IGD host opregion:0x%lx to"
+                    " guest opregion:0x%lx.\n", ret,
+                    (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
+                    (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT));
+        igd_guest_opregion = 0;
+        return;
+    }
+
+    XEN_PT_LOG(&s->dev, "Map OpRegion: 0x%lx -> 0x%lx\n",
+                    (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
+                    (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT));
+}
Signature · 1 line
1.9.1
#52 lore raw

Re: [Qemu-devel] [v5][PATCH 5/5] xen, gfx passthrough: add opregion mapping

Quoted 1 line · Michael S. Tsirkin

On Wed, Jun 25, 2014 at 10:17:21AM +0800, Tiejun Chen wrote:

[snip]

Quoted 7 lines
Quoted 7 lines
hw/xen/xen_pt.h +0 -0
index 507165c..25147cf 100644
@@ -63,7 +63,7 @@ typedef int (*xen_pt_conf_byte_read)
  #define XEN_PT_BAR_UNMAPPED (-1)
 
Quoted 8 lines

hw/xen/xen_pt.h typedef int (*xen_pt_conf_byte_read) · line 67

Quoted 4 lines
hw/xen/xen_pt.h +1 -1
  #define PCI_CAP_MAX 48
-
+#define PCI_INTEL_OPREGION 0xfc
 

XEN_.... please

PCI_CAP_MAX should be fixed too.

They are specific to PCI, not XEN. Why should we add such a prefix?

Quoted 2 lines

[snip]

Quoted 8 lines

hw/xen/xen_pt.h

Quoted 5 lines
hw/xen/xen_pt.h +4 -0
+    if (igd_guest_opregion) {
+        ret = xc_domain_memory_mapping(xen_xc, xen_domid,
+                (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
+                (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),

don't spread casts all around.
Should be a last resort.

Okay.

Quoted 11 lines
Quoted 11 lines
hw/xen/xen_pt.h +7 -0
+                3,
+                DPCI_REMOVE_MAPPING);
+        if (ret) {
+            return ret;
+        }
+    }
+
      return 0;
  }
Quoted 12 lines

hw/xen/xen_pt.h err_out: · line 470

Quoted 10 lines
hw/xen/xen_pt.h +6 -0
@@ -447,3 +462,52 @@ err_out:
      XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
      return -1;
  }
+
+uint32_t igd_read_opregion(XenPCIPassthroughState *s)
+{
+    uint32_t val = 0;
+
+    if (igd_guest_opregion == 0) {

!igd_guest_opregion is shorter and does the same,

Okay.

Quoted 19 lines
Quoted 19 lines
hw/xen/xen_pt.h +18 -0
+        return val;
+    }
+
+    val = igd_guest_opregion;
+
+    XEN_PT_LOG(&s->dev, "Read opregion val=%x\n", val);
+    return val;
+}
+
+void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val)
+{
+    int ret;
+
+    if (igd_guest_opregion) {
+        XEN_PT_LOG(&s->dev, "opregion register already been set, ignoring %x\n",
+                   val);
+        return;
+    }
Quoted 8 lines

hw/xen/xen_pt.h err_out: · line 494

Quoted 6 lines
hw/xen/xen_pt.h +6 -0
+
+    xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
+            (uint8_t *)&igd_host_opregion, 4);
+    igd_guest_opregion = (unsigned long)(val & ~0xfff)
+                            | (igd_host_opregion & 0xfff);
+

Clearly broken on BE.

I still can't understand why we need to address this in BE case.

Quoted 6 lines

Maybe not important here but writing clean code is just as easy.
uint8_t igd_host_opregion[4];

...

Quoted 8 lines
     xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
			   igd_host_opregion, sizeof igd_host_opregion);

     igd_guest_opregion = (val & ~0xfff) |
	    (pci_get_word(igd_host_opregion) & 0xfff);

0xfff should be a macro too to avoid duplication.

Okay.

Thanks
Tiejun

#53 lore raw

Re: [Qemu-devel] [v5][PATCH 5/5] xen, gfx passthrough: add opregion mapping

Quoted 19 lines · Tiejun
Quoted 1 line · Michael S. Tsirkin

On Wed, Jun 25, 2014 at 10:17:21AM +0800, Tiejun Chen wrote:

[snip]

Quoted 14 lines

hw/xen/xen_pt.h typedef int (*xen_pt_conf_byte_read) · line 67

Quoted 11 lines
hw/xen/xen_pt.h +1 -1
index 507165c..25147cf 100644
@@ -63,7 +63,7 @@ typedef int (*xen_pt_conf_byte_read)
 #define XEN_PT_BAR_UNMAPPED (-1)
 
 #define PCI_CAP_MAX 48
-
+#define PCI_INTEL_OPREGION 0xfc
 

XEN_.... please

Quoted 3 lines
Quoted 1 line

PCI_CAP_MAX should be fixed too.

They are specific to PCI, not XEN.

They are? Where in the PCI spec does it say 48?
Same for PCI_INTEL_OPREGION.

Quoted 1 line

Why should we add such a prefix?

So that people working on core pci do not have to worry about breaking your devices by adding a symbol in the global header.

Quoted 70 lines
Quoted 2 lines

[snip]

Quoted 8 lines

hw/xen/xen_pt.h

Quoted 5 lines
hw/xen/xen_pt.h +4 -0
+    if (igd_guest_opregion) {
+        ret = xc_domain_memory_mapping(xen_xc, xen_domid,
+                (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
+                (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),

don't spread casts all around.
Should be a last resort.

Okay.

Quoted 11 lines
Quoted 11 lines
hw/xen/xen_pt.h +7 -0
+                3,
+                DPCI_REMOVE_MAPPING);
+        if (ret) {
+            return ret;
+        }
+    }
+
     return 0;
 }
Quoted 12 lines

hw/xen/xen_pt.h err_out: · line 470

Quoted 10 lines
hw/xen/xen_pt.h +6 -0
@@ -447,3 +462,52 @@ err_out:
     XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
     return -1;
 }
+
+uint32_t igd_read_opregion(XenPCIPassthroughState *s)
+{
+    uint32_t val = 0;
+
+    if (igd_guest_opregion == 0) {

!igd_guest_opregion is shorter and does the same,

Okay.

Quoted 19 lines
Quoted 19 lines
hw/xen/xen_pt.h +18 -0
+        return val;
+    }
+
+    val = igd_guest_opregion;
+
+    XEN_PT_LOG(&s->dev, "Read opregion val=%x\n", val);
+    return val;
+}
+
+void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val)
+{
+    int ret;
+
+    if (igd_guest_opregion) {
+        XEN_PT_LOG(&s->dev, "opregion register already been set, ignoring %x\n",
+                   val);
+        return;
+    }
Quoted 8 lines

hw/xen/xen_pt.h err_out: · line 494

Quoted 6 lines
hw/xen/xen_pt.h +6 -0
+
+    xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
+            (uint8_t *)&igd_host_opregion, 4);
+    igd_guest_opregion = (unsigned long)(val & ~0xfff)
+                            | (igd_host_opregion & 0xfff);
+

Clearly broken on BE.

Quoted 1 line

I still can't understand why we need to address this in BE case.

So code is clean and reusable. Copy and paste is a fact of life, you don't want people to inherit bugs.
If some code absolutely must be LE specific,
it needs a comment that explains this and cautions people against trying to use it elsewhere in QEMU.

Quoted 19 lines
Quoted 6 lines

Maybe not important here but writing clean code is just as easy.
uint8_t igd_host_opregion[4];

...

Quoted 8 lines
    xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
			   igd_host_opregion, sizeof igd_host_opregion);

    igd_guest_opregion = (val & ~0xfff) |
	    (pci_get_word(igd_host_opregion) & 0xfff);

0xfff should be a macro too to avoid duplication.

Okay.

Thanks
Tiejun

#54 lore raw

Re: [Qemu-devel] [v5][PATCH 5/5] xen, gfx passthrough: add opregion mapping

Quoted 24 lines · Michael S. Tsirkin
Quoted 19 lines · Tiejun
Quoted 1 line · Michael S. Tsirkin

On Wed, Jun 25, 2014 at 10:17:21AM +0800, Tiejun Chen wrote:

[snip]

Quoted 14 lines

hw/xen/xen_pt.h typedef int (*xen_pt_conf_byte_read) · line 67

Quoted 11 lines
hw/xen/xen_pt.h +1 -1
index 507165c..25147cf 100644
@@ -63,7 +63,7 @@ typedef int (*xen_pt_conf_byte_read)
  #define XEN_PT_BAR_UNMAPPED (-1)
 
  #define PCI_CAP_MAX 48
-
+#define PCI_INTEL_OPREGION 0xfc
 

XEN_.... please

Quoted 3 lines
Quoted 1 line

PCI_CAP_MAX should be fixed too.

They are specific to PCI, not XEN.

Quoted 7 lines

They are? Where in the PCI spec does it say 48?
Same for PCI_INTEL_OPREGION.

Quoted 1 line

Why should we add such a prefix?

So that people working on core pci do not have to worry about breaking your devices by adding a symbol in the global header.

Okay.

Quoted 72 lines
Quoted 72 lines
Quoted 4 lines

[snip]

Quoted 8 lines

hw/xen/xen_pt.h

Quoted 5 lines
hw/xen/xen_pt.h +4 -0
+    if (igd_guest_opregion) {
+        ret = xc_domain_memory_mapping(xen_xc, xen_domid,
+                (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
+                (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),

don't spread casts all around.
Should be a last resort.

Okay.

Quoted 11 lines
Quoted 11 lines
hw/xen/xen_pt.h +7 -0
+                3,
+                DPCI_REMOVE_MAPPING);
+        if (ret) {
+            return ret;
+        }
+    }
+
      return 0;
  }
Quoted 12 lines

hw/xen/xen_pt.h err_out: · line 470

Quoted 10 lines
hw/xen/xen_pt.h +6 -0
@@ -447,3 +462,52 @@ err_out:
      XEN_PT_ERR(pci_dev, "Can't get pci_dev_host_bridge\n");
      return -1;
  }
+
+uint32_t igd_read_opregion(XenPCIPassthroughState *s)
+{
+    uint32_t val = 0;
+
+    if (igd_guest_opregion == 0) {

!igd_guest_opregion is shorter and does the same,

Okay.

Quoted 27 lines
Quoted 15 lines
hw/xen/xen_pt.h +14 -0
+        return val;
+    }
+
+    val = igd_guest_opregion;
+
+    XEN_PT_LOG(&s->dev, "Read opregion val=%x\n", val);
+    return val;
+}
+
+void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val)
+{
+    int ret;
+
+    if (igd_guest_opregion) {

hw/xen/xen_pt.h err_out: · line 494

Quoted 10 lines
hw/xen/xen_pt.h +10 -0
+        XEN_PT_LOG(&s->dev, "opregion register already been set, ignoring %x\n",
+                   val);
+        return;
+    }
+
+    xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
+            (uint8_t *)&igd_host_opregion, 4);
+    igd_guest_opregion = (unsigned long)(val & ~0xfff)
+                            | (igd_host_opregion & 0xfff);
+

Clearly broken on BE.

Quoted 4 lines
Quoted 1 line

I still can't understand why we need to address this in BE case.

So code is clean and reusable. Copy and paste is a fact of life, you don't want people to inherit bugs.

Understood.

Quoted 3 lines

If some code absolutely must be LE specific, it needs a comment that explains this and cautions people against trying to use it elsewhere in QEMU.

I think its fine enough to add a comment.

Thanks
Tiejun

Quoted 22 lines
Quoted 21 lines
Quoted 8 lines

Maybe not important here but writing clean code is just as easy.
uint8_t igd_host_opregion[4];

...

Quoted 8 lines
     xen_host_pci_get_block(&s->real_device, PCI_INTEL_OPREGION,
			   igd_host_opregion, sizeof igd_host_opregion);

     igd_guest_opregion = (val & ~0xfff) |
	    (pci_get_word(igd_host_opregion) & 0xfff);

0xfff should be a macro too to avoid duplication.

Okay.

Thanks
Tiejun

#55 lore raw
In reply to Tiejun Chen

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 2 lines

* Don't set that ISA class property, instead, just fake this ISA bridge with 00:1f.0.

How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0?

Paolo

#56 lore raw
Quoted 8 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 2 lines

* Don't set that ISA class property, instead, just fake this ISA bridge with 00:1f.0.

How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0?

Paolo

Maybe it just works?
Is tweaking vendor/device/revision id to match host really necessary?

Signature · 1 line
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#57 lore raw

Il 25/06/2014 09:15, Michael S. Tsirkin ha scritto:

Quoted 2 lines

Maybe it just works?
Is tweaking vendor/device/revision id to match host really necessary?

Yes, the driver inspects the fields and tweaks its behavior according to them. It also pokes at configuration space of the host bridge. It's quite disgusting.

Paolo

#58 lore raw
In reply to Paolo Bonzini
Quoted 7 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 2 lines

* Don't set that ISA class property, instead, just fake this ISA bridge with 00:1f.0.

How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0?

Could we simply pass the vendor/device ids of the host ISA bridge here?

Thanks
Tiejun

#59 lore raw
Quoted 5 lines · Tiejun
Quoted 4 lines · Paolo Bonzini

Il 25/06/2014 04:17, Tiejun Chen ha scritto:

Quoted 2 lines

* Don't set that ISA class property, instead, just fake this ISA bridge with 00:1f.0.

Quoted 8 lines
Quoted 3 lines

How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0?

Could we simply pass the vendor/device ids of the host ISA bridge here?

Thanks
Tiejun

Will firmware have drivers for this bridge?

Signature · 1 line
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#60 lore raw
In reply to Chen, Tiejun

Il 25/06/2014 09:35, Chen, Tiejun ha scritto:

Quoted 5 lines
Quoted 3 lines

How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0?

Could we simply pass the vendor/device ids of the host ISA bridge here?

No, because the firmware then would not recognize the host ISA bridge and would fail to initialize the ACPI PMBASE, the PCI interrupt routing, etc.

Paolo

#61 lore raw
Quoted 11 lines · Paolo Bonzini

Il 25/06/2014 09:35, Chen, Tiejun ha scritto:

Quoted 5 lines
Quoted 3 lines

How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0?

Could we simply pass the vendor/device ids of the host ISA bridge here?

No, because the firmware then would not recognize the host ISA bridge and would fail to initialize the ACPI PMBASE, the PCI interrupt routing, etc.

Paolo

It might be possible to move the Q35 bridge elsewhere. seabios doesn't care where the host bridge is. ACPI tables in QEMU can be adjusted.

#62 lore raw

Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:

Quoted 3 lines

It might be possible to move the Q35 bridge elsewhere. seabios doesn't care where the host bridge is. ACPI tables in QEMU can be adjusted.

But why? It's always in 00:1f.0 on real hardware. If the i915 driver wants to run under virtual machines, it should stop acting as if it knows what the whole machine looks like.

Paolo

#63 lore raw
Quoted 10 lines · Paolo Bonzini

Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:

Quoted 3 lines

It might be possible to move the Q35 bridge elsewhere. seabios doesn't care where the host bridge is. ACPI tables in QEMU can be adjusted.

But why? It's always in 00:1f.0 on real hardware. If the i915 driver wants to run under virtual machines, it should stop acting as if it knows what the whole machine looks like.

Paolo

If guest driver can be fixed that seems ideal. I don't know how it works but presumably you guys do?

Signature · 1 line
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#64 lore raw
Quoted 6 lines · Michael S. Tsirkin
Quoted 5 lines · Paolo Bonzini

Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:

Quoted 3 lines

It might be possible to move the Q35 bridge elsewhere. seabios doesn't care where the host bridge is. ACPI tables in QEMU can be adjusted.

Quoted 8 lines
Quoted 5 lines

But why? It's always in 00:1f.0 on real hardware. If the i915 driver wants to run under virtual machines, it should stop acting as if it knows what the whole machine looks like.

Paolo

If guest driver can be fixed that seems ideal. I don't know how it works but presumably you guys do?

Paolo prefer we need to fix this in the driver like:

"

Quoted 10 lines
Quoted 6 lines
Quoted 2 lines

The right way could be to make QEMU add a vendor-specific capability to the video device. The driver can probe for that capability before

Do you mean we can pick two unused offsets in the configuration space of the video device as a vendor-specific capability to hold the vendor/device ids of the PCH?

Yes, either that or add a new capability (which lets you choose the offsets more freely).

Quoted 6 lines

If the IGD driver needs config space fields of the MCH, those fields could also be mirrored in the new capability. QEMU would forward them automatically.

It could even be a new BAR, which gives even more freedom to allocate the fields.

"

Thanks
Tiejun

#65 lore raw
Quoted 33 lines · Tiejun
Quoted 6 lines · Michael S. Tsirkin
Quoted 5 lines · Paolo Bonzini

Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:

Quoted 3 lines

It might be possible to move the Q35 bridge elsewhere. seabios doesn't care where the host bridge is. ACPI tables in QEMU can be adjusted.

Quoted 8 lines
Quoted 5 lines

But why? It's always in 00:1f.0 on real hardware. If the i915 driver wants to run under virtual machines, it should stop acting as if it knows what the whole machine looks like.

Paolo

If guest driver can be fixed that seems ideal. I don't know how it works but presumably you guys do?

Paolo prefer we need to fix this in the driver like:

"

Quoted 14 lines
Quoted 6 lines
Quoted 2 lines

The right way could be to make QEMU add a vendor-specific capability to the video device. The driver can probe for that capability before

Do you mean we can pick two unused offsets in the configuration space of the video device as a vendor-specific capability to hold the vendor/device ids of the PCH?

Yes, either that or add a new capability (which lets you choose the offsets more freely).

If the IGD driver needs config space fields of the MCH, those fields could also be mirrored in the new capability. QEMU would forward them automatically.

Quoted 6 lines
Quoted 2 lines

It could even be a new BAR, which gives even more freedom to allocate the fields.

"

Thanks
Tiejun

Adding a vendor-specific capability or BAR
in an existing device is painful - hard to find free space for it.
We could add a dummy device in PCI or ACPI, but driver should really look for it using device/vendor id, not at a specific address.
What exactly is it that the driver wants to know?

Signature · 1 line
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#66 lore raw
Quoted 36 lines · Michael S. Tsirkin
Quoted 35 lines · Tiejun
Quoted 6 lines · Michael S. Tsirkin
Quoted 5 lines · Paolo Bonzini

Il 25/06/2014 10:31, Michael S. Tsirkin ha scritto:

Quoted 3 lines

It might be possible to move the Q35 bridge elsewhere. seabios doesn't care where the host bridge is. ACPI tables in QEMU can be adjusted.

Quoted 8 lines
Quoted 5 lines

But why? It's always in 00:1f.0 on real hardware. If the i915 driver wants to run under virtual machines, it should stop acting as if it knows what the whole machine looks like.

Paolo

If guest driver can be fixed that seems ideal. I don't know how it works but presumably you guys do?

Paolo prefer we need to fix this in the driver like:

"

Quoted 16 lines
Quoted 6 lines
Quoted 2 lines

The right way could be to make QEMU add a vendor-specific capability to the video device. The driver can probe for that capability before

Do you mean we can pick two unused offsets in the configuration space of the video device as a vendor-specific capability to hold the vendor/device ids of the PCH?

Yes, either that or add a new capability (which lets you choose the offsets more freely).

If the IGD driver needs config space fields of the MCH, those fields could also be mirrored in the new capability. QEMU would forward them automatically.

It could even be a new BAR, which gives even more freedom to allocate the fields.

Quoted 8 lines
Quoted 4 lines

"

Thanks
Tiejun

Adding a vendor-specific capability or BAR
in an existing device is painful - hard to find free space for it.

Yes, this is a potential risk as well since we can't guarantee current free space is always valid for ever.

Quoted 5 lines

We could add a dummy device in PCI or ACPI, but driver should really look for it using device/vendor id, not at a specific address.
What exactly is it that the driver wants to know?

The i915 driver need to use the vendor/device ids to get what pch type is running, then go different paths.

Thanks
Tiejun

#67 lore raw

Il 25/06/2014 11:21, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 3 lines

Adding a vendor-specific capability or BAR
in an existing device is painful - hard to find
free space for it.

Yes, this is a potential risk as well since we can't guarantee current free space is always valid for ever.

For past devices, we know which BARs they use. For future devices, it would be nice if the PCH/MCH backdoor was specified so that we know they will leave a free BAR for virtualization.

Paolo

#68 lore raw
Quoted 5 lines · Paolo Bonzini

Il 25/06/2014 11:21, Chen, Tiejun ha scritto:

Quoted 4 lines
Quoted 3 lines

Adding a vendor-specific capability or BAR
in an existing device is painful - hard to find
free space for it.

Quoted 7 lines
Quoted 2 lines

Yes, this is a potential risk as well since we can't guarantee current free space is always valid for ever.

For past devices, we know which BARs they use. For future devices, it would be nice if the PCH/MCH backdoor was specified so that we know they will leave a free BAR for virtualization.

Now I'm a bit confused about BAR here.

You're saying we will reserve a free BAR to address those information to expose to guest, but which device does this free BAR belong to? The video device? Or PCH/MCH?

Thanks
Tiejun

#69 lore raw

Il 25/06/2014 11:50, Chen, Tiejun ha scritto:

Quoted 11 lines
Quoted 5 lines

For past devices, we know which BARs they use. For future devices, it would be nice if the PCH/MCH backdoor was specified so that we know they will leave a free BAR for virtualization.

Now I'm a bit confused about BAR here.

You're saying we will reserve a free BAR to address those information to expose to guest, but which device does this free BAR belong to? The video device? Or PCH/MCH?

The video device. If the host device does not have the BAR (which will be the common case), QEMU can emulate it like this:

- offsets 0x0000..0x0fff map to configuration space of the host MCH

- offsets 0x1000..0x1fff map to configuration space of the host PCH

Of course this is only limited to offsets that are needed by the driver.

Paolo

#70 lore raw
Quoted 16 lines · Paolo Bonzini

Il 25/06/2014 11:50, Chen, Tiejun ha scritto:

Quoted 11 lines
Quoted 5 lines

For past devices, we know which BARs they use. For future devices, it would be nice if the PCH/MCH backdoor was specified so that we know they will leave a free BAR for virtualization.

Now I'm a bit confused about BAR here.

You're saying we will reserve a free BAR to address those information to expose to guest, but which device does this free BAR belong to? The video device? Or PCH/MCH?

The video device. If the host device does not have the BAR (which will be the common case), QEMU can emulate it like this:

Quoted 7 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

- offsets 0x1000..0x1fff map to configuration space of the host PCH

Of course this is only limited to offsets that are needed by the driver.

Paolo

Ow.
If you need hacks like this, describe this in ACPI. But I really hope not.

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#71 lore raw
In reply to Paolo Bonzini
Quoted 7 lines · Paolo Bonzini

Il 25/06/2014 11:50, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 5 lines

For past devices, we know which BARs they use. For future devices, it would be nice if the PCH/MCH backdoor was specified so that we know they will leave a free BAR for virtualization.

Quoted 8 lines
Quoted 5 lines

Now I'm a bit confused about BAR here.

You're saying we will reserve a free BAR to address those information to expose to guest, but which device does this free BAR belong to? The video device? Or PCH/MCH?

The video device. If the host device does not have the BAR (which will be the common case), QEMU can emulate it like this:

According to some feedback, neither we have any unused PCI unused config offset, nor BAR.

Quoted 3 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device? but will this overlap? Every PCIe device already have a 4K config space, right? So we should extend these two ranges:

0x0000..0x0fff: the standard PCIe config space in the video device 0x1000..0x1fff: map to configuration of the real host bridge 0x2000..0x2fff: map to configuration of the real ISA bridge

Right?

But as you know, we just need to expose a little config space from the real host bridge and the real ISA bridge, so this may be waste with 8K.

Thanks
Tiejun

Quoted 7 lines

- offsets 0x1000..0x1fff map to configuration space of the host PCH

Of course this is only limited to offsets that are needed by the driver.

Paolo

#72 lore raw

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Paolo

#73 lore raw
Quoted 6 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 5 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Quoted 6 lines
Quoted 1 line

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Paolo

I think v5 goes a bit overboard and overrides too many registers, driver likely needs much less.

But IMHO retro-fitting this into PIIX is where the problem is. We could invent 1000 ways to do this, all of varying levels of ugliness.

But why don't we start by more or less cleanly emulating what the driver needs? If we start with Q35 - it shouldn't be hard to tweak it's MCH to add the necessary config space, right?

I know xen doesn't support q35 now but it's opensource :)

I think that's a good step 1. We can do PV hacks on top if we decide they aren't too painful.

Signature · 1 line
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#74 lore raw

Il 26/06/2014 13:26, Michael S. Tsirkin ha scritto:

Quoted 21 lines · Paolo Bonzini
Quoted 6 lines

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 5 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Quoted 6 lines
Quoted 1 line

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Paolo

I think v5 goes a bit overboard and overrides too many registers, driver likely needs much less.

But IMHO retro-fitting this into PIIX is where the problem is. We could invent 1000 ways to do this, all of varying levels of ugliness.

Quoted 8 lines

But why don't we start by more or less cleanly emulating what the driver needs? If we start with Q35 - it shouldn't be hard to tweak it's MCH to add the necessary config space, right?

I know xen doesn't support q35 now but it's opensource :)

I think that's a good step 1. We can do PV hacks on top if we decide they aren't too painful.

I don't think it's a PV hack. It should be this way in real hardware too (not exactly _this_ hack, but at least no improper relationship among IGD/MCH/PCH).

Once you add nested virtualization and nested device assignment to the mix, hacking subsystem IDs simply does not scale.

Paolo

#75 lore raw
Quoted 26 lines · Paolo Bonzini

Il 26/06/2014 13:26, Michael S. Tsirkin ha scritto:

Quoted 25 lines · Paolo Bonzini
Quoted 6 lines

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 5 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Quoted 6 lines
Quoted 1 line

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Paolo

I think v5 goes a bit overboard and overrides too many registers, driver likely needs much less.

But IMHO retro-fitting this into PIIX is where the problem is. We could invent 1000 ways to do this, all of varying levels of ugliness.

But why don't we start by more or less cleanly emulating what the driver needs? If we start with Q35 - it shouldn't be hard to tweak it's MCH to add the necessary config space, right?

Quoted 6 lines
Quoted 4 lines

I know xen doesn't support q35 now but it's opensource :)

I think that's a good step 1. We can do PV hacks on top if we decide they aren't too painful.

I don't think it's a PV hack. It should be this way in real hardware too

But it isn't.

Quoted 2 lines

(not exactly _this_ hack, but at least no improper relationship among IGD/MCH/PCH).

Well that dependency between devices is common for embedded hardware, and this is what we have here.

Quoted 4 lines

Once you add nested virtualization and nested device assignment to the mix, hacking subsystem IDs simply does not scale.

Paolo

I'm not talking about subsystem id either, I'm talking about closely emulating the physical system that driver expects. In particular this definitely means not starting with PIIX :)

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#76 lore raw

Il 26/06/2014 13:36, Michael S. Tsirkin ha scritto:

Quoted 2 lines
Quoted 1 line

It should be this way in real hardware too

But it isn't.

That's why I mentioned that this hack should become architecturally specified (since it can work on real hardware too) with QEMU doing the emulation for current-generation devices.

Quoted 5 lines
Quoted 2 lines

(not exactly _this_ hack, but at least no improper relationship among IGD/MCH/PCH).

Well that dependency between devices is common for embedded hardware, and this is what we have here.

Sure, but then you should put MCH/PCH/IGD in the same IOMMU group, which basically means forgetting about IGD assignment.

Paolo

#77 lore raw
Quoted 6 lines · Paolo Bonzini

Il 26/06/2014 13:36, Michael S. Tsirkin ha scritto:

Quoted 2 lines
Quoted 1 line

It should be this way in real hardware too

But it isn't.

That's why I mentioned that this hack should become architecturally specified (since it can work on real hardware too)

Someone will have to implement it on real hardware first :) As long as no one does it's really PV.
I have no problem with PV as such, however
1. let's try to make it look less like a one-off hack
2. let's start with proper emulation, pv as step 2

Quoted 6 lines

with QEMU doing the
emulation for current-generation devices.

Quoted 3 lines
Quoted 2 lines

(not exactly _this_ hack, but at least no improper relationship among IGD/MCH/PCH).

Quoted 7 lines
Quoted 2 lines

Well that dependency between devices is common for embedded hardware, and this is what we have here.

Sure, but then you should put MCH/PCH/IGD in the same IOMMU group, which basically means forgetting about IGD assignment.

Paolo

I don't see why. We emulate parts of devices (e.g. BARs), ISA bridge/MCH is just such part of device that we emulate.

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#78 lore raw
In reply to Paolo Bonzini
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen. So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method. So when xen work on q35 PCIe machine, we can walk this way.

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

#79 lore raw
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation. Isn't this possible with an mch chipset?

Quoted 4 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 4 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a proper BAR, why didn't they?

Quoted 2 lines

So when xen work on
q35 PCIe machine, we can walk this way.

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing devices, without new capability IDs.

Quoted 6 lines

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

#80 lore raw
Quoted 20 lines · Michael S. Tsirkin
Quoted 19 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

Quoted 7 lines
Quoted 2 lines

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case. Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 10 lines
Quoted 6 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.

But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 8 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

Quoted 7 lines

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

We already have no any free BAR as we mentioned previously.

Quoted 7 lines
Quoted 4 lines

So when xen work on
q35 PCIe machine, we can walk this way.

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

Quoted 11 lines

devices, without new capability IDs.

Quoted 6 lines

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

#81 lore raw
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

What's stopping you?

Quoted 11 lines
Quoted 10 lines
Quoted 6 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.
This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host. Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 8 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

Quoted 7 lines

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.
Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 10 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

Quoted 6 lines

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Quoted 5 lines
Quoted 5 lines
Quoted 4 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 11 lines
Quoted 11 lines

devices, without new capability IDs.

Quoted 6 lines

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

#82 lore raw
Quoted 48 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

Quoted 6 lines

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.

+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev) +{
+ struct PCIDevice *dev;
+
+ char rid;
+
+ /* We havt to use a simple PCI device to fake this ISA bridge
+ * to avoid making some confusion to BIOS and ACPI.
+ */
+ dev = pci_create(bus, PCI_DEVFN(0x1f, 0), "pseudo-intel-pch-isa-bridge");
+
+ qdev_init_nofail(&dev->qdev);
+
+ pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+ pci_config_set_device_id(dev->config, hdev->device_id);
+
+ xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+ pci_config_set_revision(dev->config, rid);
+
+ XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+ return 0;
+}

Quoted 6 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

We just try to write *one* register we already confirm this is safe enough. Other register are read-only.

Quoted 7 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()

So shouldn't we already expose these information via sysfs?

Quoted 15 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 10 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

Quoted 8 lines
Quoted 6 lines

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

Quoted 35 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 11 lines
Quoted 11 lines

devices, without new capability IDs.

Quoted 6 lines

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

#83 lore raw
Quoted 51 lines · Tiejun
Quoted 50 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 8 lines
Quoted 4 lines
Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

Quoted 2 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

        /*
         * The reason to probe ISA bridge instead of Dev31:Fun0 is to
         * make graphics device passthrough work easy for VMM, that only
         * need to expose ISA bridge to let driver know the real hardware
         * underneath. This is a requirement from virtualization team.
         *
         * In some virtualized environments (e.g. XEN), there is irrelevant
         * ISA bridge in the system. To work reliably, we should scan trhough
         * all the ISA bridge devices and check for the first match, instead
         * of only checking the first one.
         */
        while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                        unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                        dev_priv->pch_id = id;

                        if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_IBX;

etc

Quoted 8 lines
Quoted 6 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

Quoted 1 line

Other register are read-only.

Doesn't matter, need to document these as well.

Quoted 41 lines
Quoted 7 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

Quoted 8 lines
	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

Quoted 20 lines
Quoted 20 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 35 lines
Quoted 35 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 11 lines
Quoted 11 lines

devices, without new capability IDs.

Quoted 6 lines

Anthony,

Any comments to address this in xen case?

Thanks
Tiejun

#84 lore raw
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

         /*
          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
          * make graphics device passthrough work easy for VMM, that only
          * need to expose ISA bridge to let driver know the real hardware
          * underneath. This is a requirement from virtualization team.
          *
          * In some virtualized environments (e.g. XEN), there is irrelevant
          * ISA bridge in the system. To work reliably, we should scan trhough
          * all the ISA bridge devices and check for the first match, instead
          * of only checking the first one.
          */
         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                         dev_priv->pch_id = id;

                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

- while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+ pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+ if (pch) {

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

Quoted 9 lines
Quoted 9 lines
Quoted 8 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#85 lore raw

Il 30/06/2014 12:20, Chen, Tiejun ha scritto:

Quoted 7 lines

I already post this to mainline to change as follows:

(quoted diff) +2 -1
-    while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+    pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+    if (pch) {
Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

Fair enough, but that means that, when using IGD, Q35 will have to move the ISA bridge off 1f.0.

To me it seems fairly clear that as things stand IGD is not virtualizable without PV support. We're beating a dead horse.

Paolo

#86 lore raw
Quoted 16 lines · Paolo Bonzini

Il 30/06/2014 12:20, Chen, Tiejun ha scritto:

Quoted 7 lines

I already post this to mainline to change as follows:

(quoted diff) +2 -1
-    while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+    pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+    if (pch) {
Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

Quoted 7 lines

Fair enough, but that means that, when using IGD, Q35 will have to move the ISA bridge off 1f.0.

To me it seems fairly clear that as things stand IGD is not virtualizable without PV support. We're beating a dead horse.

Paolo

It seems virtualizeable without PV. Virtualizing it just requires emulating a chipset that's closer to what the driver expects, which seems to be more effort than Tiejun is prepared to put in.

Signature · 1 line
MST
#87 lore raw
In reply to Chen, Tiejun
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

        /*
         * The reason to probe ISA bridge instead of Dev31:Fun0 is to
         * make graphics device passthrough work easy for VMM, that only
         * need to expose ISA bridge to let driver know the real hardware
         * underneath. This is a requirement from virtualization team.
         *
         * In some virtualized environments (e.g. XEN), there is irrelevant
         * ISA bridge in the system. To work reliably, we should scan trhough
         * all the ISA bridge devices and check for the first match, instead
         * of only checking the first one.
         */
        while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                        unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                        dev_priv->pch_id = id;

                        if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 160 lines
Quoted 9 lines
Quoted 9 lines
Quoted 8 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#88 lore raw
Quoted 180 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

         /*
          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
          * make graphics device passthrough work easy for VMM, that only
          * need to expose ISA bridge to let driver know the real hardware
          * underneath. This is a requirement from virtualization team.
          *
          * In some virtualized environments (e.g. XEN), there is irrelevant
          * ISA bridge in the system. To work reliably, we should scan trhough
          * all the ISA bridge devices and check for the first match, instead
          * of only checking the first one.
          */
         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                         dev_priv->pch_id = id;

                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

Quoted 8 lines

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#89 lore raw
Quoted 190 lines · Tiejun
Quoted 180 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

        /*
         * The reason to probe ISA bridge instead of Dev31:Fun0 is to
         * make graphics device passthrough work easy for VMM, that only
         * need to expose ISA bridge to let driver know the real hardware
         * underneath. This is a requirement from virtualization team.
         *
         * In some virtualized environments (e.g. XEN), there is irrelevant
         * ISA bridge in the system. To work reliably, we should scan trhough
         * all the ISA bridge devices and check for the first match, instead
         * of only checking the first one.
         */
        while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                        unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                        dev_priv->pch_id = id;

                        if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

Quoted 8 lines

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 5 lines

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Since we can't fix existing guests, I would say
get things working first, find a clean way for
new driver to work next.

Quoted 164 lines
Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#90 lore raw
Quoted 191 lines · Michael S. Tsirkin
Quoted 190 lines · Tiejun
Quoted 188 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

         /*
          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
          * make graphics device passthrough work easy for VMM, that only
          * need to expose ISA bridge to let driver know the real hardware
          * underneath. This is a requirement from virtualization team.
          *
          * In some virtualized environments (e.g. XEN), there is irrelevant
          * ISA bridge in the system. To work reliably, we should scan trhough
          * all the ISA bridge devices and check for the first match, instead
          * of only checking the first one.
          */
         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                         dev_priv->pch_id = id;

                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 7 lines
Quoted 5 lines

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Since we can't fix existing guests, I would say

This shouldn't be a fix existing guest, and this is why I can send this before you guys accept GFX passthrough for qemu ML.

I think you can re-read that patch head description. 1f.0 can work under all scenarios including qemu-xen-traditonal.

And this is also expected by native Linux organically, and especially Windows always use devfn to detect PCH, this is not like current Linux. So here I just sync this to make sense.

Unless you'd like to make Linux specific to this point.

Tiejun

Quoted 169 lines

get things working first, find a clean way for
new driver to work next.

Quoted 164 lines
Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#91 lore raw
Quoted 206 lines · Tiejun
Quoted 191 lines · Michael S. Tsirkin
Quoted 190 lines · Tiejun
Quoted 188 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

        /*
         * The reason to probe ISA bridge instead of Dev31:Fun0 is to
         * make graphics device passthrough work easy for VMM, that only
         * need to expose ISA bridge to let driver know the real hardware
         * underneath. This is a requirement from virtualization team.
         *
         * In some virtualized environments (e.g. XEN), there is irrelevant
         * ISA bridge in the system. To work reliably, we should scan trhough
         * all the ISA bridge devices and check for the first match, instead
         * of only checking the first one.
         */
        while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                        unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                        dev_priv->pch_id = id;

                        if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 7 lines
Quoted 5 lines

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Since we can't fix existing guests, I would say

This shouldn't be a fix existing guest, and this is why I can send this before you guys accept GFX passthrough for qemu ML.

I think you can re-read that patch head description. 1f.0 can work under all scenarios including qemu-xen-traditonal.

Quoted 7 lines

And this is also expected by native Linux organically, and especially Windows always use devfn to detect PCH, this is not like current Linux. So here I just sync this to make sense.

Unless you'd like to make Linux specific to this point.

Tiejun

Why don't both windows and linux drivers look device up by device and vendor id?
Same applies to MCH really.

Quoted 169 lines
Quoted 169 lines

get things working first, find a clean way for
new driver to work next.

Quoted 164 lines
Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#92 lore raw
Quoted 211 lines · Michael S. Tsirkin
Quoted 210 lines · Tiejun
Quoted 191 lines · Michael S. Tsirkin
Quoted 190 lines · Tiejun
Quoted 188 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing
MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

         /*
          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
          * make graphics device passthrough work easy for VMM, that only
          * need to expose ISA bridge to let driver know the real hardware
          * underneath. This is a requirement from virtualization team.
          *
          * In some virtualized environments (e.g. XEN), there is irrelevant
          * ISA bridge in the system. To work reliably, we should scan trhough
          * all the ISA bridge devices and check for the first match, instead
          * of only checking the first one.
          */
         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                         dev_priv->pch_id = id;

                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 7 lines
Quoted 5 lines

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Since we can't fix existing guests, I would say

This shouldn't be a fix existing guest, and this is why I can send this before you guys accept GFX passthrough for qemu ML.

I think you can re-read that patch head description. 1f.0 can work under all scenarios including qemu-xen-traditonal.

And this is also expected by native Linux organically, and especially Windows always use devfn to detect PCH, this is not like current Linux. So here I just sync this to make sense.

Quoted 6 lines
Quoted 3 lines

Unless you'd like to make Linux specific to this point.

Tiejun

Why don't both windows and linux drivers look device up by device and vendor id?

Its easy to understand because the same video device can work under different PCH, but we need to do different initialization based on different PCH.

Thanks
Tiejun

Quoted 173 lines

Same applies to MCH really.

Quoted 169 lines
Quoted 169 lines

get things working first, find a clean way for
new driver to work next.

Quoted 164 lines
Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with others. To do this properly, we need to get one from PCI SIG group. To have this workable and consistently validated, this method shouldn't be virt specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#93 lore raw
Quoted 219 lines · Tiejun
Quoted 211 lines · Michael S. Tsirkin
Quoted 210 lines · Tiejun
Quoted 191 lines · Michael S. Tsirkin
Quoted 190 lines · Tiejun
Quoted 188 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin
Quoted 21 lines · Tiejun

On 2014/6/26 18:03, Paolo Bonzini wrote:
Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing
MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a
offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to
extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to
q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines
Quoted 7 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so
still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think. So it seems simple: create a dummy device that gets device and vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

        /*
         * The reason to probe ISA bridge instead of Dev31:Fun0 is to
         * make graphics device passthrough work easy for VMM, that only
         * need to expose ISA bridge to let driver know the real hardware
         * underneath. This is a requirement from virtualization team.
         *
         * In some virtualized environments (e.g. XEN), there is irrelevant
         * ISA bridge in the system. To work reliably, we should scan trhough
         * all the ISA bridge devices and check for the first match, instead
         * of only checking the first one.
         */
        while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                        unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                        dev_priv->pch_id = id;

                        if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 7 lines
Quoted 5 lines

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Since we can't fix existing guests, I would say

This shouldn't be a fix existing guest, and this is why I can send this before you guys accept GFX passthrough for qemu ML.

I think you can re-read that patch head description. 1f.0 can work under all scenarios including qemu-xen-traditonal.

And this is also expected by native Linux organically, and especially Windows always use devfn to detect PCH, this is not like current Linux. So here I just sync this to make sense.

Quoted 6 lines
Quoted 3 lines

Unless you'd like to make Linux specific to this point.

Tiejun

Why don't both windows and linux drivers look device up by device and vendor id?

Quoted 6 lines

Its easy to understand because the same video device can work under different PCH, but we need to do different initialization based on different PCH.

Thanks
Tiejun

Right so why don't they look up the PCH by device and vendor id? For example, on linux use pci_get_device to iterate over all intel devices.
I'm sure windows has a similar API as well.

This isn't a suggestion to make the change in guests right now! Just a question.

Quoted 173 lines
Quoted 173 lines

Same applies to MCH really.

Quoted 169 lines
Quoted 169 lines

get things working first, find a clean way for
new driver to work next.

Quoted 164 lines
Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them directly and not through xen wrappers, this way you can open the files RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs, though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this bridge, not a pass-through device. Long term, the right thing to do is likely to extend host driver and expose the necessary information in sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines
Quoted 6 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with
others. To do this properly, we need to get one from PCI SIG group. To have
this workable and consistently validated, this method shouldn't be virt
specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys? I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Quoted 2 lines

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines
Quoted 4 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#94 lore raw
Quoted 224 lines · Michael S. Tsirkin
Quoted 223 lines · Tiejun
Quoted 211 lines · Michael S. Tsirkin
Quoted 210 lines · Tiejun
Quoted 191 lines · Michael S. Tsirkin
Quoted 190 lines · Tiejun
Quoted 188 lines · Michael S. Tsirkin
Quoted 156 lines · Tiejun
Quoted 55 lines · Michael S. Tsirkin
Quoted 54 lines · Tiejun
Quoted 53 lines · Michael S. Tsirkin
Quoted 24 lines · Tiejun
Quoted 23 lines · Michael S. Tsirkin

On Mon, Jun 30, 2014 at 10:51:49AM +0800, Chen, Tiejun wrote:
On 2014/6/26 18:03, Paolo Bonzini wrote:
Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing
MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a
offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to
extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to
q35 as a PCIe machine of xen.

Quoted 6 lines
Quoted 4 lines

That seems like a weak motivation. I don't see a need to get something
merged upstream in a short time: this seems sure to miss 2.1,
so you have the time to make it architecturally sound.
"Making existing guests work" would be a better motivation.

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this? That will just give everyone more long term benefits.

If instead we create a hack that does not resemble any existing hardware even remotely, what's the chance that it will not break with any future guest modification?

Quoted 4 lines
Quoted 1 line

Isn't this possible with an mch chipset?

If you're saying q35, I mean AFAIK we have no any plan to migrate to this MCH in xen case.

q35 or a newer chipset that's closer to what guests expect.

Quoted 2 lines

Additionally, I think I should follow this feature after q35 can work for xen scenario.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line

What's stopping you?

I mean if you want create an new machine based on q35, actually this is equal to start making xen to migrate to q35 now. Right? I can't image how much effort should be done.

I don't see why you don't try. Sounds like a more robust solution to me.

As I think this is another requirement to us. I'm not sure if I have enough time to touch this currently.

Quoted 84 lines
Quoted 3 lines

So this is a reason why I'm saying I'd like to follow this feature after q35 can work with xen completely.

Then we'll end up with more configurations to support, and to what end?

Quoted 45 lines
Quoted 20 lines
Quoted 12 lines
Quoted 11 lines

So could we do this step by step:

#1 phase: We just cover current qemu-xen implementation based on i44fx, so
still provide that pseudo ISA bridge at 00:1f.0 as we already did.

By the way there is no reason to put it at 00:1f.0 specifically I think.
So it seems simple: create a dummy device that gets device and
vendor id as properties. If you really like, add an option to get values

Quoted 7 lines

Yes, this is just what we did in [Xen-devel] [v5][PATCH 2/5] xen, gfx
passthrough: create pseudo intel isa bridge. There, we fake this device just at 00:1f.0.
But you guys don't like this, and shouldn't this be just this point we discussing now?

If you guys agree that , everything is fine.

Quoted 7 lines

Actually, this isn't what you did.
Don't tie it to xen, and don't tie it to 1f.
Just make it a simple stub pci device.
Whoever wants it, creates it.

The thing I worry about, is the chance this will break going forward. So you created a system with 2 isa bridges.

I don't set class type to claim this is an ISA bridge, just a normal PCI device.
+static int create_pseudo_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)

(quoted diff) +9 -0
+{
+    struct PCIDevice *dev;
+
+    char rid;
+
+    /* We havt to use a simple PCI device to fake this ISA bridge
+     * to avoid making some confusion to BIOS and ACPI.
+     */
+    dev = pci_create(bus, PCI_DEVFN(0x1f, 0),

"pseudo-intel-pch-isa-bridge");

(quoted diff) +3 -0
+
+    qdev_init_nofail(&dev->qdev);
+

Review

Quoted 10 lines
(quoted diff) +10 -0
+    pci_config_set_vendor_id(dev->config, hdev->vendor_id);
+    pci_config_set_device_id(dev->config, hdev->device_id);
+
+    xen_host_pci_get_block(hdev, PCI_REVISION_ID, (uint8_t *)&rid, 1);
+
+    pci_config_set_revision(dev->config, rid);
+
+    XEN_PT_LOG(dev, "The pseudo Intel PCH ISA bridge created.\n");
+    return 0;
+}

Then I don't see how it's supposed to work.
Doesn't i915 look for an isa bridge?

         /*
          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
          * make graphics device passthrough work easy for VMM, that only
          * need to expose ISA bridge to let driver know the real hardware
          * underneath. This is a requirement from virtualization team.
          *
          * In some virtualized environments (e.g. XEN), there is irrelevant
          * ISA bridge in the system. To work reliably, we should scan trhough
          * all the ISA bridge devices and check for the first match, instead
          * of only checking the first one.
          */
         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
                         dev_priv->pch_id = id;

                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
                                 dev_priv->pch_type = PCH_IBX;
Quoted 2 lines

etc

I already post this to mainline to change as follows:

Review

Quoted 3 lines
(quoted diff) +2 -1
-	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
+	pch = pci_get_bus_and_slot(0, PCI_DEVFN(0x1f, 0));
+	if (pch) {

I see - responded on that mail - but I thought the point is to make existing guests run? In fact you said so explicitly.

Quoted 7 lines

Please refer to this,

[RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type

Linux Native guys would like to accept this. And actually Windows always use devfn to detect this.

In fact I see this:

linux 2.6.35-3.9 probes the 1st IA bridge

no idea how would you fix this.
try changing default class for the main bridge?

linux 3.10 probes all ISA bridges

requires your stub to be the isa bridge?

I don't see why are driver guys so willing to do crazy things. They want to match specific device/vendor id pairs, why don't they do just that? Why poke at class, random slot numbers etc etc?

Quoted 7 lines
Quoted 5 lines

AFAIK what they did is from our previous incorrect requirement as I understand. So we need to correct this.

Thanks
Tiejun

Since we can't fix existing guests, I would say

This shouldn't be a fix existing guest, and this is why I can send this before you guys accept GFX passthrough for qemu ML.

I think you can re-read that patch head description. 1f.0 can work under all scenarios including qemu-xen-traditonal.

And this is also expected by native Linux organically, and especially Windows always use devfn to detect PCH, this is not like current Linux. So here I just sync this to make sense.

Quoted 6 lines
Quoted 3 lines

Unless you'd like to make Linux specific to this point.

Tiejun

Why don't both windows and linux drivers look device up by device and vendor id?

Its easy to understand because the same video device can work under different PCH, but we need to do different initialization based on different PCH.

Quoted 6 lines
Quoted 2 lines

Thanks
Tiejun

Right so why don't they look up the PCH by device and vendor id? For example, on linux use pci_get_device to iterate over all intel devices.

I think this will definitely work as long as we still have a PCI device represented with a real vendor/device ids.

Quoted 1 line

I'm sure windows has a similar API as well.

I guess this is true as well but firstly I have to further ask native team guys if both native Linux and Windows are like this way to avoid we're missing something.

Thanks
Tiejun

Quoted 180 lines

This isn't a suggestion to make the change in guests right now! Just a question.

Quoted 173 lines
Quoted 173 lines

Same applies to MCH really.

Quoted 169 lines
Quoted 169 lines

get things working first, find a clean way for
new driver to work next.

Quoted 164 lines
Quoted 164 lines
Quoted 163 lines
Quoted 12 lines
Quoted 12 lines
Quoted 11 lines

This is already not something that exists on real hardware. So it might break some guests that will get confused. Maybe we are lucky and most guests see an unfamiliar device and ignore it. It seems believable.

But your MCH hack overrides registers in the pci host.

Quoted 7 lines
Quoted 1 line

We just try to write *one* register we already confirm this is safe enough.

This should go in code in form of comments:
document what this register does on 440fx
and why it's safe to override.
We don't see what you
confirmed off-line.

That offset is one specific to IGD usage, not for i440fx common. This is why we need to expose something in the host bridge. They're just introduced to support IGD.

Quoted 4 lines
Quoted 2 lines

Other register are read-only.

Doesn't matter, need to document these as well.

I think everything are covered in igd_pci_write()/igd_pci_write().

Quoted 49 lines
Quoted 49 lines
Quoted 8 lines

Are we lucky and there's nothing in these registers of interest to guests? This seems much more fragile. So please poke at the spec, and compile the list of registers you want to touch, figure out why they are safe to override, and put this all in code comments.

And the same thing that applies to the isa bridge

We just expose its own vendor/device ids here. We don't access to change anything in the isa bridge.

Quoted 21 lines

applies here too. It should work without QEMU touching hosts' hardware.

Quoted 16 lines
Quoted 15 lines

from sysfs: device and vendor id are world readable, so just get them
directly and not through xen wrappers, this way you can open the files
RO and not RW.
You seem to poke at revision as well, I don't see
driver looking at that - strictly necessary?
If yes please patch host kernel to expose that info in sysfs,
though we can fall back on pci config if not there.

MCH (bridge_dev) hacks in i915 are nastier.
To clean them up, we really have to have an explicit driver for this
bridge, not a pass-through device. Long term, the right thing to do is
likely to extend host driver and expose the necessary information in
sysfs on host kernel.

Quoted 7 lines
Quoted 3 lines

I'm a bit confused. Any sysfs should be filled by the associated PCIe device, shouldn't it? So qemu still need to emulate this PCIe device firstly, then set properties into sysfs.

I am talking about getting host properties into qemu. You don't want to give qemu R/W root access to host sysfs system of the root bridge, that's not secure.

igd_pci_read()

	|
	+ xen_host_pci_get_block()
		|
		+ xen_host_pci_config_read(()
			|
			+  pread()
Quoted 3 lines
Quoted 1 line

So shouldn't we already expose these information via sysfs?

That's poking at sysfs of a real device, and after opening it RW.

I don't think we can really write anything to those read-only sysfs interface even we open them as RW.

Tiejun

Quoted 74 lines
Quoted 21 lines
Quoted 21 lines

Avoiding read only access to filesystem is a good idea too, so it should be possible to pass all parameters in as
device properties, and let whoever starts qemu
figure out what are reasonable values.

Quoted 15 lines
Quoted 9 lines

#2 phase: Now, we will choose a capability ID that won't be conflicting with
others. To do this properly, we need to get one from PCI SIG group. To have
this workable and consistently validated, this method shouldn't be virt
specific. Then native driver should use the same method.

You mean you will be able to talk sense into hardware guys?
I doubt that. If they could be convinced to make e.g. i915 base a

We're negotiating this, so this is just our long term solution we figure out currently.

Quoted 1 line

proper BAR, why didn't they?

Quoted 7 lines
Quoted 3 lines
Quoted 1 line

We already have no any free BAR as we mentioned previously.

I thought you were talking about modifying hardware?

Yes.

Tiejun

And they can't figure out how to stick extra info in an existing BAR? Oh well, that's hardware for you.

Quoted 27 lines
Quoted 27 lines
Quoted 6 lines
Quoted 6 lines

So when xen work on
q35 PCIe machine, we can walk this way.

Quoted 8 lines
Quoted 2 lines

If you are emulating MCH anyway, pick one that is close
to what i915 driver expects. It would then work with existing

Looks you guys prefer we create a new MCH anyway, right? But is it necessary to create a new based on i440fx just for a little change?

Thanks
Tiejun

You can inherit it. Maybe you are lucky and this happens to work without conflicting with whatever other guests want to do. But if you ask me, you are really just piling up hacks. If some guest does not work on i440, you should just work on emulating whatever it does work on.
That would have real value.

Quoted 5 lines
Quoted 5 lines

devices, without new capability IDs.

Anthony,

Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
Quoted 6 lines

Any comments to address this in xen case?

Thanks
Tiejun

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

#95 lore raw
In reply to Michael S. Tsirkin
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

#96 lore raw
Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

Quoted 11 lines

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2014.0.4592 / Virus Database: 3986/7769 - Release Date: 06/30/14

Signature · 1 line
Ross Philipson
#97 lore raw
Quoted 46 lines · Ross Philipson
Quoted 36 lines · Stefano Stabellini
Quoted 35 lines · Michael S. Tsirkin
Quoted 34 lines · Tiejun
Quoted 32 lines · Michael S. Tsirkin
Quoted 18 lines · Tiejun
Quoted 12 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 7 lines
Quoted 5 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

As I mentioned previously, the IGD guy told me we have no any unused a
offset or BAR in the config space.

Quoted 7 lines

And guy who are responsible for the native driver seems not be accept to
extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to
q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something
merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

Quoted 8 lines

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

So do this mean currently we still can't go q35?

Thanks
Tiejun

#98 lore raw
In reply to Ross Philipson
Quoted 41 lines · Ross Philipson
Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

Quoted 7 lines

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

It's not hard to try it out with kvm (you just need to remember to use ide with
q35: ahci is the default there). I did, and windows did not ask me to re-activate.

The detailed info is not hard to find:
http://en.wikipedia.org/wiki/Microsoft_Product_Activation
links to:
http://technet.microsoft.com/en-us/library/bb457054.aspx

1
Display Adapter
00010 (5)
2
SCSI Adapter
00011 (5)
3
IDE Adapter
0011 (4)
4
Network Adapter MAC Address
1001011000 (10)
5
RAM Amount Range (i.e. 0-64mb, 64-128mb, etc)
101 (3)
6
Processor Type
011 (3)
7
Processor Serial Number
000000 (6)
8
Hard Drive Device
1101100 (7)
9
Hard Drive Volume Serial Number
1001000001 (10)
10
CD—ROM / CD-RW / DVD-ROM
010111 (6)
-
"Dockable"
0 (1)
-
Hardware Hash version (version of algorithm used)
001 (3)

So no, chipset version won't cause re-activation.

Quoted 15 lines
Quoted 11 lines

_______________________________________________
Xen-devel mailing list
[email protected]
http://lists.xen.org/xen-devel

-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2014.0.4592 / Virus Database: 3986/7769 - Release Date: 06/30/14

Signature · 1 line
Ross Philipson
#99 lore raw
Quoted 97 lines · Michael S. Tsirkin
Quoted 41 lines · Ross Philipson
Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

Quoted 7 lines

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

It's not hard to try it out with kvm (you just need to remember to use ide with
q35: ahci is the default there). I did, and windows did not ask me to re-activate.

The detailed info is not hard to find:
http://en.wikipedia.org/wiki/Microsoft_Product_Activation
links to:
http://technet.microsoft.com/en-us/library/bb457054.aspx

1
Display Adapter
00010 (5)
2
SCSI Adapter
00011 (5)
3
IDE Adapter
0011 (4)
4
Network Adapter MAC Address
1001011000 (10)
5
RAM Amount Range (i.e. 0-64mb, 64-128mb, etc)
101 (3)
6
Processor Type
011 (3)
7
Processor Serial Number
000000 (6)
8
Hard Drive Device
1101100 (7)
9
Hard Drive Volume Serial Number
1001000001 (10)
10
CD—ROM / CD-RW / DVD-ROM
010111 (6)
-
"Dockable"
0 (1)
-
Hardware Hash version (version of algorithm used)
001 (3)

Quoted 1 line

So no, chipset version won't cause re-activation.

The page you linked is about Windows XP. Newer Windows versions have stricter activation rules. I don't think that moving existing VM images from piix to q35 could be done without extensive testing of all the major existing operating system images. I certainly wouldn't rely on a wikipedia page for this.

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

#100 lore raw
Quoted 98 lines · Stefano Stabellini
Quoted 97 lines · Michael S. Tsirkin
Quoted 41 lines · Ross Philipson
Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

Quoted 7 lines

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

It's not hard to try it out with kvm (you just need to remember to use ide with
q35: ahci is the default there). I did, and windows did not ask me to re-activate.

The detailed info is not hard to find:
http://en.wikipedia.org/wiki/Microsoft_Product_Activation
links to:
http://technet.microsoft.com/en-us/library/bb457054.aspx

1
Display Adapter
00010 (5)
2
SCSI Adapter
00011 (5)
3
IDE Adapter
0011 (4)
4
Network Adapter MAC Address
1001011000 (10)
5
RAM Amount Range (i.e. 0-64mb, 64-128mb, etc)
101 (3)
6
Processor Type
011 (3)
7
Processor Serial Number
000000 (6)
8
Hard Drive Device
1101100 (7)
9
Hard Drive Volume Serial Number
1001000001 (10)
10
CD—ROM / CD-RW / DVD-ROM
010111 (6)
-
"Dockable"
0 (1)
-
Hardware Hash version (version of algorithm used)
001 (3)

Quoted 7 lines
Quoted 1 line

So no, chipset version won't cause re-activation.

The page you linked is about Windows XP. Newer Windows versions have stricter activation rules. I don't think that moving existing VM images from piix to q35 could be done without extensive testing of all the major existing operating system images. I certainly wouldn't rely on a wikipedia page for this.

So do the testing then.
You don't even need to do anything on xen - run them all on kvm. This testing will benefit everyone.

BTW is there a chance that adding the ISA bridge or doing other tricks that Tiejun's patches do, will trigger windows activation? Looks like this logic can cut both ways.

Quoted 3 lines

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

If it's true that implementing igd passthrough on top of q35 is much cleaner architecturally, then I don't see why we should merge a stop-gap solution that we'll need to then support indefinitely.

We are talking about upstreaming functionality that xen already has, right? So there's no time to market concern, whoever wants a solution today has it. Why not do it in the cleanest possible way?

Signature · 1 line
MST
#101 lore raw
Quoted 107 lines · Michael S. Tsirkin
Quoted 98 lines · Stefano Stabellini
Quoted 97 lines · Michael S. Tsirkin
Quoted 41 lines · Ross Philipson
Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

Quoted 7 lines

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

It's not hard to try it out with kvm (you just need to remember to use ide with
q35: ahci is the default there). I did, and windows did not ask me to re-activate.

The detailed info is not hard to find:
http://en.wikipedia.org/wiki/Microsoft_Product_Activation
links to:
http://technet.microsoft.com/en-us/library/bb457054.aspx

1
Display Adapter
00010 (5)
2
SCSI Adapter
00011 (5)
3
IDE Adapter
0011 (4)
4
Network Adapter MAC Address
1001011000 (10)
5
RAM Amount Range (i.e. 0-64mb, 64-128mb, etc)
101 (3)
6
Processor Type
011 (3)
7
Processor Serial Number
000000 (6)
8
Hard Drive Device
1101100 (7)
9
Hard Drive Volume Serial Number
1001000001 (10)
10
CD—ROM / CD-RW / DVD-ROM
010111 (6)
-
"Dockable"
0 (1)
-
Hardware Hash version (version of algorithm used)
001 (3)

Quoted 7 lines
Quoted 1 line

So no, chipset version won't cause re-activation.

The page you linked is about Windows XP. Newer Windows versions have stricter activation rules. I don't think that moving existing VM images from piix to q35 could be done without extensive testing of all the major existing operating system images. I certainly wouldn't rely on a wikipedia page for this.

Quoted 7 lines

So do the testing then.
You don't even need to do anything on xen - run them all on kvm. This testing will benefit everyone.

BTW is there a chance that adding the ISA bridge or doing other tricks that Tiejun's patches do, will trigger windows activation? Looks like this logic can cut both ways.

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

Quoted 13 lines
Quoted 4 lines

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

If it's true that implementing igd passthrough on top of q35 is much cleaner architecturally, then I don't see why we should merge a stop-gap solution that we'll need to then support indefinitely.

We are talking about upstreaming functionality that xen already has, right? So there's no time to market concern, whoever wants a solution today has it. Why not do it in the cleanest possible way?

Signature · 1 line
Ross Philipson
#102 lore raw
Quoted 112 lines · Ross Philipson
Quoted 111 lines · Michael S. Tsirkin
Quoted 98 lines · Stefano Stabellini
Quoted 97 lines · Michael S. Tsirkin
Quoted 41 lines · Ross Philipson
Quoted 31 lines · Stefano Stabellini
Quoted 30 lines · Michael S. Tsirkin
Quoted 29 lines · Tiejun
Quoted 27 lines · Michael S. Tsirkin
Quoted 13 lines · Tiejun
Quoted 11 lines · Paolo Bonzini

Il 26/06/2014 11:18, Chen, Tiejun ha scritto:

Quoted 6 lines
Quoted 4 lines

- offsets 0x0000..0x0fff map to configuration space of the host MCH

Are you saying the config space in the video device?

No, I am saying in a new BAR, or at some magic offset of an existing MMIO BAR.

Quoted 8 lines

As I mentioned previously, the IGD guy told me we have no any unused a offset or BAR in the config space.

And guy who are responsible for the native driver seems not be accept to extend some magic offset of an existing MMIO BAR.

In addition I think in a short time its not possible to migrate i440fx to q35 as a PCIe machine of xen.

That seems like a weak motivation. I don't see a need to get something merged upstream in a short time: this seems sure to miss 2.1, so you have the time to make it architecturally sound. "Making existing guests work" would be a better motivation.

Quoted 8 lines
Quoted 5 lines
Quoted 1 line

Yes.

So focus on this then. Existing guests will probably work fine on a newer chipset - likely better than on i440fx. xen management tools need to do some work to support this?

Unfortunately existing Windows guests don't take well chipset changes. Windows might request a new activation.

Quoted 7 lines

That is a very good point. A while back I did a bunch of work to try to keep Windows activated between running an instance of Windows on bare metal and as a VM. There were numerous bits of hardware and firmware that went into the calculation as to whether Windows thought it was the same platform for activation purposes. Changing the chipset sounds like a likely candidate for inspection. Somewhere out there on the webs is a partial list of the things that are inspected - lost the URL.

It's not hard to try it out with kvm (you just need to remember to use ide with
q35: ahci is the default there). I did, and windows did not ask me to re-activate.

The detailed info is not hard to find:
http://en.wikipedia.org/wiki/Microsoft_Product_Activation
links to:
http://technet.microsoft.com/en-us/library/bb457054.aspx

1
Display Adapter
00010 (5)
2
SCSI Adapter
00011 (5)
3
IDE Adapter
0011 (4)
4
Network Adapter MAC Address
1001011000 (10)
5
RAM Amount Range (i.e. 0-64mb, 64-128mb, etc)
101 (3)
6
Processor Type
011 (3)
7
Processor Serial Number
000000 (6)
8
Hard Drive Device
1101100 (7)
9
Hard Drive Volume Serial Number
1001000001 (10)
10
CD—ROM / CD-RW / DVD-ROM
010111 (6)
-
"Dockable"
0 (1)
-
Hardware Hash version (version of algorithm used)
001 (3)

Quoted 7 lines
Quoted 1 line

So no, chipset version won't cause re-activation.

The page you linked is about Windows XP. Newer Windows versions have stricter activation rules. I don't think that moving existing VM images from piix to q35 could be done without extensive testing of all the major existing operating system images. I certainly wouldn't rely on a wikipedia page for this.

So do the testing then.
You don't even need to do anything on xen - run them all on kvm. This testing will benefit everyone.

Quoted 8 lines
Quoted 3 lines

BTW is there a chance that adding the ISA bridge or doing other tricks that Tiejun's patches do, will trigger windows activation? Looks like this logic can cut both ways.

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

What class does your ISA bridge device have?

Quoted 17 lines
Quoted 13 lines
Quoted 4 lines

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

If it's true that implementing igd passthrough on top of q35 is much cleaner architecturally, then I don't see why we should merge a stop-gap solution that we'll need to then support indefinitely.

We are talking about upstreaming functionality that xen already has, right? So there's no time to market concern, whoever wants a solution today has it. Why not do it in the cleanest possible way?

Signature · 1 line
Ross Philipson
#103 lore raw
Quoted 1 line · Michael S. Tsirkin

On Tue, Jul 01, 2014 at 01:39:04PM -0400, Ross Philipson wrote:

[snip]

Quoted 2 lines

What class does your ISA bridge device have?

#define PCI_CLASS_BRIDGE_ISA 0x0601

Quoted 24 lines
Quoted 10 lines
Quoted 10 lines
Quoted 5 lines

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

If it's true that implementing igd passthrough on top of q35 is much cleaner architecturally, then I don't see why we should merge a stop-gap solution that we'll need to then support indefinitely.

Quoted 8 lines
Quoted 4 lines

We are talking about upstreaming functionality that xen already has, right? So there's no time to market concern, whoever wants a solution today has it. Why not do it in the cleanest possible way?

--
Ross Philipson

-----
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Checked by AVG - www.avg.com
Version: 2014.0.4592 / Virus Database: 3986/7769 - Release Date: 06/30/14

Signature · 1 line
Ross Philipson
#104 lore raw
Quoted 9 lines · Ross Philipson
Quoted 1 line · Michael S. Tsirkin

On Tue, Jul 01, 2014 at 01:39:04PM -0400, Ross Philipson wrote:

[snip]

Quoted 2 lines

What class does your ISA bridge device have?

#define PCI_CLASS_BRIDGE_ISA 0x0601

Okay I guessed so. But IIRC Tiejun's suggesting giving it a different class. So we don't know what the effect will be on various guests without testing.

Quoted 28 lines
Quoted 24 lines
Quoted 10 lines
Quoted 10 lines
Quoted 5 lines

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

If it's true that implementing igd passthrough on top of q35 is much cleaner architecturally, then I don't see why we should merge a stop-gap solution that we'll need to then support indefinitely.

Quoted 8 lines
Quoted 4 lines

We are talking about upstreaming functionality that xen already has, right? So there's no time to market concern, whoever wants a solution today has it. Why not do it in the cleanest possible way?

--
Ross Philipson

-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2014.0.4592 / Virus Database: 3986/7769 - Release Date: 06/30/14

Signature · 1 line
Ross Philipson
#105 lore raw
Quoted 4 lines · Michael S. Tsirkin
Quoted 3 lines · Ross Philipson
Quoted 1 line · Michael S. Tsirkin

On Tue, Jul 01, 2014 at 01:39:04PM -0400, Ross Philipson wrote:

Quoted 8 lines
Quoted 6 lines

[snip]

Quoted 2 lines

What class does your ISA bridge device have?

#define PCI_CLASS_BRIDGE_ISA 0x0601

Okay I guessed so. But IIRC Tiejun's suggesting giving it a different

Organically we really use this class. But Paolo said this introduce two ISA bridges, then something will be confused. Sorry I can't find that quickly since we have so long discussion, so long email thread :(

Thanks
Tiejun

Quoted 34 lines

class. So we don't know what the effect will be on various guests without testing.

Quoted 28 lines
Quoted 16 lines
Quoted 16 lines
Quoted 14 lines
Quoted 5 lines

Also I don't like the idea of tying Tiejun's patch series, that covers a very narrow use case, to something as important and general purpose as upgrading chipset.

If it's true that implementing igd passthrough on top of q35 is much cleaner architecturally, then I don't see why we should merge a stop-gap solution that we'll need to then support indefinitely.

We are talking about upstreaming functionality that xen already has, right? So there's no time to market concern, whoever wants a solution today has it. Why not do it in the cleanest possible way?

Quoted 8 lines
Quoted 2 lines

--
Ross Philipson

-----
No virus found in this message.
Checked by AVG - www.avg.com
Version: 2014.0.4592 / Virus Database: 3986/7769 - Release Date: 06/30/14

--
Ross Philipson

#106 lore raw
In reply to Ross Philipson

Il 01/07/2014 19:39, Ross Philipson ha scritto:

Quoted 6 lines

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

The problem is not activation, the problem is that the patches are making assumptions on the driver and the firmware that might work today but are IMHO just not sane.

I would have no problem with a clean patchset that adds a new machine type and doesn't touch code in "-M pc", but it looks like mst disagrees.
Ultimately, if a patchset is too hacky for upstream, you can include
it in your downstream XenClient (and XenServer) QEMU branch. It happens.

Paolo

#107 lore raw
Quoted 8 lines · Paolo Bonzini

Il 01/07/2014 19:39, Ross Philipson ha scritto:

Quoted 6 lines

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

Quoted 8 lines

The problem is not activation, the problem is that the patches are making assumptions on the driver and the firmware that might work today but are IMHO just not sane.

I would have no problem with a clean patchset that adds a new machine type and doesn't touch code in "-M pc", but it looks like mst disagrees. Ultimately, if a patchset is too hacky for upstream, you can include it in your downstream XenClient (and XenServer) QEMU branch. It happens.

And then this discussion will come back again in a year when folks rebase and ask: Why hasn't this been done upstream.

Then the discussion resumes ..

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

2). Since we need the Southbridge magic addresses, we can expose
an bridge. [I think everybody agrees that we need to do that since 1) is no go).

3). What kind of bridge. We can do:

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

b2) We would need to use the Q35.
b2a). If we need Q35, that needs to be exposed in
for Xen guests. That means exposing the MMCONFIG and restructing the E820 to fit that in.
Problem:
- Migration is not working with Q35. (But for v1 you wouldn't migrate, however later hardware will surely have SR-IOV so we will need to migrate).

- There are no developers who have an OK from their management to focus on this. (Potential solution: Poke Intel management to see if they can get more developers on it)

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

#108 lore raw
Quoted 18 lines · Konrad Rzeszutek Wilk
Quoted 8 lines · Paolo Bonzini

Il 01/07/2014 19:39, Ross Philipson ha scritto:

Quoted 6 lines

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

Quoted 8 lines

The problem is not activation, the problem is that the patches are making assumptions on the driver and the firmware that might work today but are IMHO just not sane.

I would have no problem with a clean patchset that adds a new machine type and doesn't touch code in "-M pc", but it looks like mst disagrees. Ultimately, if a patchset is too hacky for upstream, you can include it in your downstream XenClient (and XenServer) QEMU branch. It happens.

Quoted 8 lines

And then this discussion will come back again in a year when folks rebase and ask: Why hasn't this been done upstream.

Then the discussion resumes ..

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

Before I answer could you clarify please:
by Southbridge do you mean the PCH at slot 1f or the MCH at slot 0 or both?

Quoted 46 lines

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

2). Since we need the Southbridge magic addresses, we can expose
an bridge. [I think everybody agrees that we need to do that since 1) is no go).

3). What kind of bridge. We can do:

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

b2) We would need to use the Q35.
b2a). If we need Q35, that needs to be exposed in
for Xen guests. That means exposing the MMCONFIG and restructing the E820 to fit that in.
Problem:
- Migration is not working with Q35. (But for v1 you wouldn't migrate, however later hardware will surely have SR-IOV so we will need to migrate).

- There are no developers who have an OK from their management to focus on this. (Potential solution: Poke Intel management to see if they can get more developers on it)

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

#109 lore raw
Quoted 22 lines · Michael S. Tsirkin
Quoted 21 lines · Konrad Rzeszutek Wilk
Quoted 8 lines · Paolo Bonzini

Il 01/07/2014 19:39, Ross Philipson ha scritto:

Quoted 6 lines

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

Quoted 8 lines

The problem is not activation, the problem is that the patches are making assumptions on the driver and the firmware that might work today but are IMHO just not sane.

I would have no problem with a clean patchset that adds a new machine type and doesn't touch code in "-M pc", but it looks like mst disagrees. Ultimately, if a patchset is too hacky for upstream, you can include it in your downstream XenClient (and XenServer) QEMU branch. It happens.

And then this discussion will come back again in a year when folks rebase and ask: Why hasn't this been done upstream.

Quoted 8 lines
Quoted 5 lines

Then the discussion resumes ..

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

Before I answer could you clarify please:
by Southbridge do you mean the PCH at slot 1f or the MCH at slot 0 or both?

MCH slot. We read/write from this (see intel_setup_mchbar) from couple of registers (0x44 and 0x48 if gen >= 4, otherwise 0x54). It is hard-coded in the i915_get_bridge_dev (see ec2a4c3fdc8e82fe82a25d800e85c1ea06b74372) as 0:0.0 BDF.

The PCH (does not matter where it sits) we only use the model:vendor id to figure out the pch_type (see intel_detect_pch).

I don't see why that model:vendor_id can't be exposed via checking the type of device:vendor_id of the IGD itself. CC-ing some Intel i915 authors.

So for the discussion here, when I say Southbridge I mean MCH.

Quoted 47 lines
Quoted 47 lines

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

2). Since we need the Southbridge magic addresses, we can expose
an bridge. [I think everybody agrees that we need to do that since 1) is no go).

3). What kind of bridge. We can do:

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

b2) We would need to use the Q35.
b2a). If we need Q35, that needs to be exposed in
for Xen guests. That means exposing the MMCONFIG and restructing the E820 to fit that in.
Problem:
- Migration is not working with Q35. (But for v1 you wouldn't migrate, however later hardware will surely have SR-IOV so we will need to migrate).

- There are no developers who have an OK from their management to focus on this. (Potential solution: Poke Intel management to see if they can get more developers on it)

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

#110 lore raw
Quoted 37 lines · Konrad Rzeszutek Wilk
Quoted 22 lines · Michael S. Tsirkin
Quoted 21 lines · Konrad Rzeszutek Wilk
Quoted 8 lines · Paolo Bonzini

Il 01/07/2014 19:39, Ross Philipson ha scritto:

Quoted 6 lines

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

Quoted 8 lines

The problem is not activation, the problem is that the patches are making assumptions on the driver and the firmware that might work today but are IMHO just not sane.

I would have no problem with a clean patchset that adds a new machine type and doesn't touch code in "-M pc", but it looks like mst disagrees. Ultimately, if a patchset is too hacky for upstream, you can include it in your downstream XenClient (and XenServer) QEMU branch. It happens.

And then this discussion will come back again in a year when folks rebase and ask: Why hasn't this been done upstream.

Quoted 8 lines
Quoted 5 lines

Then the discussion resumes ..

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

Before I answer could you clarify please:
by Southbridge do you mean the PCH at slot 1f or the MCH at slot 0 or both?

MCH slot. We read/write from this (see intel_setup_mchbar) from couple of registers (0x44 and 0x48 if gen >= 4, otherwise 0x54). It is hard-coded in the i915_get_bridge_dev (see ec2a4c3fdc8e82fe82a25d800e85c1ea06b74372) as 0:0.0 BDF.

Quoted 7 lines

The PCH (does not matter where it sits) we only use the model:vendor id to figure out the pch_type (see intel_detect_pch).

I don't see why that model:vendor_id can't be exposed via checking the type of device:vendor_id of the IGD itself. CC-ing some Intel i915 authors.

So for the discussion here, when I say Southbridge I mean MCH.

OK so PIIX spec says:

0x10-4F reserved.

So far so good, it is likely harmless to stick something at 0x44 and 0x48 most guests will very likely just keep ticking.

0x54-0x57 deal with RAM though.

Maybe we can just stick to emulating gen >= 4 for now:
detect it on host and fail assignment.
How old is gen 4?

Quoted 47 lines
Quoted 47 lines
Quoted 47 lines

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

2). Since we need the Southbridge magic addresses, we can expose
an bridge. [I think everybody agrees that we need to do that since 1) is no go).

3). What kind of bridge. We can do:

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

b2) We would need to use the Q35.
b2a). If we need Q35, that needs to be exposed in
for Xen guests. That means exposing the MMCONFIG and restructing the E820 to fit that in.
Problem:
- Migration is not working with Q35. (But for v1 you wouldn't migrate, however later hardware will surely have SR-IOV so we will need to migrate).

- There are no developers who have an OK from their management to focus on this. (Potential solution: Poke Intel management to see if they can get more developers on it)

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

#111 lore raw
In reply to Konrad Rzeszutek Wilk
Quoted 58 lines · Konrad Rzeszutek Wilk
Quoted 8 lines · Paolo Bonzini

Il 01/07/2014 19:39, Ross Philipson ha scritto:

Quoted 6 lines

We do IGD pass-through in our project (XenClient). The patches originally came from our project. We surface the same ISA bridge and have never had activation issues on any version of Widows from XP to Win8. We do not normally run server platforms so I can't say for sure there.

Quoted 8 lines

The problem is not activation, the problem is that the patches are making assumptions on the driver and the firmware that might work today but are IMHO just not sane.

I would have no problem with a clean patchset that adds a new machine type and doesn't touch code in "-M pc", but it looks like mst disagrees. Ultimately, if a patchset is too hacky for upstream, you can include it in your downstream XenClient (and XenServer) QEMU branch. It happens.

And then this discussion will come back again in a year when folks rebase and ask: Why hasn't this been done upstream.

Then the discussion resumes ..

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

2). Since we need the Southbridge magic addresses, we can expose
an bridge. [I think everybody agrees that we need to do that since 1) is no go).

3). What kind of bridge. We can do:

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

b2) We would need to use the Q35.
b2a). If we need Q35, that needs to be exposed in
for Xen guests. That means exposing the MMCONFIG and restructing the E820 to fit that in.
Problem:
- Migration is not working with Q35. (But for v1 you wouldn't migrate, however later hardware will surely have SR-IOV so we will need to migrate).

Quoted 4 lines

- There are no developers who have an OK from their management to focus on this. (Potential solution: Poke Intel management to see if they can get more developers on it)

- need to test compatibility with current Xen VM images

Quoted 10 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

UK timezone. Maybe Friday afternoon so that afterwards we can go have enough beers to forget about all this.

#112 lore raw
Quoted 9 lines
Quoted 5 lines

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

UK timezone. Maybe Friday afternoon so that afterwards we can go have enough beers to forget about all this.

Is this determined formally?

I mean I can ask if someone in Intel can attend this talk, and then they maybe answer your questions for GFX, Linux native driver, Windows driver.

Tiejun

#113 lore raw
Quoted 11 lines · Tiejun
Quoted 9 lines
Quoted 5 lines

Is that about correct?

What are folks timezones and the best days next week to talk about this on either Google Hangout or the phone?

UK timezone. Maybe Friday afternoon so that afterwards we can go have enough beers to forget about all this.

Is this determined formally?

Not sure what you mean, but I am just polling times and days so we all can talk.

Quoted 4 lines

I mean I can ask if someone in Intel can attend this talk, and then they maybe answer your questions for GFX, Linux native driver, Windows driver.

Yes of course. That would be fantastic!

Quoted 2 lines

Tiejun

#114 lore raw

[Qemu-devel] ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

In reply to Konrad Rzeszutek Wilk

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

Regarding the second, fixing IGD hardware to not rely on chipset magic is a no-go, I agree. I disagree that it's a no-go to define a "backdoor" that lets a hypervisor pass the right information to the driver without hacking the chipset device model.

The hardware folks would have to give us a place for a pair of registers (something like data/address), and a bit somewhere else that would be always 0 on hardware and always 1 if the hypervisor is implementing the pair of registers. This is similar to CPUID, which has the HYPERVISOR bit + hypervisor-defined leaves at 0x40000000.

The data/address pair could be in a BAR, in configuration space, in the low VGA ports at 0x3c0-0x3df, wherever. The hypervisor bit can be in the same place or somewhere else---again, whatever is convenient for the hardware folks. We just need *one bit* that is known-zero on all hardware, and 8 bytes in a reserved area. I don't think it's too hard to find this space, and I really, really would like Intel to follow up on a paravirtualized backdoor.

That said, we have the problem of existing guests, so I agree something else is needed.

Quoted 3 lines

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

This is pretty much the only solution for existing Linux guests that look up the southbridge by class.

The proposed solution here is to define a new "pci stub" device in QEMU that lets you define a do-nothing device with your desired vendor ID, device ID, class and optionally subsystem IDs.

The new machine type (the one that instantiates the special IGD-passthrough-enabled northbridge) can then instantiate this stub device at 1f.0 with the desired vendor ID, device ID and class ID.

If we cannot get the paravirtualized backdoor, it would also make sense to:

- have drivers standardize on a single way to probe the southbridge

- make this be neither by class (because the firmware wants to distinguish the actual ISA bridge from the stub, and it can do so by looking up the class), nor by slot (because this conflicts with the Q35 chipset model that has the southbridge at 1f.0).

mst's proposal was to probe by subsystem id. I'm not sure I understood the details exactly, but I trust him. :) However, in case it wasn't clear I think a paravirtualized backdoor would still be better.

Quoted 6 lines

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

As I understand it, mst brought up Q35 because the northbridge configuration space layout might be more similar to what the driver expects than for PIIX4. But I don't think anyone really said whether this is true or false.

I think Q35 is absolutely not a requirement for IGD passthrough, especially until this statement is either proved or disproved.

Quoted 3 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

FWIW, I don't really care about code sharing with KVM. That's a separate problem and it's not necessary to bring it up and make waters even more muddy.

Paolo

#115 lore raw

Re: [Qemu-devel] ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 63 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

Regarding the second, fixing IGD hardware to not rely on chipset magic is a no-go, I agree. I disagree that it's a no-go to define a "backdoor" that lets a hypervisor pass the right information to the driver without hacking the chipset device model.

The hardware folks would have to give us a place for a pair of registers (something like data/address), and a bit somewhere else that would be always 0 on hardware and always 1 if the hypervisor is implementing the pair of registers. This is similar to CPUID, which has the HYPERVISOR bit + hypervisor-defined leaves at 0x40000000.

The data/address pair could be in a BAR, in configuration space, in the low VGA ports at 0x3c0-0x3df, wherever. The hypervisor bit can be in the same place or somewhere else---again, whatever is convenient for the hardware folks. We just need *one bit* that is known-zero on all hardware, and 8 bytes in a reserved area. I don't think it's too hard to find this space, and I really, really would like Intel to follow up on a paravirtualized backdoor.

That said, we have the problem of existing guests, so I agree something else is needed.

Quoted 3 lines

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

This is pretty much the only solution for existing Linux guests that look up the southbridge by class.

The proposed solution here is to define a new "pci stub" device in QEMU that lets you define a do-nothing device with your desired vendor ID, device ID, class and optionally subsystem IDs.

The new machine type (the one that instantiates the special IGD-passthrough-enabled northbridge) can then instantiate this stub device at 1f.0 with the desired vendor ID, device ID and class ID.

If we cannot get the paravirtualized backdoor, it would also make sense to:

- have drivers standardize on a single way to probe the southbridge

Quoted 8 lines

- make this be neither by class (because the firmware wants to distinguish the actual ISA bridge from the stub, and it can do so by looking up the class), nor by slot (because this conflicts with the Q35 chipset model that has the southbridge at 1f.0).

mst's proposal was to probe by subsystem id. I'm not sure I understood the details exactly, but I trust him. :) However, in case it wasn't clear I think a paravirtualized backdoor would still be better.

This was a paravirtualized idea actually. Since ISA bridge is just needed for type identification, stick this info in subsystem device id. guest could do

	if subsystem vendor id == xen then
		get type from subsystem device id

does not address pci host registers.

Quoted 7 lines
Quoted 6 lines

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

Quoted 6 lines

As I understand it, mst brought up Q35 because the northbridge configuration space layout might be more similar to what the driver expects than for PIIX4. But I don't think anyone really said whether this is true or false.

I think Q35 is absolutely not a requirement for IGD passthrough, especially until this statement is either proved or disproved.

I kept saying MCH/PCH, people keep hearing Q35.

There is actually c:

c) the ideal solution, clearly superior to the above set of hacks (a) and (b), is to actually emulate the chipsets that include the necessary cards.

For example, if you want to support Lynxpoint cards, emulate Z87.

Q35 codebase could be a good starting point in that work.

Quoted 9 lines
Quoted 3 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

FWIW, I don't really care about code sharing with KVM. That's a separate problem and it's not necessary to bring it up and make waters even more muddy.

Paolo

I agree here.
I would like to see everything passed to these fake devices through properties though.
xen could populate these properties from sysfs, kvm could later do its own thing whatever it will be.

Signature · 1 line
MST
#116 lore raw

Re: [Qemu-devel] ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 28 lines · Michael S. Tsirkin
Quoted 27 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

Regarding the second, fixing IGD hardware to not rely on chipset magic is a no-go, I agree. I disagree that it's a no-go to define a "backdoor" that lets a hypervisor pass the right information to the driver without hacking the chipset device model.

Quoted 8 lines
Quoted 8 lines

The hardware folks would have to give us a place for a pair of registers (something like data/address), and a bit somewhere else that would be always 0 on hardware and always 1 if the hypervisor is implementing the pair of registers. This is similar to CPUID, which has the HYPERVISOR bit + hypervisor-defined leaves at 0x40000000.

The data/address pair could be in a BAR, in configuration space, in the low VGA ports at 0x3c0-0x3df, wherever. The hypervisor bit can be in the same

This all looks like wishful thinking to me. Just look though the i915 driver, hardware seems to arbitrarily change between chips and I expect the drivers have a hard enough time supporting real hardware. I would like to see a concise document/comment from Intel listing which registers, opregions, gtt mappings are required to be mirrored to the guest and what needs write access through to the host per device generation though. The dependency on MCH/PCH IDs is only part of the story. Things like opregions and gtt mappings may require identity mapping to the host and therefore require reserved memory regions and guest access. In order to provide that access, we need to know exactly what we're providing access to and whether it compromises the host isolation.

I do want to note that we should not add any dependency on VGA space if we do go the path of a paravirt interface. VGA routing is a nightmare and for a VFIO path forward, I think we'll want to rely on legacy-free UEFI drivers.

Quoted 67 lines
Quoted 28 lines

place or somewhere else---again, whatever is convenient for the hardware folks. We just need *one bit* that is known-zero on all hardware, and 8 bytes in a reserved area. I don't think it's too hard to find this space, and I really, really would like Intel to follow up on a paravirtualized backdoor.

That said, we have the problem of existing guests, so I agree something else is needed.

Quoted 3 lines

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

This is pretty much the only solution for existing Linux guests that look up the southbridge by class.

The proposed solution here is to define a new "pci stub" device in QEMU that lets you define a do-nothing device with your desired vendor ID, device ID, class and optionally subsystem IDs.

The new machine type (the one that instantiates the special IGD-passthrough-enabled northbridge) can then instantiate this stub device at 1f.0 with the desired vendor ID, device ID and class ID.

If we cannot get the paravirtualized backdoor, it would also make sense to:

- have drivers standardize on a single way to probe the southbridge

Quoted 8 lines

- make this be neither by class (because the firmware wants to distinguish the actual ISA bridge from the stub, and it can do so by looking up the class), nor by slot (because this conflicts with the Q35 chipset model that has the southbridge at 1f.0).

mst's proposal was to probe by subsystem id. I'm not sure I understood the details exactly, but I trust him. :) However, in case it wasn't clear I think a paravirtualized backdoor would still be better.

This was a paravirtualized idea actually. Since ISA bridge is just needed for type identification, stick this info in subsystem device id. guest could do

	if subsystem vendor id == xen then
		get type from subsystem device id

does not address pci host registers.

Quoted 7 lines
Quoted 6 lines

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

Quoted 6 lines

As I understand it, mst brought up Q35 because the northbridge configuration space layout might be more similar to what the driver expects than for PIIX4. But I don't think anyone really said whether this is true or false.

I think Q35 is absolutely not a requirement for IGD passthrough, especially until this statement is either proved or disproved.

I kept saying MCH/PCH, people keep hearing Q35.

There is actually c:

Quoted 8 lines

c) the ideal solution, clearly superior to the above set of hacks (a) and (b), is to actually emulate the chipsets that include the necessary cards.

For example, if you want to support Lynxpoint cards, emulate Z87.

Q35 codebase could be a good starting point in that work.

This would only guarantee that QEMU never supports the latest hardware. Also, is it really sufficient to have a virtual implementation of the host chipset or do we also still need to populate registers in that virtual chipset with host values? At least we'd know that the passthrough registers don't conflict, but that may be the only problem it solves.

Quoted 8 lines
Quoted 8 lines
Quoted 3 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

FWIW, I don't really care about code sharing with KVM. That's a separate problem and it's not necessary to bring it up and make waters even more muddy.

Quoted 7 lines
Quoted 1 line

Paolo

I agree here.
I would like to see everything passed to these fake devices through properties though.
xen could populate these properties from sysfs, kvm could later do its own thing whatever it will be.

I expect that a VFIO solution would also want to populate from sysfs. I think we'll need a new "device specific" VFIO region to provide access to non-PCI resources of IGD, but I don't want that to include random registers on other devices. It would really throw a wrench in the isolation of a guest if IGD passthrough were to require write access to registers or config space on the MCH/PCH though. Thanks,

Alex

#117 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

In reply to Paolo Bonzini
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 23 lines

Regarding the second, fixing IGD hardware to not rely on chipset magic is a no-go, I agree. I disagree that it's a no-go to define a "backdoor" that lets a hypervisor pass the right information to the driver without hacking the chipset device model.

The hardware folks would have to give us a place for a pair of registers (something like data/address), and a bit somewhere else that would be always 0 on hardware and always 1 if the hypervisor is implementing the pair of registers. This is similar to CPUID, which has the HYPERVISOR bit + hypervisor-defined leaves at 0x40000000.

The data/address pair could be in a BAR, in configuration space, in the low VGA ports at 0x3c0-0x3df, wherever. The hypervisor bit can be in the same place or somewhere else---again, whatever is convenient for the hardware folks. We just need *one bit* that is known-zero on all hardware, and 8 bytes in a reserved area. I don't think it's too hard to find this space, and I really, really would like Intel to follow up on a paravirtualized backdoor.

That said, we have the problem of existing guests, so I agree something else is needed.

Quoted 6 lines
Quoted 3 lines

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

This is pretty much the only solution for existing Linux guests that look up the southbridge by class.

Right.

Quoted 4 lines

The proposed solution here is to define a new "pci stub" device in QEMU that lets you define a do-nothing device with your desired vendor ID, device ID, class and optionally subsystem IDs.

<nods>

Quoted 4 lines

The new machine type (the one that instantiates the special IGD-passthrough-enabled northbridge) can then instantiate this stub device at 1f.0 with the desired vendor ID, device ID and class ID.

Which is kind of neat because you can use a different type of device ID with (say make it look like Ibex Peak) and pair it up with an IGD that is found only on LynxPoint. Oh fun!

Quoted 5 lines

If we cannot get the paravirtualized backdoor, it would also make sense to:

- have drivers standardize on a single way to probe the southbridge

Quoted 8 lines

- make this be neither by class (because the firmware wants to distinguish the actual ISA bridge from the stub, and it can do so by looking up the class), nor by slot (because this conflicts with the Q35 chipset model that has the southbridge at 1f.0).

mst's proposal was to probe by subsystem id. I'm not sure I understood the details exactly, but I trust him. :) However, in case it wasn't clear I think a paravirtualized backdoor would still be better.

OK, like this:

drivers/gpu/drm/i915/i915_drv.c +2 -0
index 651e65e..03f2829 100644
@@ -433,6 +433,8 @@ void intel_detect_pch(struct drm_device *dev)
 			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			dev_priv->pch_id = id;
 
+			if (pch->subsystem_vendor == PCI_VENDOR_ID_XEN)
+				id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Quoted 8 lines
Quoted 7 lines

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

Quoted 6 lines

As I understand it, mst brought up Q35 because the northbridge configuration space layout might be more similar to what the driver expects than for PIIX4. But I don't think anyone really said whether this is true or false.

I think Q35 is absolutely not a requirement for IGD passthrough, especially until this statement is either proved or disproved.

OK, so lets drop that.

Quoted 9 lines
Quoted 4 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

FWIW, I don't really care about code sharing with KVM. That's a separate problem and it's not necessary to bring it up and make waters even more muddy.

OK, lets drop that for now.

Quoted 1 line

Paolo

#118 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Il 02/07/2014 18:23, Konrad Rzeszutek Wilk ha scritto:

drivers/gpu/drm/i915/i915_drv.c void intel_detect_pch(struct drm_device *dev) · line 437

Quoted 10 lines
drivers/gpu/drm/i915/i915_drv.c +2 -0
index 651e65e..03f2829 100644
@@ -433,6 +433,8 @@ void intel_detect_pch(struct drm_device *dev)
 			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			dev_priv->pch_id = id;
 
+			if (pch->subsystem_vendor == PCI_VENDOR_ID_XEN)
+				id = pch->device & INTEL_PCH_DEVICE_ID_MASK;

Actually you could look at *dev*'s subsystem IDs and skip the pch lookup completely.

Paolo

Quoted 4 lines
drivers/gpu/drm/i915/i915_drv.c +0 -0
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Quoted 1 line
Quoted 1 line
#119 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

In reply to Konrad Rzeszutek Wilk
Quoted 128 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 23 lines

Regarding the second, fixing IGD hardware to not rely on chipset magic is a no-go, I agree. I disagree that it's a no-go to define a "backdoor" that lets a hypervisor pass the right information to the driver without hacking the chipset device model.

The hardware folks would have to give us a place for a pair of registers (something like data/address), and a bit somewhere else that would be always 0 on hardware and always 1 if the hypervisor is implementing the pair of registers. This is similar to CPUID, which has the HYPERVISOR bit + hypervisor-defined leaves at 0x40000000.

The data/address pair could be in a BAR, in configuration space, in the low VGA ports at 0x3c0-0x3df, wherever. The hypervisor bit can be in the same place or somewhere else---again, whatever is convenient for the hardware folks. We just need *one bit* that is known-zero on all hardware, and 8 bytes in a reserved area. I don't think it's too hard to find this space, and I really, really would like Intel to follow up on a paravirtualized backdoor.

That said, we have the problem of existing guests, so I agree something else is needed.

Quoted 6 lines
Quoted 3 lines

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

This is pretty much the only solution for existing Linux guests that look up the southbridge by class.

Right.

Quoted 4 lines

The proposed solution here is to define a new "pci stub" device in QEMU that lets you define a do-nothing device with your desired vendor ID, device ID, class and optionally subsystem IDs.

<nods>

Quoted 4 lines

The new machine type (the one that instantiates the special IGD-passthrough-enabled northbridge) can then instantiate this stub device at 1f.0 with the desired vendor ID, device ID and class ID.

Which is kind of neat because you can use a different type of device ID with (say make it look like Ibex Peak) and pair it up with an IGD that is found only on LynxPoint. Oh fun!

Quoted 5 lines

If we cannot get the paravirtualized backdoor, it would also make sense to:

- have drivers standardize on a single way to probe the southbridge

Quoted 8 lines

- make this be neither by class (because the firmware wants to distinguish the actual ISA bridge from the stub, and it can do so by looking up the class), nor by slot (because this conflicts with the Q35 chipset model that has the southbridge at 1f.0).

mst's proposal was to probe by subsystem id. I'm not sure I understood the details exactly, but I trust him. :) However, in case it wasn't clear I think a paravirtualized backdoor would still be better.

OK, like this:

drivers/gpu/drm/i915/i915_drv.c +0 -0
index 651e65e..03f2829 100644

drivers/gpu/drm/i915/i915_drv.c void intel_detect_pch(struct drm_device *dev) · line 440

Quoted 8 lines
drivers/gpu/drm/i915/i915_drv.c +2 -0
@@ -433,6 +433,8 @@ void intel_detect_pch(struct drm_device *dev)
 			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			dev_priv->pch_id = id;
 
+			if (pch->subsystem_vendor == PCI_VENDOR_ID_XEN)
+				id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");

No!
The point is to avoid looking at PCH at all, only look at the card itself.

Quoted 28 lines
Quoted 8 lines
Quoted 7 lines

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

Quoted 6 lines

As I understand it, mst brought up Q35 because the northbridge configuration space layout might be more similar to what the driver expects than for PIIX4. But I don't think anyone really said whether this is true or false.

I think Q35 is absolutely not a requirement for IGD passthrough, especially until this statement is either proved or disproved.

OK, so lets drop that.

Quoted 9 lines
Quoted 4 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

FWIW, I don't really care about code sharing with KVM. That's a separate problem and it's not necessary to bring it up and make waters even more muddy.

OK, lets drop that for now.

Quoted 1 line

Paolo

#120 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

In reply to Konrad Rzeszutek Wilk
Quoted 58 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

Quoted 2 lines

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.
It would then run on the priveledged host
and we won't need to deal with it in QEMU.

Quoted 103 lines
Quoted 23 lines

Regarding the second, fixing IGD hardware to not rely on chipset magic is a no-go, I agree. I disagree that it's a no-go to define a "backdoor" that lets a hypervisor pass the right information to the driver without hacking the chipset device model.

The hardware folks would have to give us a place for a pair of registers (something like data/address), and a bit somewhere else that would be always 0 on hardware and always 1 if the hypervisor is implementing the pair of registers. This is similar to CPUID, which has the HYPERVISOR bit + hypervisor-defined leaves at 0x40000000.

The data/address pair could be in a BAR, in configuration space, in the low VGA ports at 0x3c0-0x3df, wherever. The hypervisor bit can be in the same place or somewhere else---again, whatever is convenient for the hardware folks. We just need *one bit* that is known-zero on all hardware, and 8 bytes in a reserved area. I don't think it's too hard to find this space, and I really, really would like Intel to follow up on a paravirtualized backdoor.

That said, we have the problem of existing guests, so I agree something else is needed.

Quoted 6 lines
Quoted 3 lines

a) Two bridges - one 'passthrough' and the legacy ISA bridge that QEMU emulates. Both Linux and Windows are OK with two bridges (even thought it is pretty weird).

This is pretty much the only solution for existing Linux guests that look up the southbridge by class.

Right.

Quoted 4 lines

The proposed solution here is to define a new "pci stub" device in QEMU that lets you define a do-nothing device with your desired vendor ID, device ID, class and optionally subsystem IDs.

<nods>

Quoted 4 lines

The new machine type (the one that instantiates the special IGD-passthrough-enabled northbridge) can then instantiate this stub device at 1f.0 with the desired vendor ID, device ID and class ID.

Which is kind of neat because you can use a different type of device ID with (say make it look like Ibex Peak) and pair it up with an IGD that is found only on LynxPoint. Oh fun!

Quoted 5 lines

If we cannot get the paravirtualized backdoor, it would also make sense to:

- have drivers standardize on a single way to probe the southbridge

Quoted 8 lines

- make this be neither by class (because the firmware wants to distinguish the actual ISA bridge from the stub, and it can do so by looking up the class), nor by slot (because this conflicts with the Q35 chipset model that has the southbridge at 1f.0).

mst's proposal was to probe by subsystem id. I'm not sure I understood the details exactly, but I trust him. :) However, in case it wasn't clear I think a paravirtualized backdoor would still be better.

OK, like this:

drivers/gpu/drm/i915/i915_drv.c +2 -0
index 651e65e..03f2829 100644
@@ -433,6 +433,8 @@ void intel_detect_pch(struct drm_device *dev)
 			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			dev_priv->pch_id = id;
 
+			if (pch->subsystem_vendor == PCI_VENDOR_ID_XEN)
+				id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_IBX;
 				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
Quoted 8 lines
Quoted 7 lines

b) One bridge - the one that QEMU emulates - and lets emulate more of the registers (by emulate - I mean for some get the data from the real hardware).

b1). We can't use the legacy because the registers are
above 256 (is that correct? Did I miss something?)

Quoted 6 lines

As I understand it, mst brought up Q35 because the northbridge configuration space layout might be more similar to what the driver expects than for PIIX4. But I don't think anyone really said whether this is true or false.

I think Q35 is absolutely not a requirement for IGD passthrough, especially until this statement is either proved or disproved.

OK, so lets drop that.

Quoted 9 lines
Quoted 4 lines

4). Code does a bit of sysfs that could use some refacturing with
the KVM code.
Problem: More time needed to do the code restructing.

FWIW, I don't really care about code sharing with KVM. That's a separate problem and it's not necessary to bring it up and make waters even more muddy.

OK, lets drop that for now.

Quoted 1 line

Paolo

#121 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 59 lines · Michael S. Tsirkin
Quoted 58 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

Quoted 5 lines
Quoted 2 lines

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

Quoted 2 lines

It would then run on the priveledged host
and we won't need to deal with it in QEMU.

#122 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 63 lines · On Thu, 3 Jul 2014 14:26:12 -0400 Konrad Rzeszutek Wilk…
Quoted 62 lines · Michael S. Tsirkin
Quoted 60 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 6 lines
Quoted 2 lines

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

The display part of the GPU is partly on the PCH, and it's possible to mix & match them a bit, so we have this detection code to figure things out. In some cases, the PCH display portion may not even be present, so we look for that too.

Practically speaking, we could probably assume specific CPU/PCH combos, as I don't think they're generally mixed across generations, though SNB and IVB did have compatible sockets, so there is the possibility of mixing CPT and PPT PCHs, but those are register identical as far as the graphics driver is concerned, so even that should be safe.

Beyond that, the other MCH data we need to look at is mirrored into the GPU's MMIO space on current gens. On older gens, we do need to poke at the memory controller a bit to get some info (see intel_setup_mchbar()), but that's not true of newer stuff. Looks like we only short circuit that on VLV though; we could probably do it on SNB+.

Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center
#123 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 84 lines · Jesse Barnes
Quoted 63 lines · On Thu, 3 Jul 2014 14:26:12 -0400 Konrad Rzeszutek Wilk…
Quoted 62 lines · Michael S. Tsirkin
Quoted 60 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 6 lines
Quoted 2 lines

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

The display part of the GPU is partly on the PCH, and it's possible to mix & match them a bit, so we have this detection code to figure things out. In some cases, the PCH display portion may not even be present, so we look for that too.

Practically speaking, we could probably assume specific CPU/PCH combos, as I don't think they're generally mixed across generations, though SNB and IVB did have compatible sockets, so there is the possibility of mixing CPT and PPT PCHs, but those are register identical as far as the graphics driver is concerned, so even that should be safe.

Quoted 6 lines

Beyond that, the other MCH data we need to look at is mirrored into the GPU's MMIO space on current gens. On older gens, we do need to poke at the memory controller a bit to get some info (see intel_setup_mchbar()), but that's not true of newer stuff. Looks like we only short circuit that on VLV though; we could probably do it on SNB+.

That sounds great. Tiejun could you confirm that with windows driver guys too?

Quoted 2 lines
Signature · 1 line
Jesse Barnes, Intel Open Source Technology Center
#124 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 92 lines · Michael S. Tsirkin
Quoted 84 lines · Jesse Barnes
Quoted 63 lines · On Thu, 3 Jul 2014 14:26:12 -0400 Konrad Rzeszutek Wilk…
Quoted 62 lines · Michael S. Tsirkin
Quoted 60 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 6 lines
Quoted 2 lines

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

The display part of the GPU is partly on the PCH, and it's possible to mix & match them a bit, so we have this detection code to figure things out. In some cases, the PCH display portion may not even be present, so we look for that too.

Practically speaking, we could probably assume specific CPU/PCH combos, as I don't think they're generally mixed across generations, though SNB and IVB did have compatible sockets, so there is the possibility of mixing CPT and PPT PCHs, but those are register identical as far as the graphics driver is concerned, so even that should be safe.

Quoted 6 lines

Beyond that, the other MCH data we need to look at is mirrored into the GPU's MMIO space on current gens. On older gens, we do need to poke at the memory controller a bit to get some info (see intel_setup_mchbar()), but that's not true of newer stuff. Looks like we only short circuit that on VLV though; we could probably do it on SNB+.

Quoted 2 lines

That sounds great. Tiejun could you confirm that with windows driver guys too?

ping?

Quoted 3 lines
Quoted 3 lines
Signature · 2 lines
-- 
Jesse Barnes, Intel Open Source Technology Center
#125 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 93 lines · Konrad Rzeszutek Wilk
Quoted 92 lines · Michael S. Tsirkin
Quoted 90 lines · Jesse Barnes
Quoted 63 lines · On Thu, 3 Jul 2014 14:26:12 -0400 Konrad Rzeszutek Wilk…
Quoted 62 lines · Michael S. Tsirkin
Quoted 60 lines · Konrad Rzeszutek Wilk
Quoted 11 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 6 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID; some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

  432                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  433                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  434                         dev_priv->pch_id = id;
  435
  436                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and pass through the registers you need. The patch must document _exactly_ why the registers are safe to pass. If they are not reserved on PIIX4, the patch must document what the same offsets mean on PIIX4, and why it's sensible to assume that firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 6 lines
Quoted 2 lines

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

The display part of the GPU is partly on the PCH, and it's possible to mix & match them a bit, so we have this detection code to figure things out. In some cases, the PCH display portion may not even be present, so we look for that too.

Practically speaking, we could probably assume specific CPU/PCH combos, as I don't think they're generally mixed across generations, though SNB and IVB did have compatible sockets, so there is the possibility of mixing CPT and PPT PCHs, but those are register identical as far as the graphics driver is concerned, so even that should be safe.

Beyond that, the other MCH data we need to look at is mirrored into the GPU's MMIO space on current gens. On older gens, we do need to poke at the memory controller a bit to get some info (see intel_setup_mchbar()), but that's not true of newer stuff. Looks like we only short circuit that on VLV though; we could probably do it on SNB+.

Quoted 4 lines
Quoted 2 lines

That sounds great. Tiejun could you confirm that with windows driver guys too?

ping?

Allen,

Could you reply this?

Thanks
Tiejun

#126 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

In reply to Michael S. Tsirkin
Quoted 1 line

That sounds great. Tiejun could you confirm that with windows driver guys too?

I believe windows driver can also assume specific CPU/PCH combos. I will discuss this with native Windows driver guys. Preferably, the same code path can be used for both native and virtualization cases to avoid frequent breakage as most developers and QA do not test new code changes in virtualization environment.

I have verified that Windows driver do not need to write to any MCH PCI registers on HSW/BDW so the PCI write function can be removed. The MCH PCI registers that need to be read, we are working with HW team to get them mirrored in GPU MMIO registers in future HW.

Allen

-----Original Message-----
From: Intel-gfx [mailto:[email protected]] On Behalf Of Michael S. Tsirkin
Sent: Thursday, July 03, 2014 1:28 PM
To: Jesse Barnes
Cc: [email protected]; [email protected]; Ross Philipson; Konrad Rzeszutek Wilk; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Anthony Perard; Stefano Stabellini; [email protected]; Paolo Bonzini; Zhang, Yang Z; Chen, Tiejun
Subject: Re: [Intel-gfx] ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 85 lines · Jesse Barnes
Quoted 64 lines · On Thu, 3 Jul 2014 14:26:12 -0400 Konrad Rzeszutek Wilk…
Quoted 63 lines · Michael S. Tsirkin
Quoted 61 lines · Konrad Rzeszutek Wilk
Quoted 5 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 4 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

Quoted 7 lines
Quoted 2 lines

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID;
some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and
pass through the registers you need. The patch must document
_exactly_ why the registers are safe to pass. If they are not
reserved on PIIX4, the patch must document what the same
offsets mean on PIIX4, and why it's sensible to assume that
firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 6 lines
Quoted 2 lines

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

The display part of the GPU is partly on the PCH, and it's possible to mix & match them a bit, so we have this detection code to figure things out. In some cases, the PCH display portion may not even be present, so we look for that too.

Practically speaking, we could probably assume specific CPU/PCH combos, as I don't think they're generally mixed across generations, though SNB and IVB did have compatible sockets, so there is the possibility of mixing CPT and PPT PCHs, but those are register identical as far as the graphics driver is concerned, so even that should be safe.

Quoted 6 lines

Beyond that, the other MCH data we need to look at is mirrored into the GPU's MMIO space on current gens. On older gens, we do need to poke at the memory controller a bit to get some info (see intel_setup_mchbar()), but that's not true of newer stuff. Looks like we only short circuit that on VLV though; we could probably do it on SNB+.

That sounds great. Tiejun could you confirm that with windows driver guys too?

Quoted 2 lines

--
Jesse Barnes, Intel Open Source Technology Center

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#127 lore raw

Re: ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 6 lines · Allen M
Quoted 1 line

That sounds great. Tiejun could you confirm that with windows driver guys too?

I believe windows driver can also assume specific CPU/PCH combos. I will discuss this with native Windows driver guys. Preferably, the same code path can be used for both native and virtualization cases to avoid frequent breakage as most developers and QA do not test new code changes in virtualization environment.

I have verified that Windows driver do not need to write to any MCH PCI registers on HSW/BDW so the PCI write function can be removed. The MCH PCI registers that need to be read, we are working with HW team to get them mirrored in GPU MMIO registers in future HW.

For the MCH PCI registers that do need to be read - can you tell us which ones those are?

Thank you!

Quoted 110 lines

Allen

-----Original Message-----
From: Intel-gfx [mailto:[email protected]] On Behalf Of Michael S. Tsirkin
Sent: Thursday, July 03, 2014 1:28 PM
To: Jesse Barnes
Cc: [email protected]; [email protected]; Ross Philipson; Konrad Rzeszutek Wilk; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Anthony Perard; Stefano Stabellini; [email protected]; Paolo Bonzini; Zhang, Yang Z; Chen, Tiejun
Subject: Re: [Intel-gfx] ResettRe: [Xen-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support

Quoted 85 lines · Jesse Barnes
Quoted 64 lines · On Thu, 3 Jul 2014 14:26:12 -0400 Konrad Rzeszutek Wilk…
Quoted 63 lines · Michael S. Tsirkin
Quoted 61 lines · Konrad Rzeszutek Wilk
Quoted 5 lines · Paolo Bonzini

Il 02/07/2014 16:00, Konrad Rzeszutek Wilk ha scritto:

Quoted 4 lines

With this long thread I lost a bit context about the challenges that exists. But let me try summarizing it here - which will hopefully get some consensus.

Quoted 7 lines
Quoted 2 lines

1). Fix IGD hardware to not use Southbridge magic addresses.
We can moan and moan but I doubt it is going to change.

There are two problems:

- Northbridge (i.e. MCH i.e. PCI host bridge) configuration space addresses

Right. So in drivers/gpu/drm/i915/i915_dma.c:
1135 #define MCHBAR_I915 0x44
1136 #define MCHBAR_I965 0x48

1147 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1152 if (INTEL_INFO(dev)->gen >= 4)
1153 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1154 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1155 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

and

1139 #define DEVEN_REG 0x54

1193 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1202 if (IS_I915G(dev) || IS_I915GM(dev)) {
1203 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1204 enabled = !!(temp & DEVEN_MCHBAR_EN);
1205 } else {
1206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1207 enabled = temp & 1;
1208 }

Quoted 3 lines

- Southbridge (i.e. PCH i.e. ISA bridge) vendor/device ID;
some versions of the driver identify it by class, some versions identify it by slot (1f.0).

Right, So in drivers/gpu/drm/i915/i915_drv.c the giant intel_detect_pch which sets the pch_type based on :

432 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
433 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
434 dev_priv->pch_id = id;
435
436 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {

It checks for 0x3b00, 0x1c00, 0x1e00, 0x8c00 and 0x9c00. The INTEL_PCH_DEVICE_ID_MASK is 0xff00

Quoted 7 lines

To solve the first, make a new machine type, PIIX4-based, and
pass through the registers you need. The patch must document
_exactly_ why the registers are safe to pass. If they are not
reserved on PIIX4, the patch must document what the same
offsets mean on PIIX4, and why it's sensible to assume that
firmware for virtual machine will not read/write them. Bonus point for also documenting the same for Q35.

OK. They look to be related to setting up an MBAR , but I don't understand why it is needed. Hopefully some of the i915 folks CC-ed here can answer.

Quoted 6 lines
Quoted 2 lines

In particular, I think setting up MBAR should move out of i915 and become the bridge driver tweak on linux and windows.

That is an excellent idea.

However I am still curious to _why_ it has to be done in the first place.

The display part of the GPU is partly on the PCH, and it's possible to mix & match them a bit, so we have this detection code to figure things out. In some cases, the PCH display portion may not even be present, so we look for that too.

Practically speaking, we could probably assume specific CPU/PCH combos, as I don't think they're generally mixed across generations, though SNB and IVB did have compatible sockets, so there is the possibility of mixing CPT and PPT PCHs, but those are register identical as far as the graphics driver is concerned, so even that should be safe.

Quoted 6 lines

Beyond that, the other MCH data we need to look at is mirrored into the GPU's MMIO space on current gens. On older gens, we do need to poke at the memory controller a bit to get some info (see intel_setup_mchbar()), but that's not true of newer stuff. Looks like we only short circuit that on VLV though; we could probably do it on SNB+.

That sounds great. Tiejun could you confirm that with windows driver guys too?

Quoted 2 lines

--
Jesse Barnes, Intel Open Source Technology Center

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx