ata: Fixes related to APM X-Gene SATA host controller driver.
Subsystems (3)
v2 cover ata: Fixes related to APM X-Gene SATA host controller driver.
This patch set contains a couple of fixes related to APM X-Gene SATA controller driver.
v2 Change:
- Drop the Link down retry patch from this patch set.
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Suman Tripathi (2):
ata: Fix the watermark threshold for the APM X-Gene SATA host
controller driver.
arm64: Fix the APM X-Gene SoC SATA PHY clock DTS node csr-mask of the
SATA Host Controller 1.
arch/arm64/boot/dts/apm-storm.dtsi | 5 +---- drivers/ata/ahci_xgene.c | 7 +++++++ 2 files changed, 8 insertions(+), 4 deletions(-)
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1.8.2.1
PATCH v2 1/2 ata: Fix the watermark threshold for the APM X-Gene SATA host controller driver.
This patch fixes the watermark threshold of the receive FIFO for the APM X-Gene SATA host controller driver.
--- drivers/ata/ahci_xgene.c | 7 +++++++ 1 file changed, 7 insertions(+)
drivers/ata/ahci_xgene.c +7 -0
@@ -67,6 +67,9 @@#define PORTAXICFG 0x000000bc#define PORTAXICFG_OUTTRANS_SET (dst, src) \ (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) +#define PORTRANSCFG 0x000000c8 +#define PORTRANSCFG_RXWM_SET (dst, src) \ + (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))/* SATA host controller AXI CSR */ #define INT_SLV_TMOMASK 0x00000010
@@ -176,6 +179,10 @@ static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel) val =PORTAXICFG_OUTTRANS_SET (val,0xe );/* Set outstanding */ writel (val, mmio +PORTAXICFG );readl (mmio +PORTAXICFG );/* Force a barrier */ +/* Set the watermark threshold of the receive FIFO */ + val =readl (mmio +PORTRANSCFG ); + val =PORTRANSCFG_RXWM_SET (val,0x30 ); +writel (val, mmio +PORTRANSCFG ); }/**
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1.8.2.1
PATCH v2 1/2 ata: Fix the watermark threshold for the APM X-Gene SATA host controller driver.
Quoted 2 lines · Suman Tripathi
This patch fixes the watermark threshold of the receive FIFO for the APM X-Gene SATA host controller driver.
Can you please explain what are the effects of these patches? Patch descriptions should include why the specific changes are being made in addition to the description of the changes themselves. What are the implications of applying this patch?
Thanks.
Signature · 1 line
tejun
PATCH v2 2/2 arm64: Fix the APM X-Gene SoC SATA PHY clock DTS node csr-mask of the SATA Host Controller 1.
In reply to Suman TripathiThis patch fixes the SATA PHY clock DTS node csr-mask of the SATA Host controller 1. This patch also fixes the status of the PHY clock node of SATA Host Controller 1.
--- arch/arm64/boot/dts/apm-storm.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
arch/arm64/boot/dts/apm-storm.dtsi +1 -4
@@ -184,9 +184,8 @@ reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy1clk"; - status = "disabled"; csr-offset = <0x4>; - csr-mask = <0x00>; + csr-mask = <0x3a>; enable-offset = <0x0>; enable-mask = <0x06>; };
@@ -198,7 +197,6 @@ reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy2clk"; - status = "ok"; csr-offset = <0x4>; csr-mask = <0x3a>; enable-offset = <0x0>;
@@ -212,7 +210,6 @@ reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy3clk"; - status = "ok"; csr-offset = <0x4>; csr-mask = <0x3a>; enable-offset = <0x0>;
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1.8.2.1
PATCH v2 2/2 arm64: Fix the APM X-Gene SoC SATA PHY clock DTS node csr-mask of the SATA Host Controller 1.
Quoted 3 lines · Suman Tripathi
This patch fixes the SATA PHY clock DTS node csr-mask of the SATA Host controller 1. This patch also fixes the status of the PHY clock node of SATA Host Controller 1.
Ditto. Before, XXX was wrong and as a result YYY didn't work properly. This patch updates ZZZ to fix the issue.
Signature · 1 line
tejun