APQ8064 multimedia clock driver

PATCH New Stephen Boyd 1 participant 3 messages Jul 15, 2014

Subsystems (5)

Device tree bindings Arm Qualcomm mailing list Common clk Qualcomm clock drivers +1 more subsystems

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Stephen Boyd

author

2014-07-15 22:59 UTC #0 lore raw

cover APQ8064 multimedia clock driver

These two patches add support for the APQ8064 multimedia clock controller. They rely on a couple other patches to this driver[1][2].

Stephen Boyd (2):
clk: qcom: pll: Add support for configuring SR PLLs
clk: qcom: Add support for APQ8064 multimedia clocks

 .../devicetree/bindings/clock/qcom,mmcc.txt        |   1 +
 drivers/clk/qcom/clk-pll.c                         |  15 +-
 drivers/clk/qcom/clk-pll.h                         |   2 +
 drivers/clk/qcom/mmcc-msm8960.c                    | 433 ++++++++++++++++++++-
 include/dt-bindings/clock/qcom,mmcc-msm8960.h      |   8 +
 include/dt-bindings/reset/qcom,mmcc-msm8960.h      |   8 +
 6 files changed, 462 insertions(+), 5 deletions(-)

[1] https://patchwork.kernel.org/patch/4561071/
[2] https://patchwork.kernel.org/patch/4510951/

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Stephen Boyd

author

2014-07-15 22:59 UTC #1 lore raw

PATCH 1/2 clk: qcom: pll: Add support for configuring SR PLLs

Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on APQ8064.

Signed-off-by Stephen Boyd <[email protected]>

---
 drivers/clk/qcom/clk-pll.c | 15 ++++++++++++---
 drivers/clk/qcom/clk-pll.h |  2 ++
 2 files changed, 14 insertions(+), 3 deletions(-)

drivers/clk/qcom/clk-pll.c +12 -3

index 0f927c538613..9db03d3b1657 100644
@@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = {
 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
 
 static void
-clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
+clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
 {
 	u32 val;
 	u32 mask;

@@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
 	regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
 
 	/* Program bias count and lock count */
-	val = 1 << PLL_BIAS_COUNT_SHIFT;
+	val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
 	mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
 	mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
 	regmap_update_bits(regmap, pll->mode_reg, mask, val);

@@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
 	regmap_update_bits(regmap, pll->config_reg, mask, val);
 }
 
+void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
+		const struct pll_config *config, bool fsm_mode)
+{
+	clk_pll_configure(pll, regmap, config);
+	if (fsm_mode)
+		clk_pll_set_fsm_mode(pll, regmap, 8);
+}
+EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
+
 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
 		const struct pll_config *config, bool fsm_mode)
 {
 	clk_pll_configure(pll, regmap, config);
 	if (fsm_mode)
-		clk_pll_set_fsm_mode(pll, regmap);
+		clk_pll_set_fsm_mode(pll, regmap, 0);
 }
 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);

drivers/clk/qcom/clk-pll.h +2 -0

index 0775a99ca768..3003e9962472 100644
@@ -60,6 +60,8 @@ struct pll_config {
 	u32 aux_output_mask;
 };
 
+void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
+		const struct pll_config *config, bool fsm_mode);
 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
 		const struct pll_config *config, bool fsm_mode);

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Stephen Boyd

author

2014-07-15 22:59 UTC #2 lore raw

PATCH 2/2 clk: qcom: Add support for APQ8064 multimedia clocks

In reply to Stephen Boyd

The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks.

Signed-off-by Stephen Boyd <[email protected]>

---
 .../devicetree/bindings/clock/qcom,mmcc.txt        |   1 +
 drivers/clk/qcom/mmcc-msm8960.c                    | 433 ++++++++++++++++++++-
 include/dt-bindings/clock/qcom,mmcc-msm8960.h      |   8 +
 include/dt-bindings/reset/qcom,mmcc-msm8960.h      |   8 +
 4 files changed, 448 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/clock/qcom,mmcc.txt +1 -0

index d572e9964c54..60596018ea5d 100644
@@ -4,6 +4,7 @@ Qualcomm Multimedia Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 
+			"qcom,mmcc-apq8064"
 			"qcom,mmcc-msm8660"
 			"qcom,mmcc-msm8960"
 			"qcom,mmcc-msm8974"

drivers/clk/qcom/mmcc-msm8960.c +431 -2

512 lines not on this page · raw message

include/dt-bindings/clock/qcom,mmcc-msm8960.h +8 -0

index 5868ef14a777..85041b28f97f 100644
@@ -133,5 +133,13 @@
 #define CSIPHY0_TIMER_CLK				116
 #define PLL1						117
 #define PLL2						118
+#define RGB_TV_CLK					119
+#define NPL_TV_CLK					120
+#define VCAP_AHB_CLK					121
+#define VCAP_AXI_CLK					122
+#define VCAP_SRC					123
+#define VCAP_CLK					124
+#define VCAP_NPL_CLK					125
+#define PLL15						126
 
 #endif

include/dt-bindings/reset/qcom,mmcc-msm8960.h +8 -0

index ba36ec680118..11741113a841 100644
@@ -89,5 +89,13 @@
 #define CSI2_RESET					72
 #define CSI_RDI1_RESET					73
 #define CSI_RDI2_RESET					74
+#define GFX3D_AXI_RESET					75
+#define VCAP_AXI_RESET					76
+#define SMMU_VCAP_AHB_RESET				77
+#define VCAP_AHB_RESET					78
+#define CSI_RDI_RESET					79
+#define CSI_PIX_RESET					80
+#define VCAP_NPL_RESET					81
+#define VCAP_RESET					82
 
 #endif

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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation