mx6sxsabresd: Add Ethernet support
PATCH 2/2 mx6sxsabresd: Add Ethernet support
From: Fabio Estevam <[email protected]>
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
Add support for one FEC port initially.
---
FEC is not functional after this series.
There is still another patch for FEC that I will submit later that makes FEC functional on mx6solox, but it is orthogonal to this series.
arch/arm/include/asm/arch-mx6/crm_regs.h | 1 + arch/arm/include/asm/arch-mx6/iomux.h | 10 +++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 116 ++++++++++++++++++++++++++++ include/configs/mx6sxsabresd.h | 17 ++++ 4 files changed, 144 insertions(+)
arch/arm/include/asm/arch-mx6/crm_regs.h +1 -0
@@ -981,6 +981,7 @@ struct mxc_ccm_reg {#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000#define BF_ANADIG_PLL_ENET_RSVD1 (v) \ (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) +#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
arch/arm/include/asm/arch-mx6/iomux.h +10 -0
@@ -65,6 +65,16 @@#define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) +#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17) +#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13) +#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK) + +#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18) +#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14) +#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK) +#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24)#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24)#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)
board/freescale/mx6sxsabresd/mx6sxsabresd.c +116 -0
156 lines not on this page · raw message
include/configs/mx6sxsabresd.h +17 -0
@@ -181,6 +181,23 @@#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +/* Network */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +/* FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH
Signature · 1 line
1.9.1
PATCH 1/2 mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
From: Fabio Estevam <[email protected]>
Configure and enable the ethernet clock for mx6solox.
--- arch/arm/cpu/armv7/mx6/clock.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
arch/arm/cpu/armv7/mx6/clock.c +21 -0
@@ -373,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq) reg &= ~BM_ANADIG_PLL_ENET_BYPASS ;writel (reg, &anatop->pll_enet); +#ifdef CONFIG_MX6SX +/* +* Set enet ahb clock to 200MHz +* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB +*/ + reg =readl (&imx_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_ENET_PODF_MASK + |MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK ); +/* PLL2 PFD2 */ + reg |= (4 <<MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET ); +/* Div = 2*/ + reg |= (1 <<MXC_CCM_CHSCCDR_ENET_PODF_OFFSET ); + reg |= (0 <<MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET ); +writel (reg, &imx_ccm->chsccdr); + +/* Enable enet system clock */ + reg =readl (&imx_ccm->CCGR3); + reg |=MXC_CCM_CCGR3_ENET_MASK ; +writel (reg, &imx_ccm->CCGR3); +#endif return 0; }#endif
Signature · 1 line
1.9.1
PATCH 1/2 mx6sx: Adjust enable_fec_anatop_clock() for mx6solox
Hi Fabio,
Quoted 32 lines · Fabio Estevam
From: Fabio Estevam <[email protected]>
Configure and enable the ethernet clock for mx6solox.
Signed-off-by Fabio Estevam <[email protected]>--- arch/arm/cpu/armv7/mx6/clock.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)arch/arm/cpu/armv7/mx6/clock.c +14
-0@@ -373,6 +373,27 @@ int enable_fec_anatop_clock(enum enet_freq freq) reg &= ~BM_ANADIG_PLL_ENET_BYPASS ;writel (reg, &anatop->pll_enet); +#ifdef CONFIG_MX6SX +/* +* Set enet ahb clock to 200MHz +* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB +*/ + reg =readl (&imx_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK + |MXC_CCM_CHSCCDR_ENET_PODF_MASK + |MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK ); +/* PLL2 PFD2 */ + reg |= (4 <<MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET ); +/* Div = 2*/ + reg |= (1 <<MXC_CCM_CHSCCDR_ENET_PODF_OFFSET ); + reg |= (0 <<MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET );
arch/arm/cpu/armv7/mx6/clock.c int enable_fec_anatop_clock(enum enet_freq freq) · line 399
Quoted 10 lines
arch/arm/cpu/armv7/mx6/clock.c +7
-0+writel (reg, &imx_ccm->chsccdr); + +/* Enable enet system clock */ + reg =readl (&imx_ccm->CCGR3); + reg |=MXC_CCM_CCGR3_ENET_MASK ; +writel (reg, &imx_ccm->CCGR3); +#endif return 0; }#endif
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================
PATCH 2/2 mx6sxsabresd: Add Ethernet support
In reply to Fabio EstevamHi Fabio,
Quoted 4 lines · Fabio Estevam
From: Fabio Estevam <[email protected]>
mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.
Quoted 9 lines
Add support for one FEC port initially.
Signed-off-by Fabio Estevam <[email protected]>---
FEC is not functional after this series.There is still another patch for FEC that I will submit later that makes FEC functional on mx6solox, but it is orthogonal to this series.
This is ok for me. Please feel free to send the additional patch fixing FEC behavior.
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================