arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support

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new file mode 100644
index 0000000..834aa53
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_LS1_SERDES_H
+#define __FSL_LS1_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+#endif /* __FSL_LS1_SERDES_H */

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new file mode 100644
index 0000000..fd36bb0
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
+#define __ASM_ARCH_LS102XA_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */

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new file mode 100644
index 0000000..3a92f5a
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	SATA1,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+
+#endif /* __FSL_SERDES_H */

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index 5f2a5f4..2f1e0a1 100644
@@ -23,4 +23,8 @@
 #include <asm/arch-fsl-lsch3/config.h>
 #endif
 
+#ifdef CONFIG_LS102xA
+#include <asm/arch/config.h>
+#endif
+
 #endif

index 6d18eb3..e60ed73 100644
@@ -376,7 +376,12 @@ out:
 	return retval;
 }
 
-#elif !defined(readb)
+#else
+#define memset_io(a, b, c)		memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)		memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)		memcpy((void *)(a), (b), (c))
+
+#if !defined(readb)
 
 #define readb(addr)			(__readwrite_bug("readb"),0)
 #define readw(addr)			(__readwrite_bug("readw"),0)

@@ -389,6 +394,7 @@ out:
 
 #define check_signature(io,sig,len)	(0)
 
+#endif
 #endif	/* __mem_pci */
 
 /*

index c14797c..83a9ffa 100644
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
 	(void *)IMX_I2C2_BASE
 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||	\
-	defined(CONFIG_MX6)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
 	(void *)I2C1_BASE_ADDR,
 	(void *)I2C2_BASE_ADDR,
 	(void *)I2C3_BASE_ADDR

@@ -545,7 +545,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 			 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
 	defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
-	defined(CONFIG_MX6)
+	defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 			 mxc_i2c_read, mxc_i2c_write,
 			 mxc_i2c_set_bus_speed,

deleted file mode 100644
index 96146b6..0000000
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include <phy.h>
-
-struct tsec_mii_mng {
-	u32 miimcfg;		/* MII management configuration reg */
-	u32 miimcom;		/* MII management command reg */
-	u32 miimadd;		/* MII management address reg */
-	u32 miimcon;		/* MII management control reg */
-	u32 miimstat;		/* MII management status reg  */
-	u32 miimind;		/* MII management indication reg */
-	u32 ifstat;		/* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */

index ac96163..5ff9dff 100644
@@ -11,13 +11,13 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <phy.h>
+#include <fsl_mdio.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
 #include <spd_sdram.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/mmu.h>
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>

index 0a3c972..c749e55 100644
@@ -10,7 +10,6 @@
 #include <i2c.h>
 #include <asm/io.h>
 #include <asm/fsl_mpc83xx_serdes.h>
-#include <asm/fsl_enet.h>
 #include <spd_sdram.h>
 #include <tsec.h>
 #include <libfdt.h>

index 78bbd43..8d3dc0e 100644
@@ -7,7 +7,6 @@
 #include <common.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_dtsec.h>
 #include <fsl_mdio.h>
 #include <phy.h>

index 316e06e..a9691c6 100644
@@ -8,8 +8,8 @@
 #define __FM_H__
 
 #include <common.h>
+#include <phy.h>
 #include <fm_eth.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_fman.h>
 
 /* Port ID */

index ff04695..6cf21c6 100644
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
+#include <fsl_mdio.h>
 
 #include "fm.h"
 

index 592a67f..9499290 100644
@@ -12,7 +12,6 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_memac.h>
 
 #include "fm.h"

index f450f80..5017123 100644
@@ -12,7 +12,6 @@
 #include <phy.h>
 #include <asm/types.h>
 #include <asm/io.h>
-#include <asm/fsl_enet.h>
 #include <asm/fsl_tgec.h>
 
 #include "fm.h"

index 1d88e65..8d09f5d 100644
@@ -11,7 +11,6 @@
 #include <fsl_mdio.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/fsl_enet.h>
 
 void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 		int dev_addr, int regnum, int value)

index 48a1634..6b559f7 100644
@@ -13,7 +13,6 @@
 #include "qe.h"
 #include "uccf.h"
 #include <phy.h>
-#include <asm/fsl_enet.h>
 
 #define MAX_TX_THREADS				8
 #define MAX_RX_THREADS				8

index 98edfcf..e46a684 100644
@@ -8,8 +8,8 @@
 #define __FM_ETH_H__
 
 #include <common.h>
+#include <phy.h>
 #include <asm/types.h>
-#include <asm/fsl_enet.h>
 
 enum fm_port {
 	FM1_DTSEC1,

index b58713d..a531edf 100644
@@ -10,7 +10,18 @@
 
 #include <net.h>
 #include <miiphy.h>
-#include <asm/fsl_enet.h>
+
+struct tsec_mii_mng {
+	u32 miimcfg;		/* MII management configuration reg */
+	u32 miimcom;		/* MII management command reg */
+	u32 miimadd;		/* MII management address reg */
+	u32 miimcon;		/* MII management control reg */
+	u32 miimstat;		/* MII management status reg  */
+	u32 miimind;		/* MII management indication reg */
+	u32 ifstat;		/* Interface Status Register */
+} __packed;
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
 
 /* PHY register offsets */
 #define PHY_EXT_PAGE_ACCESS	0x1f

index 1046426..2054715 100644
@@ -20,7 +20,7 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <asm/fsl_enet.h>
+#include <fsl_mdio.h>
 
 #define TSEC_SIZE 		0x01000
 #define TSEC_MDIO_OFFSET	0x01000

index 8d09f5d..6eae78f 100644
@@ -98,8 +98,13 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
 		return -1;
 	}
 
-	bus->read = tsec_phy_read;
-	bus->write = tsec_phy_write;
+	if (info->priv_mdio_read) {
+		bus->read = info->priv_mdio_read;
+		bus->write = info->priv_mdio_write;
+	} else {
+		bus->read = tsec_phy_read;
+		bus->write = tsec_phy_write;
+	}
 	bus->reset = fsl_pq_mdio_reset;
 	sprintf(bus->name, info->name);
 

index a531edf..633123c 100644
@@ -57,6 +57,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 struct fsl_pq_mdio_info {
 	struct tsec_mii_mng __iomem *regs;
 	char *name;
+	int (*priv_mdio_read)(struct mii_dev *bus, int addr,
+			      int devad, int reg);
+	int (*priv_mdio_write)(struct mii_dev *bus, int addr, int devad,
+			       int reg, u16 val);
 };
 int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
 

index 6eae78f..2657c44 100644
@@ -19,7 +19,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 
 	out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
 	out_be32(&phyregs->miimcon, value);
-	asm("sync");
+	mb();
 
 	while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
 		;

@@ -37,11 +37,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
 
 	/* Clear the command register, and wait */
 	out_be32(&phyregs->miimcom, 0);
-	asm("sync");
+	mb();
 
 	/* Initiate a read command, and wait */
 	out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
-	asm("sync");
+	mb();
 
 	/* Wait for the the indication that the read is done */
 	while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))

index e9138f0..a220221 100644
@@ -20,6 +20,7 @@
 #include <fsl_mdio.h>
 #include <asm/errno.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 
 	do {
 		uint16_t status;

@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
 	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+	setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
 }
 
 /* This returns the status bits of the device.	The return value

index 2054715..5b74f67 100644
@@ -20,10 +20,14 @@
 #include <net.h>
 #include <config.h>
 #include <phy.h>
-#include <fsl_mdio.h>
 
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE		0x40000
+#define TSEC_MDIO_OFFSET	0x40000
+#else
 #define TSEC_SIZE 		0x01000
 #define TSEC_MDIO_OFFSET	0x01000
+#endif
 
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
 

@@ -128,6 +132,7 @@
 #define DMACTRL_INIT_SETTINGS	0x000000c3
 #define DMACTRL_GRS		0x00000010
 #define DMACTRL_GTS		0x00000008
+#define DMACTRL_LE		0x00008000
 
 #define TSTAT_CLEAR_THALT	0x80000000
 #define RSTAT_CLEAR_RHALT	0x00800000

index 5541613..aec459f 100644
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102xA)
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif

@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
 	voltage_caps = 0;
-	caps = regs->hostcapblt;
+	caps = esdhc_read32(&regs->hostcapblt);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |

index 9814964..c1b6648 100644
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
 };
 
 /* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32            in_be32
+#define esdhc_write32           out_be32
+#define esdhc_clrsetbits32      clrsetbits_be32
+#define esdhc_clrbits32         clrbits_be32
+#define esdhc_setbits32         setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
 #define esdhc_read32		in_le32
 #define esdhc_write32		out_le32
 #define esdhc_clrsetbits32	clrsetbits_le32

index 04e4178..5e0ee77 100644
@@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int x32_en = 0;	/* x32 enable */
 	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
 	unsigned int hse;		/* Global half strength override */
+	unsigned int acc_ecc_en = 0;	/* Accumulated ECC enable */
 	unsigned int mem_halt = 0;	/* memory controller halt */
 	unsigned int bi = 0;		/* Bypass initialization */
 

@@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	ba_intlv_ctl = popts->ba_intlv_ctl;
 	hse = popts->half_strength_driver_enable;
 
+	/* set when ddr bus width < 64 */
+	acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
+
 	ddr->ddr_sdram_cfg = (0
 			| ((mem_en & 0x1) << 31)
 			| ((sren & 0x1) << 30)

@@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			| ((x32_en & 0x1) << 5)
 			| ((pchb8 & 0x1) << 4)
 			| ((hse & 0x1) << 3)
+			| ((acc_ecc_en & 0x1) << 2)
 			| ((mem_halt & 0x1) << 1)
 			| ((bi & 0x1) << 0)
 			);

index d4ed9ae..59f2fd6 100644
@@ -194,7 +194,7 @@ step2:
 	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 	 * Let's wait for 800ms
 	 */
-	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 			>> SDRAM_CFG_DBW_SHIFT);
 	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 		(get_ddr_freq(0) >> 20)) << 1;

index 5e0ee77..d9cac22 100644
@@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	if (ip_rev > 0x40400)
 		unq_mrs_en = 1;
 
+	if (ip_rev > 0x40700)
+		ddr->debug[18] = popts->cswl_override;
+
 	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
 	set_ddr_sdram_mode(ddr, popts, common_dimm,
 				cas_latency, additive_latency, unq_mrs_en);

index 7fb4187..6aa16b2 100644
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(wrlvl_override),
 		CTRL_OPTIONS(wrlvl_sample),
 		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS(cswl_override),
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),

@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(wrlvl_override),
 		CTRL_OPTIONS(wrlvl_sample),
 		CTRL_OPTIONS(wrlvl_start),
+		CTRL_OPTIONS_HEX(cswl_override),
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),

index e8a2db9..987119b 100644
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
 #define DDR_DATA_BUS_WIDTH_64 0
 #define DDR_DATA_BUS_WIDTH_32 1
 #define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0	0x04000001
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller

@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
 	unsigned int cpo_override;
 	unsigned int write_data_delay;		/* DQS adjust */
 
+	unsigned int cswl_override;
 	unsigned int wrlvl_override;
 	unsigned int wrlvl_sample;		/* Write leveling */
 	unsigned int wrlvl_start;

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new file mode 100644
index 0000000..09b3be2
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1021AQDS_QIXIS_H__
+#define __LS1021AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1021AQDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#define QIXIS_SRDS1CLK_100		0x0
+
+#endif

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index 5b74f67..1f0c233 100644
@@ -129,7 +129,11 @@
 
 #define MINFLR_INIT_SETTINGS	0x00000040
 
+#ifdef CONFIG_LS102xA
+#define DMACTRL_INIT_SETTINGS	0x00000003
+#else
 #define DMACTRL_INIT_SETTINGS	0x000000c3
+#endif
 #define DMACTRL_GRS		0x00000010
 #define DMACTRL_GTS		0x00000008
 #define DMACTRL_LE		0x00008000

index da5f9a2..6e639b7 100644
@@ -17,10 +17,34 @@
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
 
+#define STAT_LBKDIF	(1 << 31)
+#define STAT_RXEDGIF	(1 << 30)
+#define STAT_TDRE	(1 << 23)
+#define STAT_RDRF	(1 << 21)
+#define STAT_IDLE	(1 << 20)
+#define STAT_OR		(1 << 19)
+#define STAT_NF		(1 << 18)
+#define STAT_FE		(1 << 17)
+#define STAT_PF		(1 << 16)
+#define STAT_MA1F	(1 << 15)
+#define STAT_MA2F	(1 << 14)
+#define STAT_FLAGS	(STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+			STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE		(1 << 19)
+#define CTRL_RE		(1 << 18)
+
+#define FIFO_TXFE		0x80
+#define FIFO_RXFE		0x40
+
+#define WATER_TXWATER_OFF	1
+#define WATER_RXWATER_OFF	16
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
 
+#ifndef CONFIG_LPUART_32B_REG
 static void lpuart_serial_setbrg(void)
 {
 	u32 clk = mxc_get_clock(MXC_UART_CLK);

@@ -107,13 +131,111 @@ static struct serial_device lpuart_serial_drv = {
 	.getc = lpuart_serial_getc,
 	.tstc = lpuart_serial_tstc,
 };
+#else
+static void lpuart32_serial_setbrg(void)
+{
+	u32 clk = CONFIG_SYS_CLK_FREQ;
+	u32 sbr;
+
+	if (!gd->baudrate)
+		gd->baudrate = CONFIG_BAUDRATE;
+
+	sbr = (clk / (16 * gd->baudrate));
+	/* place adjustment later - n/32 BRFA */
+
+	out_be32(&base->baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+	u32 stat;
+
+	while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
+		out_be32(&base->stat, STAT_FLAGS);
+		WATCHDOG_RESET();
+	}
+
+	return in_be32(&base->data) & 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+	if (c == '\n')
+		serial_putc('\r');
+
+	while (!(in_be32(&base->stat) & STAT_TDRE))
+		WATCHDOG_RESET();
+
+	out_be32(&base->data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+	if ((in_be32(&base->water) >> 24) == 0)
+		return 0;
+
+	return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+	u8 ctrl;
+
+	ctrl = in_be32(&base->ctrl);
+	ctrl &= ~CTRL_RE;
+	ctrl &= ~CTRL_TE;
+	out_be32(&base->ctrl, ctrl);
+
+	out_be32(&base->modir, 0);
+	out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+	out_be32(&base->match, 0);
+	/* provide data bits, parity, stop bit, etc */
+
+	serial_setbrg();
+
+	out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
+
+	return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+	.name = "lpuart32_serial",
+	.start = lpuart32_serial_init,
+	.stop = NULL,
+	.setbrg = lpuart32_serial_setbrg,
+	.putc = lpuart32_serial_putc,
+	.puts = default_serial_puts,
+	.getc = lpuart32_serial_getc,
+	.tstc = lpuart32_serial_tstc,
+};
+#endif
+void lpuart32_serial_initialize(void)
+{
+	serial_register(&lpuart32_serial_drv);
+}
 
 void lpuart_serial_initialize(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+	serial_register(&lpuart32_serial_drv);
+#else
 	serial_register(&lpuart_serial_drv);
+#endif
 }
 
 __weak struct serial_device *default_serial_console(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+	return &lpuart32_serial_drv;
+#else
 	return &lpuart_serial_drv;
+#endif
 }

index 856fdfc..5a8bf21 100644
@@ -279,11 +279,16 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Serial Port
  */
+#ifdef CONFIG_LETECH
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
 
 #define CONFIG_BAUDRATE			115200
 

@@ -367,11 +372,19 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTDELAY		3
 
+#ifdef CONFIG_LETECH
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+	"fdt_high=0xcfffffff\0"		\
+	"initrd_high=0xcfffffff\0"      \
+	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 	"fdt_high=0xcfffffff\0"		\
 	"initrd_high=0xcfffffff\0"      \
 	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#endif
 
 /*
  * Miscellaneous configurable options

index f8cbe32..b268a70 100644
@@ -147,11 +147,16 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Serial Port
  */
+#ifdef CONFIG_LETECH
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
 
 #define CONFIG_BAUDRATE			115200
 

@@ -228,10 +233,17 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTDELAY		3
 
+#ifdef CONFIG_LETECH
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+	"initrd_high=0xcfffffff\0"      \
+	"fdt_high=0xcfffffff\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 	"initrd_high=0xcfffffff\0"      \
 	"fdt_high=0xcfffffff\0"
+#endif
 
 /*
  * Miscellaneous configurable options

153 lines not on this page · raw message

new file mode 100644
index 0000000..de76733
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __DCU_HDMI_SII9022A__
+#define __DCU_HDMI_SII9022A__
+
+/* Programming of Silicon SII9022A connector HDMI Transmitter*/
+int dcu_set_dvi_encoder(struct fb_videomode *videomode);
+
+#endif

index ddc747f..dfc5668 100644
@@ -21,6 +21,7 @@
 #define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
 
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000

@@ -57,6 +58,9 @@
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_DCU_BE
+
+#define DCU_LAYER_MAX_NUM			16
 
 #define CONFIG_SYS_FSL_SRDS_1
 

365 lines not on this page · raw message

new file mode 100644
index 0000000..4263298
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <linux/fb.h>
+
+int fsl_dcu_init(unsigned int xres, unsigned int yres,
+		 unsigned int pixel_format);
+
+/* Prototypes for external board-specific functions */
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port, struct fb_videomode *dcu_fb_videomode);
+unsigned int dcu_set_pixel_clock(unsigned int pixclock);

47 lines not on this page · raw message

index 7fdcbcd..e4364dd 100644
@@ -264,6 +264,12 @@ int board_early_init_f(void)
 	init_early_memctl_regs();
 #endif
 
+#ifdef CONFIG_FSL_DCU_FB
+	out_be32(&scfg->scfgrevcr, 0xffffffff);
+	out_be32(&scfg->pixclkcr, 0x80000000);
+	out_be32(&scfg->scfgrevcr, 0x00000000);
+#endif
+
 	out_le32(&cci->ctrl_ord, 0x00000008);
 
 	return 0;

index b268a70..fb2cf08 100644
@@ -182,6 +182,24 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_GENERIC_MMC
 
 /*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DCU_SII9022A
+#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
+#define CONFIG_SYS_I2C_DVI_ADDR		0x39
+#endif
+
+/*
  * eTSEC
  */
 #define CONFIG_TSEC_ENET