mx6: imx-regs: Provide a structure for GPC registers

PATCH New Fabio Estevam 2 participants 7 messages Aug 24, 2014 – Aug 25, 2014

Subsystems (3)

Arm (32-bit) Arm i.MX and Layerscape PCI

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Fabio Estevam

author reviewer

2014-08-24 17:52 UTC #0 lore raw

PATCH v2 1/3 mx6: imx-regs: Provide a structure for GPC registers

From: Fabio Estevam <[email protected]>

Introduce a structure for accessing the General Power Controller block (GPC) registers.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- None

 arch/arm/include/asm/arch-mx6/imx-regs.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

arch/arm/include/asm/arch-mx6/imx-regs.h +13 -0

index 2631beb..22614fc 100644
@@ -419,6 +419,19 @@ struct iomuxc {
 	u32 gpr[14];
 };
 
+struct gpc {
+	u32	cntr;
+	u32	pgr;
+	u32	imr1;
+	u32	imr2;
+	u32	imr3;
+	u32	imr4;
+	u32	isr1;
+	u32	isr2;
+	u32	isr3;
+	u32	isr4;
+};
+
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16

Signature · 1 line

1.9.1

Fabio Estevam

author reviewer

2014-08-24 17:52 UTC #1 lore raw

PATCH v2 2/3 pcie_imx: Add mx6solox support

From: Fabio Estevam <[email protected]>

Let PCI on mx6solox also be supported.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Put the definition of gpc inside CONFIG_MX6SX ifdef
- Use setbits_le32 to configure register CNTR
- Improve comments in the code

 arch/arm/cpu/armv7/mx6/clock.c        |  9 ++++++++
 arch/arm/include/asm/arch-mx6/iomux.h |  9 ++++++++
 drivers/pci/pcie_imx.c                | 40 +++++++++++++++++++++++++++++++----
 3 files changed, 54 insertions(+), 4 deletions(-)

arch/arm/cpu/armv7/mx6/clock.c +9 -0

index abd9d61..dd628d8 100644
@@ -504,10 +504,19 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+#ifndef CONFIG_MX6SX
+	/* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
 	clrsetbits_le32(&anatop_regs->ana_misc1,
 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+#else
+	/* lvds_clk1 is sourced from pcie ref on imx6sx */
+	clrsetbits_le32(&anatop_regs->ana_misc1,
+			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
+#endif
 
 	/* PCIe reference clock sourced from AXI. */
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);

arch/arm/include/asm/arch-mx6/iomux.h +9 -0

index 6a4a632..c86aa31 100644
@@ -19,6 +19,12 @@
 #define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
 
 /*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST			(1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST			(1 << 18)
+
+/*
  * IOMUXC_GPR8 bit fields
  */
 #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)

@@ -35,12 +41,15 @@
 /*
  * IOMUXC_GPR12 bit fields
  */
+#define IOMUXC_GPR12_RX_EQ_2			(0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK			(0x7 << 0)
 #define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
 #define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN		(1 << 30)
 
 /*
  * IOMUXC_GPR13 bit fields

drivers/pci/pcie_imx.c +36 -4

index a3982c4..194da2e 100644
@@ -23,13 +23,20 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
+#ifdef CONFIG_MX6SX
+#define MX6_DBI_ADDR	0x08ffc000
+#define MX6_IO_ADDR	0x08000000
+#define MX6_MEM_ADDR	0x08100000
+#define MX6_ROOT_ADDR	0x08f00000
+#else
 #define MX6_DBI_ADDR	0x01ffc000
-#define MX6_DBI_SIZE	0x4000
 #define MX6_IO_ADDR	0x01000000
-#define MX6_IO_SIZE	0x100000
 #define MX6_MEM_ADDR	0x01100000
-#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_ADDR	0x01f00000
+#endif
+#define MX6_DBI_SIZE	0x4000
+#define MX6_IO_SIZE	0x100000
+#define MX6_MEM_SIZE	0xe00000
 #define MX6_ROOT_SIZE	0xfc000
 
 /* PCIe Port Logic registers (memory-mapped) */

@@ -57,6 +64,8 @@
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
+#define PCIE_PHY_PUP_REQ		(1 << 7)
+
 /* iATU registers */
 #define PCIE_ATU_VIEWPORT		0x900
 #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)

@@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
+#if defined(CONFIG_MX6SX)
+	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+	/* SSP_EN is not used on MX6SX anymore */
+	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Force PCIe PHY reset */
+	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+	/* Power up PCIe PHY */
+	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+#else
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	return 0;
 }

@@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void)
 			IOMUXC_GPR12_LOS_LEVEL_MASK,
 			IOMUXC_GPR12_LOS_LEVEL_9);
 
+#ifdef CONFIG_MX6SX
+	clrsetbits_le32(&iomuxc_regs->gpr[12],
+			IOMUXC_GPR12_RX_EQ_MASK,
+			IOMUXC_GPR12_RX_EQ_2);
+#endif
+
 	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
 	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
 	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |

@@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void)
 	 */
 	mdelay(50);
 
+#if defined(CONFIG_MX6SX)
+	/* SSP_EN is not used on MX6SX anymore */
+	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+	/* Clear PCIe PHY reset bit */
+	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+#else
 	/* Enable PCIe */
 	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
+#endif
 
 	imx6_pcie_toggle_reset();

Signature · 1 line

1.9.1

Marek Vasut

2014-08-25 07:54 UTC #2 lore raw

PATCH v2 2/3 pcie_imx: Add mx6solox support

On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote:

[...]

Quoted 9 lines

arch/arm/cpu/armv7/mx6/clock.c +2 -0

@@ -504,10 +504,19 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
+#ifndef CONFIG_MX6SX
+	/* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
 	clrsetbits_le32(&anatop_regs->ana_misc1,

arch/arm/cpu/armv7/mx6/clock.c int enable_pcie_clock(void) · line 519

Quoted 10 lines

arch/arm/cpu/armv7/mx6/clock.c +7 -0

 			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+#else
+	/* lvds_clk1 is sourced from pcie ref on imx6sx */
+	clrsetbits_le32(&anatop_regs->ana_misc1,
+			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
+#endif

Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for please ?

arch/arm/cpu/armv7/mx6/clock.c int enable_pcie_clock(void) · line 522

Quoted 2 lines

arch/arm/cpu/armv7/mx6/clock.c +0 -0

 	/* PCIe reference clock sourced from AXI. */
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);

[...]

Best regards,
Marek Vasut

Fabio Estevam

author reviewer

2014-08-25 13:54 UTC #3 lore raw

PATCH v2 2/3 pcie_imx: Add mx6solox support

Quoted 18 lines · Marek Vasut

On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote:

[...]

Quoted 14 lines

arch/arm/cpu/armv7/mx6/clock.c +4 -0

@@ -504,10 +504,19 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN               (1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN               (1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK  0x0000001F
+#ifndef CONFIG_MX6SX
+     /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
      clrsetbits_le32(&anatop_regs->ana_misc1,
                      ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
                      ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
                      ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
+#else
+     /* lvds_clk1 is sourced from pcie ref on imx6sx */

Quoted 8 lines

arch/arm/cpu/armv7/mx6/clock.c int enable_pcie_clock(void) · line 519
Quoted 5 lines
arch/arm/cpu/armv7/mx6/clock.c +5 -0
+     clrsetbits_le32(&anatop_regs->ana_misc1,
+                     ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+                     ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+                     ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
+#endif
Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for please ?

Correct.

0xa means that LVDS1_CLK_SEL comes from PCIE_REF ? PCIe ref clock

0xb means that LVDS1_CLK_SEL comes from SATA_REF ? SATA ref clock

In this patch I have added comments for both cases, so hopefully it is clear.

Marek Vasut

2014-08-25 14:27 UTC #4 lore raw

PATCH v2 2/3 pcie_imx: Add mx6solox support

Quoted 33 lines · Fabio Estevam

Quoted 21 lines · Marek Vasut

On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote:

[...]

Quoted 17 lines

arch/arm/cpu/armv7/mx6/clock.c +2 -0

@@ -504,10 +504,19 @@ int enable_pcie_clock(void)
 
 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN               (1 << 12)
 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN               (1 << 10)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK  0x0000001F
 
+#ifndef CONFIG_MX6SX
+     /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */
 
      clrsetbits_le32(&anatop_regs->ana_misc1,
 
                      ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
                      ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
                      ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);

Quoted 10 lines

arch/arm/cpu/armv7/mx6/clock.c int enable_pcie_clock(void) · line 519

Quoted 7 lines

arch/arm/cpu/armv7/mx6/clock.c +7 -0

+#else
+     /* lvds_clk1 is sourced from pcie ref on imx6sx */
+     clrsetbits_le32(&anatop_regs->ana_misc1,
+                     ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
+                     ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
+                     ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa);
+#endif

Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for please ?

Quoted 8 lines

Correct.
0xa means that LVDS1_CLK_SEL comes from PCIE_REF ? PCIe ref clock
0xb means that LVDS1_CLK_SEL comes from SATA_REF ? SATA ref clock
In this patch I have added comments for both cases, so hopefully it is clear.

Can you maybe pull the mask out and just ORR it with the correct bit in the ifdef ? Or -- even better, can this not be done at runtime ?

Best regards,
Marek Vasut

Fabio Estevam

author reviewer

2014-08-25 17:29 UTC #5 lore raw

PATCH v2 2/3 pcie_imx: Add mx6solox support

Quoted 2 lines · Marek Vasut

Can you maybe pull the mask out and just ORR it with the correct bit in the ifdef ? Or -- even better, can this not be done at runtime ?

Yes, I implemented the run-time approach in v3. Thanks

Fabio Estevam

author reviewer

2014-08-24 17:52 UTC #6 lore raw

PATCH v2 3/3 mx6sxsabresd: Add PCI support

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Tested with an Intel Wireless PCI 7260HMW card:

U-Boot 2014.10-rc1-16576-g4a8a8a8-dirty (Aug 23 2014 - 16:05:11)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz                                      
Reset cause: WDOG                                                               
Board: MX6SX SABRE SDB                                                          
I2C:   ready                                                                    
DRAM:  1 GiB                                                                    
MMC:   FSL_SDHC: 0

00:01.0 - 16c3:abcd - Bridge device
01:00.0 - 8086:08b1 - Network controller

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- None

 include/configs/mx6sxsabresd.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

include/configs/mx6sxsabresd.h +10 -0

index 7967b5d..467c125 100644
@@ -181,6 +181,16 @@
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
 
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 1)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 0)
+#endif
+
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH

Signature · 1 line

1.9.1