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net: can: Use syscon regmap for TI specific RAMINIT register

PATCH Superseded Roger Quadros 4 participants 35 messages Sep 9, 2014 – Oct 1, 2014

Subsystems (4)
Networking Network drivers Device tree bindings CAN network drivers

v2 of 8 Superseded Latest is v8 →

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Roger Quadros

author
#0 lore raw

v2 cover net: can: Use syscon regmap for TI specific RAMINIT register

Hi,

Some hardware (TI am43xx) has a buggy RAMINIT DONE mechanism and it might not always set the DONE bit. This will result in a lockup in c_can_hw_raminit_wait_ti(), so patch 1 adds a timeout mechanism there.

There is a non compliancy within TI platforms with respect to the layout of the RAMINIT register. The patches 2 and 3 address this issue and make a flexible but standard way of defining the RAMINIT hardware register layout in the device tree. The RAMINIT register is accessed using the syscon regmap framework.

Patches available at
[email protected]:rogerq/linux.git [for-v3.18/can]

Changelog:

v2:
- added "ti" vendor prefix to TI specific raminit properties.
- split DTS changes into a separate series

cheers,
-roger
---

Roger Quadros (3):
can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout
net: can: c_can: Add syscon/regmap RAMINIT mechanism
net: can: c_can: Add support for START pulse in RAMINIT sequence

 .../devicetree/bindings/net/can/c_can.txt          |  10 ++
 drivers/net/can/c_can/c_can.h                      |  12 +-
 drivers/net/can/c_can/c_can_platform.c             | 123 ++++++++++++++++-----
 3 files changed, 114 insertions(+), 31 deletions(-)
Signature · 1 line
1.8.3.2
author
#1 lore raw

PATCH v2 1/3 can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti(). They seem to have been swapped in the usage instances.

TI's RAMINIT DONE mechanism is buggy and may not always be set after the START bit is set. So add a timeout mechanism to c_can_hw_raminit_wait_ti().

Signed-off-by Roger Quadros <[email protected]>
---
 drivers/net/can/c_can/c_can_platform.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)
drivers/net/can/c_can/c_can_platform.c +11 -3
index 109cb44..b144e71 100644
@@ -75,10 +75,18 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
 				  u32 val)
 {
+	int timeout = 0;
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {
+			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
+			break;
+		}
+	}
 }
 
 static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)

@@ -97,14 +105,14 @@ static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
 	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
 	writel(ctrl, priv->raminit_ctrlreg);
 	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-	c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
 		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
 		writel(ctrl, priv->raminit_ctrlreg);
 		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+		c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 	}
 	spin_unlock(&raminit_lock);
 }
Signature · 1 line
1.8.3.2
maintainer
#2 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

Quoted 2 lines · Roger Quadros

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti(). They seem to have been swapped in the usage instances.

Can you split this fix into a seperate patch, please.

Quoted 3 lines

TI's RAMINIT DONE mechanism is buggy and may not always be set after the START bit is set. So add a timeout mechanism to c_can_hw_raminit_wait_ti().

What should happen if the timeout occurs?

Marc

Signature · 4 lines
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |
author
#3 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

Quoted 5 lines · Marc Kleine-Budde
Quoted 2 lines · Roger Quadros

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti(). They seem to have been swapped in the usage instances.

Can you split this fix into a seperate patch, please.

OK.

Quoted 6 lines
Quoted 4 lines

TI's RAMINIT DONE mechanism is buggy and may not always be set after the START bit is set. So add a timeout mechanism to c_can_hw_raminit_wait_ti().

What should happen if the timeout occurs?

I'm not sure yet. I will verify if the hardware still works or not in that case. If it doesn't work then we should fail.

cheers,
-roger

maintainer
#4 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

Quoted 8 lines · Roger Quadros
Quoted 5 lines · Marc Kleine-Budde
Quoted 2 lines · Roger Quadros

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti(). They seem to have been swapped in the usage instances.

Can you split this fix into a seperate patch, please.

OK.

I've added this fix only to the can-tree.

Thanks,
Marc

Signature · 4 lines
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |
#5 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

In reply to Roger Quadros
Quoted 19 lines · Roger Quadros

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti(). They seem to have been swapped in the usage instances.

TI's RAMINIT DONE mechanism is buggy and may not always be set after the START bit is set. So add a timeout mechanism to c_can_hw_raminit_wait_ti().

Signed-off-by Roger Quadros <[email protected]>
---
 drivers/net/can/c_can/c_can_platform.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)
drivers/net/can/c_can/c_can_platform.c +0 -0
index 109cb44..b144e71 100644
@@ -75,10 +75,18 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
 				  u32 val)

drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, · line 85

Quoted 10 lines
drivers/net/can/c_can/c_can_platform.c +5 -1
 {
+	int timeout = 0;
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {

How did we come up with this number?

drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, · line 87

Quoted 2 lines
drivers/net/can/c_can/c_can_platform.c +2 -0
+			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
+			break;

lets say we did timeout..
see below:

Quoted 9 lines
drivers/net/can/c_can/c_can_platform.c +2 -0
+		}
+	}
 }
 
 static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)

@@ -97,14 +105,14 @@ static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
 	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
 	writel(ctrl, priv->raminit_ctrlreg);
 	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);

drivers/net/can/c_can/c_can_platform.c static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable) · line 115

Quoted 10 lines
drivers/net/can/c_can/c_can_platform.c +2 -2
-	c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
 
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
 		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
 		writel(ctrl, priv->raminit_ctrlreg);
 		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+		c_can_hw_raminit_wait_ti(priv, mask, ctrl);

is it possible for us to continue? does it make sense for us to change that void to a int and handle error cascading?

Quoted 4 lines
drivers/net/can/c_can/c_can_platform.c +0 -0
 	}
 	spin_unlock(&raminit_lock);
 }
Signature · 2 lines
Regards,
Nishanth Menon
author
#6 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

Quoted 24 lines · Nishanth Menon
Quoted 23 lines · Roger Quadros

Pass the correct 'mask' and 'value' bits to c_can_hw_raminit_wait_ti(). They seem to have been swapped in the usage instances.

TI's RAMINIT DONE mechanism is buggy and may not always be set after the START bit is set. So add a timeout mechanism to c_can_hw_raminit_wait_ti().

Signed-off-by Roger Quadros <[email protected]>
---
 drivers/net/can/c_can/c_can_platform.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)
drivers/net/can/c_can/c_can_platform.c +1 -0
index 109cb44..b144e71 100644
@@ -75,10 +75,18 @@ static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
 static void c_can_hw_raminit_wait_ti(const struct c_can_priv *priv, u32 mask,
 				  u32 val)
 {
+	int timeout = 0;
 	/* We look only at the bits of our instance. */
 	val &= mask;
Quoted 8 lines

drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, · line 85

Quoted 6 lines
drivers/net/can/c_can/c_can_platform.c +4 -1
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {

How did we come up with this number?

wild guess ;), that it should be set in a few microseconds and the delay is not too large.

Till I don't hear from hardware guys, it will remain a guess.

Quoted 17 lines

drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, · line 87

Quoted 3 lines
drivers/net/can/c_can/c_can_platform.c +2 -0
+			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
+			break;

lets say we did timeout..
see below:

Quoted 12 lines
drivers/net/can/c_can/c_can_platform.c +3 -1
+		}
+	}
 }
 
 static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)

@@ -97,14 +105,14 @@ static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
 	ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
 	writel(ctrl, priv->raminit_ctrlreg);
 	ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
-	c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+	c_can_hw_raminit_wait_ti(priv, mask, ctrl);
Quoted 10 lines

drivers/net/can/c_can/c_can_platform.c static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable) · line 115

Quoted 7 lines
drivers/net/can/c_can/c_can_platform.c +1 -1
 	if (enable) {
 		/* Set start bit and wait for the done bit. */
 		ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
 		writel(ctrl, priv->raminit_ctrlreg);
 		ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
-		c_can_hw_raminit_wait_ti(priv, ctrl, mask);
+		c_can_hw_raminit_wait_ti(priv, mask, ctrl);

is it possible for us to continue? does it make sense for us to change that void to a int and handle error cascading?

I will verify this first to check if the hardware works or not in the failing case. Considering we never checked for the DONE bit in our earlier TI releases maybe it works.

But I'll verify and get back.

Quoted 7 lines

drivers/net/can/c_can/c_can_platform.c static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable) · line 118

Quoted 5 lines
drivers/net/can/c_can/c_can_platform.c +0 -0
 	}
 	spin_unlock(&raminit_lock);
 }

cheers,
-roger

#7 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

On 09/09/2014 09:45 AM, Roger Quadros wrote:
[...]

Quoted 11 lines
Quoted 10 lines

drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, · line 85

Quoted 8 lines
drivers/net/can/c_can/c_can_platform.c +4 -1
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {

How did we come up with this number?

Quoted 5 lines

wild guess ;), that it should be set in a few microseconds and the delay is not too large.

Till I don't hear from hardware guys, it will remain a guess.

in cases like these, I suggest using emperical data as point -> example doing some 10,000 iterations of the operation and picking up the worse case number and double it.

Either way, you need to document the same, else a few years down the line, when that number is in question, no one will know what it's basis was..

Signature · 2 lines
Regards,
Nishanth Menon
author
#8 lore raw

Re: [PATCH v2 1/3] can: c_can_platform: Fix c_can_hw_raminit_ti() and add timeout

Quoted 16 lines · Nishanth Menon

On 09/09/2014 09:45 AM, Roger Quadros wrote:
[...]

Quoted 14 lines
Quoted 10 lines

drivers/net/can/c_can/c_can_platform.c static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, · line 85

Quoted 8 lines
drivers/net/can/c_can/c_can_platform.c +4 -1
 	/* We look only at the bits of our instance. */
 	val &= mask;
-	while ((readl(priv->raminit_ctrlreg) & mask) != val)
+	while ((readl(priv->raminit_ctrlreg) & mask) != val) {
 		udelay(1);
+		timeout++;
+
+		if (timeout == 1000) {

How did we come up with this number?

wild guess ;), that it should be set in a few microseconds and the delay is not too large.

Quoted 6 lines
Quoted 2 lines

Till I don't hear from hardware guys, it will remain a guess.

in cases like these, I suggest using emperical data as point -> example doing some 10,000 iterations of the operation and picking up the worse case number and double it.

In my tests the bit was either set immediately or never at all. Not sure if we should increase it further.

Quoted 5 lines

Either way, you need to document the same, else a few years down the line, when that number is in question, no one will know what it's basis was..

OK. I'll add a comment there.

cheers,
-roger

author
#9 lore raw

PATCH v2 2/3 net: can: c_can: Add syscon/regmap RAMINIT mechanism

In reply to Roger Quadros

Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver.

To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register.

Signed-off-by Roger Quadros <[email protected]>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 109 +++++++++++++++------
 3 files changed, 95 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/net/can/c_can.txt +7 -0
index 8f1ae81..e12d1a1 100644
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- ti,raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
+
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
 Future plan is to migrate hwmod data base contents into device tree
drivers/net/can/c_can/c_can.h +9 -2
index 99ad1aa..bf68822 100644
@@ -169,6 +169,14 @@ enum c_can_dev_id {
 	BOSCH_D_CAN,
 };
 
+/* Out of band RAMINIT register access via syscon regmap */
+struct c_can_raminit {
+	struct regmap *syscon;	/* for raminit ctrl. reg. access */
+	unsigned int reg;	/* register index within syscon */
+	u8 start_bit;	/* START bit position in raminit reg. */
+	u8 done_bit;	/* DONE bit position in raminit reg. */
+};
+
 /* c_can private data structure */
 struct c_can_priv {
 	struct can_priv can;	/* must be the first member */

@@ -186,8 +194,7 @@ struct c_can_priv {
 	const u16 *regs;
 	void *priv;		/* for board-specific data */
 	enum c_can_dev_id type;
-	u32 __iomem *raminit_ctrlreg;
-	int instance;
+	struct c_can_raminit raminit_sys;	/* RAMINIT via syscon regmap */
 	void (*raminit) (const struct c_can_priv *priv, bool enable);
 	u32 comm_rcv_high;
 	u32 rxmasked;
drivers/net/can/c_can/c_can_platform.c +79 -30

170 lines not on this page · raw message

Signature · 1 line
1.8.3.2
#10 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 23 lines · Roger Quadros

Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver.

To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register.

Signed-off-by Roger Quadros <[email protected]>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 109 +++++++++++++++------
 3 files changed, 95 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/net/can/c_can.txt +0 -0
index 8f1ae81..e12d1a1 100644

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 7 lines
Documentation/devicetree/bindings/net/can/c_can.txt +4 -0
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- ti,raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 21

Quoted 2 lines
Documentation/devicetree/bindings/net/can/c_can.txt +2 -0
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register

This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...

author
#11 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 27 lines · Wolfram Sang
Quoted 26 lines · Roger Quadros

Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver.

To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register.

Signed-off-by Roger Quadros <[email protected]>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 109 +++++++++++++++------
 3 files changed, 95 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/net/can/c_can.txt +0 -0
index 8f1ae81..e12d1a1 100644
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
Quoted 6 lines

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 4 lines
Documentation/devicetree/bindings/net/can/c_can.txt +4 -0
+- ti,raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

I had used plain "syscon" in the earlier revisions but was asked to make it a TI specific property since only TI uses this mechanism.

Quoted 8 lines

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 21

Quoted 3 lines
Documentation/devicetree/bindings/net/can/c_can.txt +2 -0
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register

This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...

OK. I'll think of matching the compatible ID with SOC specific data in the driver.

cheers,
-roger

#12 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 10 lines
Quoted 7 lines

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 5 lines

+- ti,raminit-syscon : Handle to system control region that contains the

Documentation/devicetree/bindings/net/can/c_can.txt +3 -0
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

I had used plain "syscon" in the earlier revisions but was asked to make it a TI specific property since only TI uses this mechanism.

I see, when was that? Currently, it looks messy :( Grepping through the dts files in 3.17-rc7, I see that bcm7445 uses "syscon" and variants with prefixes, STE uses it, too. Samsung uses "samsung,syscon-phandle", st uses "st,syscon"...

The MACID readout patches for AM335x (just applied right now) also use "syscon": https://patchwork.ozlabs.org/patch/394289/

I'd vote for a generic "syscon" to be OK, yet I guess the DT maintainers will have the final word.

Quoted 8 lines
Quoted 7 lines
Quoted 2 lines
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register

This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...

OK. I'll think of matching the compatible ID with SOC specific data in the driver.

Great, thanks!

author
#13 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 16 lines · Wolfram Sang
Quoted 10 lines
Quoted 7 lines

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 5 lines

+- ti,raminit-syscon : Handle to system control region that contains the

Documentation/devicetree/bindings/net/can/c_can.txt +3 -0
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

I had used plain "syscon" in the earlier revisions but was asked to make it a TI specific property since only TI uses this mechanism.

I see, when was that? Currently, it looks messy :( Grepping through the dts files in 3.17-rc7, I see that bcm7445 uses "syscon" and variants with prefixes, STE uses it, too. Samsung uses "samsung,syscon-phandle", st uses "st,syscon"...

Quoted 5 lines

The MACID readout patches for AM335x (just applied right now) also use "syscon": https://patchwork.ozlabs.org/patch/394289/

I'd vote for a generic "syscon" to be OK, yet I guess the DT maintainers will have the final word.

Now that I actually checked, it was never just "syscon" but just without the "ti" vendor prefix. Sorry for the misinformation.

As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"?

cheers,
-roger

#14 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 2 lines

As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"?

Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we need an (optional) way to describe that. However, accessing syscon registers in general is not TI specific and a generic way to do this should be used. Which looks to me like the "syscon" property to allow access to the register. Still, we should ask DT maintainers about it, maybe they prefer a more precise property like "syscon-raminit" to allow for further syscon extensions later or something...

maintainer
#15 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 10 lines · Wolfram Sang
Quoted 2 lines

As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"?

Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we need an (optional) way to describe that. However, accessing syscon registers in general is not TI specific and a generic way to do this should be used. Which looks to me like the "syscon" property to allow access to the register. Still, we should ask DT maintainers about it, maybe they prefer a more precise property like "syscon-raminit" to allow for further syscon extensions later or something...

What do you think about putting the bit information in the syscon-raminit phandle as additional arguments?

Marc

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#16 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 12 lines · Marc Kleine-Budde
Quoted 10 lines · Wolfram Sang
Quoted 2 lines

As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"?

Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we need an (optional) way to describe that. However, accessing syscon registers in general is not TI specific and a generic way to do this should be used. Which looks to me like the "syscon" property to allow access to the register. Still, we should ask DT maintainers about it, maybe they prefer a more precise property like "syscon-raminit" to allow for further syscon extensions later or something...

Quoted 2 lines

What do you think about putting the bit information in the syscon-raminit phandle as additional arguments?

Then we'd have <n> syscon phandles for <n> instances?

Also, judging from Markus patch [1] there is already some infrastructure, namely syscon_regmap_lookup_by_phandle(). From a glimpse, it doesn't look viable to add such a support to it.

So, I'd rather drop additional arguments.

Why would you like to have it encoded in DT?

maintainer
#17 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 13 lines · Wolfram Sang
Quoted 12 lines · Marc Kleine-Budde
Quoted 10 lines · Wolfram Sang
Quoted 2 lines

As just TI is using this out of band RAMINIT mechanism, should it be "ti,syscon" or just "syscon"?

Yes, only TI uses this out-of-band RAMINIT (currently, at least). So, we need an (optional) way to describe that. However, accessing syscon registers in general is not TI specific and a generic way to do this should be used. Which looks to me like the "syscon" property to allow access to the register. Still, we should ask DT maintainers about it, maybe they prefer a more precise property like "syscon-raminit" to allow for further syscon extensions later or something...

Quoted 8 lines
Quoted 2 lines

What do you think about putting the bit information in the syscon-raminit phandle as additional arguments?

Then we'd have <n> syscon phandles for <n> instances?

Also, judging from Markus patch [1] there is already some infrastructure, namely syscon_regmap_lookup_by_phandle(). From a glimpse, it doesn't look viable to add such a support to it.

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

Quoted 3 lines

So, I'd rather drop additional arguments.

Why would you like to have it encoded in DT?

Where put the information then? Into the driver, but where do you get the reference which instance of the DCAN you are, so that you can look up the correct bits?

Marc

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#18 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

Phew... Then we should really have a "syscon-raminit" property probably, so that at least plain "syscon" has a consistent syntax?

Quoted 8 lines
Quoted 4 lines

So, I'd rather drop additional arguments.

Why would you like to have it encoded in DT?

Where put the information then? Into the driver, but where do you get the reference which instance of the DCAN you are, so that you can look up the correct bits?

Agreed. I thought we had this information in the driver already, but we haven't...

maintainer
#19 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 11 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

Quoted 2 lines

Phew... Then we should really have a "syscon-raminit" property probably, so that at least plain "syscon" has a consistent syntax?

I think^whope we can have the same syntax as the stmmc :D

Quoted 11 lines
Quoted 7 lines
Quoted 3 lines

So, I'd rather drop additional arguments.

Why would you like to have it encoded in DT?

Where put the information then? Into the driver, but where do you get the reference which instance of the DCAN you are, so that you can look up the correct bits?

Agreed. I thought we had this information in the driver already, but we haven't...

The current driver relies on the of_alias_get_id(), which isn't considered best practice, is it? So I want to avoid this when switching to syscon.

Marc

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author
#20 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 10 lines · Marc Kleine-Budde
Quoted 9 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

Quoted 6 lines
Quoted 2 lines

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

I'm sorry I didn't understand what you meant.

<&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances.

Quoted 5 lines
Quoted 3 lines

Phew... Then we should really have a "syscon-raminit" property probably, so that at least plain "syscon" has a consistent syntax?

I think^whope we can have the same syntax as the stmmc :D

I agree too.

Quoted 9 lines
Quoted 9 lines
Quoted 8 lines
Quoted 4 lines

So, I'd rather drop additional arguments.

Why would you like to have it encoded in DT?

Where put the information then? Into the driver, but where do you get the reference which instance of the DCAN you are, so that you can look up the correct bits?

Quoted 7 lines
Quoted 3 lines

Agreed. I thought we had this information in the driver already, but we haven't...

The current driver relies on the of_alias_get_id(), which isn't considered best practice, is it? So I want to avoid this when switching to syscon.

cheers,
-roger

maintainer
#21 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 14 lines · Roger Quadros
Quoted 13 lines · Marc Kleine-Budde
Quoted 11 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

Quoted 8 lines
Quoted 3 lines

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

I'm sorry I didn't understand what you meant.

<&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances.

What's start bit and stop bit for instance 0 and 1 on that SoC that has two instances??

Marc

Signature · 4 lines
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author
#22 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 19 lines · Marc Kleine-Budde
Quoted 18 lines · Roger Quadros
Quoted 16 lines · Marc Kleine-Budde
Quoted 11 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

Quoted 8 lines
Quoted 4 lines

I'm sorry I didn't understand what you meant.

<&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances.

What's start bit and stop bit for instance 0 and 1 on that SoC that has two instances??

we have 3 SoCs at the moment, all have 2 DCAN instances.

AM33xx & AM43xx
instance start stop
1 0 8
2 1 9

DRA7xx
instance start stop
1 3 1
2 5 2

cheers,
-roger

maintainer
#23 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 29 lines · Roger Quadros
Quoted 19 lines · Marc Kleine-Budde
Quoted 18 lines · Roger Quadros
Quoted 16 lines · Marc Kleine-Budde
Quoted 11 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

Quoted 8 lines
Quoted 4 lines

I'm sorry I didn't understand what you meant.

<&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances.

What's start bit and stop bit for instance 0 and 1 on that SoC that has two instances?

Quoted 6 lines

we have 3 SoCs at the moment, all have 2 DCAN instances.

AM33xx & AM43xx
instance start stop
1 0 8
2 1 9

If we use a 0-based numbering for the instances:
instance start stop
0 (0 << instance) (8 << instance)
1 (0 << instance) (8 << instance)

Quoted 4 lines

DRA7xx
instance start stop
1 3 1
2 5 2

                ^

5 or 4?

Marc

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author
#24 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 37 lines · Marc Kleine-Budde
Quoted 29 lines · Roger Quadros
Quoted 19 lines · Marc Kleine-Budde
Quoted 18 lines · Roger Quadros
Quoted 16 lines · Marc Kleine-Budde
Quoted 11 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

Quoted 8 lines
Quoted 4 lines

I'm sorry I didn't understand what you meant.

<&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances.

What's start bit and stop bit for instance 0 and 1 on that SoC that has two instances?

Quoted 6 lines

we have 3 SoCs at the moment, all have 2 DCAN instances.

AM33xx & AM43xx
instance start stop
1 0 8
2 1 9

Quoted 5 lines

If we use a 0-based numbering for the instances:
instance start stop
0 (0 << instance) (8 << instance)
1 (0 << instance) (8 << instance)

How does the instance number get set? What happens on boards where the first instance is unused while the second one is in use?

Quoted 6 lines
Quoted 4 lines

DRA7xx
instance start stop
1 3 1
2 5 2

                ^

5 or 4?

Unfortunately it is 5 ;)
We have display IP related bit in between 3 and 5 :P

cheers,
-roger

maintainer
#25 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 38 lines · Roger Quadros
Quoted 37 lines · Marc Kleine-Budde
Quoted 35 lines · Roger Quadros
Quoted 19 lines · Marc Kleine-Budde
Quoted 18 lines · Roger Quadros
Quoted 16 lines · Marc Kleine-Budde
Quoted 11 lines · Wolfram Sang
Quoted 8 lines

Yes, but syscon_regmap_lookup_by_phandle() doesn't need any support for additional parameters. Have a look at:

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

First get the regmap, then the 1st argument is the offset in the regmap, the 2nd and 3rd could be the bits.

So, for one driver the extra arguments are: <reg> <start_bit> <stop_bit> For another driver (the stmmac example): <reg_offset> <reg_shift>

The DCAN's "reg" is a "reg_offset" as in the stmmc.

Roger, can we derive both start and done bit from a common reg_shift?

Quoted 8 lines
Quoted 4 lines

I'm sorry I didn't understand what you meant.

<&syscon_phandl> <reg offset> <start bit> <stop bit> should work well for us. Even though reg offset is the same for both the DCAN instances.

What's start bit and stop bit for instance 0 and 1 on that SoC that has two instances?

we have 3 SoCs at the moment, all have 2 DCAN instances.

AM33xx & AM43xx
instance start stop
1 0 8
2 1 9

Quoted 8 lines
Quoted 5 lines

If we use a 0-based numbering for the instances:
instance start stop
0 (0 << instance) (8 << instance)
1 (0 << instance) (8 << instance)

How does the instance number get set? What happens on boards where the first instance is unused while the second one is in use?

Via a single "instance" parameter of the syscon phandle....

Quoted 10 lines
Quoted 7 lines
Quoted 5 lines

DRA7xx
instance start stop
1 3 1
2 5 2

                ^

5 or 4?

Unfortunately it is 5 ;)
We have display IP related bit in between 3 and 5 :P

What on earth were the HW engineers thinking????????????

...if we just have the instance parameter in the syscon phandle, we have to put the mapping into the driver, which makes IMHO no sense, because you have to touch the driver, if there is another SoC with the DCAN core.

AFAICS we have these options:
1) syscon phandle with three parameters:
reg offset, start bit shift, stop bit shift (the name of the syscon phandle is a different topic)
2) a single ti,start-stop-bit option with two parameter
3) two ti,* entries with a single parameter each (as in Roger's initial patch)

Wolfram, which solution do you prefer? I'm in favour of 3 (+ plus a phandle with a reg offset parameter).

puzzled,
Marc

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#26 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 5 lines
Quoted 3 lines

Unfortunately it is 5 ;)
We have display IP related bit in between 3 and 5 :P

What on earth were the HW engineers thinking????????????

"Let's test my RNG on the bit-placement of this register" :)

Quoted 3 lines

...if we just have the instance parameter in the syscon phandle, we have to put the mapping into the driver, which makes IMHO no sense, because you have to touch the driver, if there is another SoC with the DCAN core.

... which would be my preferred solution. I think new SoCs should have some kind of:

	compatible = "commodore,c64ultra", "bosch,d_can";

in the DT anyhow to allow for SoC specific quirks/adjustments. And custom raminit belongs to that IMO (see the ti routine getting more and more specific).

author
#27 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 7 lines · Wolfram Sang
Quoted 5 lines
Quoted 3 lines

Unfortunately it is 5 ;)
We have display IP related bit in between 3 and 5 :P

What on earth were the HW engineers thinking????????????

"Let's test my RNG on the bit-placement of this register" :)

:D

Quoted 4 lines
Quoted 4 lines

...if we just have the instance parameter in the syscon phandle, we have to put the mapping into the driver, which makes IMHO no sense, because you have to touch the driver, if there is another SoC with the DCAN core.

My guess is that TI won't come up with a 3rd variant so we won't have to touch the driver, but you never know for sure.

Quoted 10 lines

... which would be my preferred solution. I think new SoCs should have some kind of:

	compatible = "commodore,c64ultra", "bosch,d_can";

in the DT anyhow to allow for SoC specific quirks/adjustments. And custom raminit belongs to that IMO (see the ti routine getting more and more specific).

Right. For now we need 2 start/stop definations for the existing TI Socs.

but where to store the raminit start/stop bits? The driver_data currently seems to contain the CAN type C_CAN vs D_CAN without containing it in a platform_data structure.

Is it OK to create a new platform_data structure for CAN and put the type and raminit start/stop bits there?

cheers,
-roger

maintainer
#28 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 6 lines · Roger Quadros
Quoted 3 lines
Quoted 3 lines

...if we just have the instance parameter in the syscon phandle, we have to put the mapping into the driver, which makes IMHO no sense, because you have to touch the driver, if there is another SoC with the DCAN core.

My guess is that TI won't come up with a 3rd variant so we won't have to touch the driver, but you never know for sure.

When I comes to 99% compatible hardware.... I've seen some.

Quoted 10 lines
Quoted 9 lines

... which would be my preferred solution. I think new SoCs should have some kind of:

	compatible = "commodore,c64ultra", "bosch,d_can";

in the DT anyhow to allow for SoC specific quirks/adjustments. And custom raminit belongs to that IMO (see the ti routine getting more and more specific).

Quoted 7 lines

Right. For now we need 2 start/stop definations for the existing TI Socs.

but where to store the raminit start/stop bits? The driver_data currently seems to contain the CAN type C_CAN vs D_CAN without containing it in a platform_data structure.

Is it OK to create a new platform_data structure for CAN and put the type and raminit start/stop bits there?

Yes, have a look how it's handled in the flexcan driver.

regards,
Marc

Signature · 4 lines
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#29 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

In reply to Roger Quadros
Quoted 3 lines

Is it OK to create a new platform_data structure for CAN and put the type and raminit start/stop bits there?

I'd say yes, don't see a reason not to.

maintainer
#30 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

In reply to Wolfram Sang
Quoted 1 line · Wolfram Sang
	compatible = "commodore,c64ultra", "bosch,d_can";

\o/

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maintainer
#31 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

In reply to Wolfram Sang
Quoted 34 lines · Wolfram Sang
Quoted 23 lines · Roger Quadros

Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver.

To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register.

Signed-off-by Roger Quadros <[email protected]>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 109 +++++++++++++++------
 3 files changed, 95 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/net/can/c_can.txt +0 -0
index 8f1ae81..e12d1a1 100644

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 7 lines
Documentation/devicetree/bindings/net/can/c_can.txt +4 -0
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- ti,raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

Quoted 6 lines

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 21

Quoted 2 lines
Documentation/devicetree/bindings/net/can/c_can.txt +2 -0
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register

This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...

Is the register shared by more than one core? If so the information has to go somewhere. Using an alias in the DT is probably the wrong approach.

Marc

Signature · 4 lines
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |
author
#32 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 38 lines · Marc Kleine-Budde
Quoted 37 lines · Wolfram Sang
Quoted 23 lines · Roger Quadros

Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver.

To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register.

Signed-off-by Roger Quadros <[email protected]>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 109 +++++++++++++++------
 3 files changed, 95 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/net/can/c_can.txt +0 -0
index 8f1ae81..e12d1a1 100644

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 7 lines
Documentation/devicetree/bindings/net/can/c_can.txt +4 -0
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- ti,raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

Quoted 2 lines
Documentation/devicetree/bindings/net/can/c_can.txt +2 -0
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
Quoted 6 lines
Quoted 3 lines

This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...

Is the register shared by more than one core? If so the information has to go somewhere. Using an alias in the DT is probably the wrong approach.

In case of the DRA7xx Soc, this syscon register is shared by multiple cores. (CAN, Display, etc), sigh!! For AM335x and AM43xx SoCs, the register is used only for DCAN. but shared by 2 DCAN instances.

Shouldn't the information for the CAN specific bits lie in the CAN driver?

cheers,
-roger

maintainer
#33 lore raw

Re: [PATCH v2 2/3] net: can: c_can: Add syscon/regmap RAMINIT mechanism

Quoted 43 lines · Roger Quadros
Quoted 42 lines · Marc Kleine-Budde
Quoted 40 lines · Wolfram Sang
Quoted 23 lines · Roger Quadros

Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver.

To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register.

Signed-off-by Roger Quadros <[email protected]>
---
 .../devicetree/bindings/net/can/c_can.txt          |   7 ++
 drivers/net/can/c_can/c_can.h                      |  11 ++-
 drivers/net/can/c_can/c_can_platform.c             | 109 +++++++++++++++------
 3 files changed, 95 insertions(+), 32 deletions(-)
Documentation/devicetree/bindings/net/can/c_can.txt +0 -0
index 8f1ae81..e12d1a1 100644

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 19

Quoted 7 lines
Documentation/devicetree/bindings/net/can/c_can.txt +4 -0
@@ -13,6 +13,13 @@ Optional properties:
 - ti,hwmods		: Must be "d_can<n>" or "c_can<n>", n being the
 			  instance number
 
+- ti,raminit-syscon	: Handle to system control region that contains the
+			  RAMINIT register. If specified, the second memory resource
+			  in the reg property must index into the RAMINIT
+			  register within the syscon region

There seems to be a simple "syscon" property these days.

Documentation/devicetree/bindings/net/can/c_can.txt Optional properties: · line 21

Quoted 2 lines
Documentation/devicetree/bindings/net/can/c_can.txt +2 -0
+- ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
+- ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register

This should not be encoded in DT! This is not describing hardware setup. The driver should know where the bits are for the syscon phandle, depending on which SoC it runs...

Quoted 7 lines
Quoted 2 lines

Is the register shared by more than one core? If so the information has to go somewhere. Using an alias in the DT is probably the wrong approach.

In case of the DRA7xx Soc, this syscon register is shared by multiple cores. (CAN, Display, etc), sigh!! For AM335x and AM43xx SoCs, the register is used only for DCAN. but shared by 2 DCAN instances.

Shouldn't the information for the CAN specific bits lie in the CAN driver?

As there are more than one DCAN instance on the same SOC the information which DCAN instance uses which bits in the register has to go somewhere. We might add these bits as the 3rd and 4th parameter to the syscon phandle.

Marc

Signature · 4 lines
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |
author
#34 lore raw

PATCH v2 3/3 net: can: c_can: Add support for START pulse in RAMINIT sequence

In reply to Roger Quadros

Some SoCs e.g. (TI DRA7xx) need a START pulse to start the RAMINIT sequence i.e. START bit must be set and cleared before checking for the DONE bit status. Add a new DT property "raminit-pulse" to specify if this mechanism must be used for RAMINIT.

Signed-off-by Roger Quadros <[email protected]>
---
 Documentation/devicetree/bindings/net/can/c_can.txt | 3 +++
 drivers/net/can/c_can/c_can.h                       | 1 +
 drivers/net/can/c_can/c_can_platform.c              | 8 ++++++++
 3 files changed, 12 insertions(+)
Documentation/devicetree/bindings/net/can/c_can.txt +3 -0
index e12d1a1..705411f 100644
@@ -19,6 +19,9 @@ Optional properties:
 			  register within the syscon region
 - ti,raminit-start-bit	: Bit posistion of START bit in the RAMINIT register
 - ti,raminit-done-bit	: Bit position of DONE bit in the RAMINIT register
+- ti,raminit-pulse	: Property must exist if START pulse is needed for RAMINIT
+			  sequence i.e. START bit will be set and cleared before
+			  checking for DONE bit.
 
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
drivers/net/can/c_can/c_can.h +1 -0
index bf68822..85b5ad0 100644
@@ -175,6 +175,7 @@ struct c_can_raminit {
 	unsigned int reg;	/* register index within syscon */
 	u8 start_bit;	/* START bit position in raminit reg. */
 	u8 done_bit;	/* DONE bit position in raminit reg. */
+	bool needs_pulse;	/* If set, sets and clears START bit (pulse) */
 };
 
 /* c_can private data structure */
drivers/net/can/c_can/c_can_platform.c +8 -0
index fb0c35b..5ae9eb3 100644
@@ -120,6 +120,12 @@ static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
 		ctrl |= 1 << raminit->start_bit;
 		regmap_write(raminit->syscon, raminit->reg, ctrl);
 
+		/* clear START bit if start pulse is needed */
+		if (raminit->needs_pulse) {
+			ctrl &= ~(1 << raminit->start_bit);
+			regmap_write(raminit->syscon, raminit->reg, ctrl);
+		}
+
 		ctrl |= 1 << raminit->done_bit;
 		c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
 	}

@@ -340,6 +346,8 @@ static int c_can_plat_probe(struct platform_device *pdev)
 		}
 
 		priv->raminit_sys.done_bit = val;
+		priv->raminit_sys.needs_pulse = of_property_read_bool(np,
+								      "ti,raminit-pulse");
 		priv->raminit = c_can_hw_raminit_syscon;
 		break;
 	default:
Signature · 1 line
1.8.3.2