Skip to contentSkip to conversation

ARM: dts: imx53: Improve SSI clocks description

PATCH New Fabio Estevam 4 participants 6 messages Sep 18, 2014 – Oct 25, 2014

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape
lore
Share & tools
lore

Fabio Estevam

author reviewer
#0 lore raw

PATCH 1/2 ARM: dts: imx53: Improve SSI clocks description

From: Fabio Estevam <[email protected]>

SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode.

Add the extra 'baud' clock so that we can have SSI functional in master mode.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx53.dtsi | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)
arch/arm/boot/dts/imx53.dtsi +9 -3
index 6b198c6d..5040dae 100644
@@ -227,7 +227,9 @@
 							"fsl,imx21-ssi";
 					reg = <0x50014000 0x4000>;
 					interrupts = <30>;
-					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+						 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+					clock-names = "ipg", "baud";
 					dmas = <&sdma 24 1 0>,
 					       <&sdma 25 1 0>;
 					dma-names = "rx", "tx";

@@ -667,7 +669,9 @@
 						"fsl,imx21-ssi";
 				reg = <0x63fcc000 0x4000>;
 				interrupts = <29>;
-				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+					 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+				clock-names = "ipg", "baud";
 				dmas = <&sdma 28 0 0>,
 				       <&sdma 29 0 0>;
 				dma-names = "rx", "tx";

@@ -695,7 +699,9 @@
 						"fsl,imx21-ssi";
 				reg = <0x63fe8000 0x4000>;
 				interrupts = <96>;
-				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
+				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+					 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+				clock-names = "ipg", "baud";
 				dmas = <&sdma 46 0 0>,
 				       <&sdma 47 0 0>;
 				dma-names = "rx", "tx";
Signature · 1 line
1.9.1
author reviewer
#1 lore raw

PATCH 2/2 ARM: dts: imx51: Improve SSI clocks description

From: Fabio Estevam <[email protected]>

SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode.

Add the extra 'baud' clock so that we can have SSI functional in master mode.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx51.dtsi | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)
arch/arm/boot/dts/imx51.dtsi +9 -3
index 92660e1..c0116cf 100644
@@ -214,7 +214,9 @@
 					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 					reg = <0x70014000 0x4000>;
 					interrupts = <30>;
-					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
+					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+						 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+					clock-names = "ipg", "baud";
 					dmas = <&sdma 24 1 0>,
 					       <&sdma 25 1 0>;
 					dma-names = "rx", "tx";

@@ -504,7 +506,9 @@
 				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 				reg = <0x83fcc000 0x4000>;
 				interrupts = <29>;
-				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
+				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+					 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+				clock-names = "ipg", "baud";
 				dmas = <&sdma 28 0 0>,
 				       <&sdma 29 0 0>;
 				dma-names = "rx", "tx";

@@ -560,7 +564,9 @@
 				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 				reg = <0x83fe8000 0x4000>;
 				interrupts = <96>;
-				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
+				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+					 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+				clock-names = "ipg", "baud";
 				dmas = <&sdma 46 0 0>,
 				       <&sdma 47 0 0>;
 				dma-names = "rx", "tx";
Signature · 1 line
1.9.1
Applied
#2 lore raw

PATCH 1/2 ARM: dts: imx53: Improve SSI clocks description

In reply to Fabio Estevam
Quoted 8 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode.

Add the extra 'baud' clock so that we can have SSI functional in master mode.

Signed-off-by Fabio Estevam <[email protected]>

Applied both, thanks.

author reviewer
#3 lore raw

PATCH 1/2 ARM: dts: imx53: Improve SSI clocks description

Shawn,

Quoted 11 lines · Shawn Guo
Quoted 8 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode.

Add the extra 'baud' clock so that we can have SSI functional in master mode.

Signed-off-by Fabio Estevam <[email protected]>

Applied both, thanks.

I am not able to see these patches in linux-next yet.

#4 lore raw

PATCH 1/2 ARM: dts: imx53: Improve SSI clocks description

Quoted 9 lines · Fabio Estevam

Shawn,

Quoted 6 lines · Shawn Guo
Quoted 5 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode.

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines

Add the extra 'baud' clock so that we can have SSI functional in master mode.

Signed-off-by Fabio Estevam <[email protected]>

Applied both, thanks.

I am not able to see these patches in linux-next yet.

Yes, I haven't updated my for-next branch. Will do soon.

Shawn

#5 lore raw

PATCH 1/2 ARM: dts: imx53: Improve SSI clocks description

Quoted 5 lines · Shawn Guo
Quoted 3 lines
Quoted 1 line

Applied both, thanks.

I am not able to see these patches in linux-next yet.

Yes, I haven't updated my for-next branch. Will do soon.

I'll also have some dts and defconfig patches, looking forward to it :)