arm: socfpga: Add Cadence QSPI support

PATCH Superseded Stefan Roese 4 participants 11 messages Sep 23, 2014 – Sep 25, 2014 SPI

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Stefan Roese

author

2014-09-23 14:08 UTC #0 lore raw

v2 cover arm: socfpga: Add Cadence QSPI support

Hi SoCFPGA-developers!

So this is my 2nd posting regarding the Candence SPI driver on SoCFPGA. I got it working now. But only with one quick-hack, as you can see in patch 4/4. Which disabled the dcache. Or more precise, doesn't enable it. Thanks to Michael who pointed this out.

Since I really can't spend more time on this in this week, and Chin Liang mentioned that he might be able to help out (thanks again for this), I'm posting this version now for all others as a reference. Hopefully Chin Liang (or some other volunteer) can fix this cache issue in a generic way.

Thanks,
Stefan

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Michael Trimarchi <[email protected]>

Stefan Roese

author

2014-09-23 14:08 UTC #1 lore raw

PATCH v2 1/4 spi: Add Cadence QSPI driver used by SoCFPGA

This driver is copied directly from the Altera Rockerboard.org U-Boot repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With minimal changes to enable compilation in mainline U-Boot.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Michael Trimarchi <[email protected]>

---
 drivers/spi/Makefile           |   1 +
 drivers/spi/cadence_qspi.c     | 355 ++++++++++++++++
 drivers/spi/cadence_qspi.h     |  73 ++++
 drivers/spi/cadence_qspi_apb.c | 900 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 1329 insertions(+)
 create mode 100644 drivers/spi/cadence_qspi.c
 create mode 100644 drivers/spi/cadence_qspi.h
 create mode 100644 drivers/spi/cadence_qspi_apb.c

drivers/spi/Makefile +1 -0

index f02c35a..4b7b566 100644
@@ -16,6 +16,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
 obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o
 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o

drivers/spi/cadence_qspi.c new file +355 -0

355 lines not on this page · raw message

drivers/spi/cadence_qspi.h new file +73 -0

73 lines not on this page · raw message

drivers/spi/cadence_qspi_apb.c new file +900 -0

900 lines not on this page · raw message

Signature · 1 line

2.1.0

Pavel Machek

2014-09-23 20:05 UTC #2 lore raw

PATCH v2 1/4 spi: Add Cadence QSPI driver used by SoCFPGA

Hi!

Quoted 14 lines

+++ b/drivers/spi/cadence_qspi.c

drivers/spi/cadence_qspi.c new file +12 -0

@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *

drivers/spi/cadence_qspi.c line 22

Quoted 10 lines

drivers/spi/cadence_qspi.c new file +10 -0

+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA  02111-1307  USA
+ */

SPDX headers?

drivers/spi/cadence_qspi.h line 28

Quoted 2 lines

drivers/spi/cadence_qspi.h new file +2 -0
+#define CQSPI_WRITEL		writel
+#define CQSPI_READL		readl

It would be nice to get rid of these.

drivers/spi/cadence_qspi_apb.c line 293

Quoted 8 lines

drivers/spi/cadence_qspi_apb.c new file +8 -0

+/* Write to SRAM FIFO with polling SRAM fill level. */
+static int qpsi_write_sram_fifo_push(const void *reg_base, void *dest_addr,
+				const void *src_addr, unsigned int num_bytes)
+{
+	unsigned int retry = CQSPI_REG_RETRY;
+	unsigned int sram_level;
+	unsigned int wr_bytes;
+	unsigned char* src = (unsigned char *)src_addr;

"char *src", afaict.

Best regards,
Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Marek Vasut

2014-09-23 20:08 UTC #3 lore raw

PATCH v2 1/4 spi: Add Cadence QSPI driver used by SoCFPGA

Quoted 29 lines · Pavel Machek

Hi!

Quoted 14 lines

+++ b/drivers/spi/cadence_qspi.c

drivers/spi/cadence_qspi.c new file +12 -0

@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2012
+ * Altera Corporation <www.altera.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *

drivers/spi/cadence_qspi.c line 22

Quoted 10 lines

drivers/spi/cadence_qspi.c new file +10 -0

+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA  02111-1307  USA
+ */

SPDX headers?

Quoted 8 lines

drivers/spi/cadence_qspi.h line 28
Quoted 2 lines
drivers/spi/cadence_qspi.h new file +2 -0
+#define CQSPI_WRITEL		writel
+#define CQSPI_READL		readl
It would be nice to get rid of these.
Quoted 3 lines
(quoted diff) +2 -0
+/* Write to SRAM FIFO with polling SRAM fill level. */
+static int qpsi_write_sram_fifo_push(const void *reg_base, void
*dest_addr, + const void *src_addr, unsigned

int num_bytes)

Quoted 7 lines

drivers/spi/cadence_qspi_apb.c line 293
Quoted 5 lines
drivers/spi/cadence_qspi_apb.c new file +5 -0
+{
+	unsigned int retry = CQSPI_REG_RETRY;
+	unsigned int sram_level;
+	unsigned int wr_bytes;
+	unsigned char* src = (unsigned char *)src_addr;
"char *src", afaict.

uint8_t ...

Best regards,
Marek Vasut

Stefan Roese

author

2014-09-23 14:08 UTC #4 lore raw

PATCH v2 2/4 arm: socfpga: Add Cadence QSPI support to config header

In reply to Stefan Roese

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Michael Trimarchi <[email protected]>

---
 include/configs/socfpga_cyclone5_common.h | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

include/configs/socfpga_cyclone5_common.h +31 -0

index 3f8f91f..d183510 100644
@@ -142,6 +142,37 @@
 #endif
 
 /*
+ * QSPI support
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_CADENCE_QSPI
+#define CONFIG_CQSPI_BASE		(SOCFPGA_QSPI_ADDRESS)
+#define CONFIG_CQSPI_AHB_BASE		(SOCFPGA_QSPIDATA_ADDRESS)
+#define CONFIG_SPI_FLASH		/* SPI flash subsystem */
+#define CONFIG_SPI_FLASH_STMICRO	/* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION	/* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* Flash device info */
+#define CONFIG_SF_DEFAULT_SPEED		(50000000)
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#define CONFIG_SPI_FLASH_QUAD		(1)
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+/* QSPI page size and block size */
+#define CONFIG_CQSPI_PAGE_SIZE		(256)
+#define CONFIG_CQSPI_BLOCK_SIZE		(16)
+/* QSPI Delay timing */
+#define CONFIG_CQSPI_TSHSL_NS		(200)
+#define CONFIG_CQSPI_TSD2D_NS		(255)
+#define CONFIG_CQSPI_TCHSH_NS		(20)
+#define CONFIG_CQSPI_TSLCH_NS		(20)
+#define CONFIG_CQSPI_DECODER		(0)
+#endif	/* CONFIG_CMD_SF */
+
+/*
  * Serial Driver
  */
 #define CONFIG_SYS_NS16550

Signature · 1 line

2.1.0

Stefan Roese

author

2014-09-23 14:08 UTC #5 lore raw

PATCH v2 3/4 arm: socfpga: Don't define CONFIG_SPI_FLASH_QUAD

In reply to Stefan Roese

This define is currently not supported in mainline U-Boot. So don't define it. Otherwise the drivers doesn't work correctly.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Michael Trimarchi <[email protected]>

---
 include/configs/socfpga_cyclone5_common.h | 2 ++
 1 file changed, 2 insertions(+)

include/configs/socfpga_cyclone5_common.h +2 -0

index d183510..5ef6936 100644
@@ -155,7 +155,9 @@
 /* Flash device info */
 #define CONFIG_SF_DEFAULT_SPEED		(50000000)
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#if 0 /* not supported in mainline right now */
 #define CONFIG_SPI_FLASH_QUAD		(1)
+#endif
 /* QSPI reference clock */
 #ifndef __ASSEMBLY__
 unsigned int cm_get_qspi_controller_clk_hz(void);

Signature · 1 line

2.1.0

Stefan Roese

author

2014-09-23 14:08 UTC #6 lore raw

PATCH v2 4/4 arm: socfpga: Don't enable dcache (because of cadence SPI driver problem)

In reply to Stefan Roese

The Cadence SPI driver currently has some problems when the dcache is enabled. As a work-around until this problem is fixed in the SPI driver, lets not enable the dcache on the socfpga platforms. As its also done in the rocketboards version.

Signed-off-by Stefan Roese <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Vince Bridgers <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Pavel Machek <[email protected]>

Cc Michael Trimarchi <[email protected]>

---
 board/altera/socfpga/socfpga_cyclone5.c | 2 ++
 1 file changed, 2 insertions(+)

board/altera/socfpga/socfpga_cyclone5.c +2 -0

index 10f15e0..3f19d89 100644
@@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
 int board_init(void)
 {
 	icache_enable();
+#if 0 // test-only: disable dcache for now as it causes problems with the SPI driver
 	dcache_enable();
+#endif
 
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

Signature · 1 line

2.1.0

Marek Vasut

2014-09-23 14:32 UTC #7 lore raw

PATCH v2 4/4 arm: socfpga: Don't enable dcache (because of cadence SPI driver problem)

Quoted 21 lines · Stefan Roese

The Cadence SPI driver currently has some problems when the dcache is enabled. As a work-around until this problem is fixed in the SPI driver, lets not enable the dcache on the socfpga platforms. As its also done in the rocketboards version.
Signed-off-by Stefan Roese <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Vince Bridgers <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Pavel Machek <[email protected]>
Cc Michael Trimarchi <[email protected]>
---
 board/altera/socfpga/socfpga_cyclone5.c | 2 ++
 1 file changed, 2 insertions(+)
(quoted diff) +0 -0
b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644

board/altera/socfpga/socfpga_cyclone5.c int board_phy_config(struct phy_device *phydev) · line 81

Quoted 6 lines

board/altera/socfpga/socfpga_cyclone5.c +2 -0

@@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
 int board_init(void)
 {
 	icache_enable();
+#if 0 // test-only: disable dcache for now as it causes problems with the
 SPI driver dcache_enable();
+#endif

This means the DMA code in cadence driver is not flushing/invalidating cache as it should. Are you planning to fix it proper eventually?

But this is really a good thing that you found this out! That's an important information, thanks!

Best regards,
Marek Vasut

Stefan Roese

author

2014-09-23 15:20 UTC #8 lore raw

PATCH v2 4/4 arm: socfpga: Don't enable dcache (because of cadence SPI driver problem)

Quoted 6 lines · Marek Vasut

Quoted 6 lines
(quoted diff) +0 -0
b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644
board/altera/socfpga/socfpga_cyclone5.c +0 -0
@@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
  int board_init(void)

Quoted 8 lines

board/altera/socfpga/socfpga_cyclone5.c int board_phy_config(struct phy_device *phydev) · line 81
Quoted 5 lines
board/altera/socfpga/socfpga_cyclone5.c +2 -0
  {
  	icache_enable();
+#if 0 // test-only: disable dcache for now as it causes problems with the
 SPI driver dcache_enable();
+#endif
This means the DMA code in cadence driver is not flushing/invalidating cache as it should.

I am aware of this. Caching related issues are definitely not new to me. ;)

I didn't spot any DMA controller related code in the driver. Only some FIFO stuff which is most likely the problematic code part. But since I've no deeper insight in this IP core right now, I just wanted to offer this info to others for now.

Quoted 1 line

Are you planning to fix it proper eventually?

Not right now, sorry. As I explained in my cover letter, I have to move to other projects. At least for a few days.

Quoted 2 lines

But this is really a good thing that you found this out! That's an important information, thanks!

Yes, thats exactly why I posted it in this stage.

Thanks,
Stefan

Michael Trimarchi

2014-09-23 15:41 UTC #9 lore raw

PATCH v2 4/4 arm: socfpga: Don't enable dcache (because of cadence SPI driver problem)

Quoted 28 lines · Stefan Roese

Quoted 10 lines · Marek Vasut
Quoted 10 lines
(quoted diff) +0 -0
b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644
board/altera/socfpga/socfpga_cyclone5.c +1 -0
@@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
  int board_init(void)
  {
        icache_enable();
+#if 0 // test-only: disable dcache for now as it causes problems with
Quoted 8 lines
Quoted 3 lines
the
SPI driver dcache_enable();
+#endif
This means the DMA code in cadence driver is not flushing/invalidating cache
as it should.
I am aware of this. Caching related issues are definitely not new to me. ;)
I didn't spot any DMA controller related code in the driver. Only some FIFO stuff which is most likely the problematic code part. But since I've no deeper insight in this IP core right now, I just wanted to offer this info to others for now.

Quoted 6 lines

Quoted 1 line
Are you planning to fix it proper eventually?
Not right now, sorry. As I explained in my cover letter, I have to move to other projects. At least for a few days.

me too ;). I don't have any fpga on my desk right now (maybe in 3 weeks)

Quoted 7 lines

Quoted 3 lines
But this is really a good thing that you found this out! That's an important
information, thanks!
Yes, thats exactly why I posted it in this stage.

I'm really happy that start to work ;)

Michael

Quoted 3 lines

Thanks,
Stefan

Signature · 4 lines

| Michael Nazzareno Trimarchi                     Amarula Solutions BV |
| COO  -  Founder                                      Cruquiuskade 47 |
| +31(0)851119172                                 Amsterdam 1018 AM NL |
|                  [`as] http://www.amarulasolutions.com               |

Marek Vasut

2014-09-25 15:25 UTC #10 lore raw

v2 cover arm: socfpga: Add Cadence QSPI support

In reply to Stefan Roese

Quoted 7 lines · Stefan Roese

Hi SoCFPGA-developers!
So this is my 2nd posting regarding the Candence SPI driver on SoCFPGA. I got it working now. But only with one quick-hack, as you can see in patch 4/4. Which disabled the dcache. Or more precise, doesn't enable it. Thanks to Michael who pointed this out.

Quoted 5 lines

Since I really can't spend more time on this in this week, and Chin Liang mentioned that he might be able to help out (thanks again for this), I'm posting this version now for all others as a reference. Hopefully Chin Liang (or some other volunteer) can fix this cache issue in a generic way.

I will keep tracking this in my repository so it doesn't get lost. I am not sure I will get to fixing it though.

Best regards,
Marek Vasut