arm, at91, spl: add spl support for the taurus and corvus boards

index 8136396..76668d2 100644
@@ -26,7 +26,8 @@ int ddr2_init(const unsigned int ram_address,
 	/* Compute bank offset according to NC in configuration register */
 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
 	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
-		ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2)
+			   + 11;
 
 	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
 

index 76668d2..602e71e 100644
@@ -17,6 +17,15 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 	writel(0, ram_address);
 }
 
+static int ddr2_decodtype_is_seq(u32 cr)
+{
+#if defined(CONFIG_SAMA5D3)
+	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
+		return 0;
+#endif
+	return 1;
+}
+
 int ddr2_init(const unsigned int ram_address,
 	      const struct atmel_mpddr *mpddr_value)
 {

@@ -25,7 +34,7 @@ int ddr2_init(const unsigned int ram_address,
 
 	/* Compute bank offset according to NC in configuration register */
 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
-	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+	if (ddr2_decodtype_is_seq(mpddr_value->cr))
 		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2)
 			   + 11;
 

index 5741f6e..bd403d2 100644
@@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address,
 #define ATMEL_MPDDRC_CR_DIC_DS			(0x1 << 8)
 #define ATMEL_MPDDRC_CR_DIS_DLL			(0x1 << 9)
 #define ATMEL_MPDDRC_CR_OCD_DEFAULT		(0x7 << 12)
+#define ATMEL_MPDDRC_CR_EBISHARE		(0x1 << 16)
 #define ATMEL_MPDDRC_CR_ENRDM_ON		(0x1 << 17)
 #define ATMEL_MPDDRC_CR_NB_8BANKS		(0x1 << 20)
 #define ATMEL_MPDDRC_CR_NDQS_DISABLED		(0x1 << 21)

index b16664f..97dc0f0 100644
@@ -61,6 +61,15 @@ __weak void spl_board_prepare_for_linux(void)
 	/* Nothing to do! */
 }
 
+void spl_set_header_raw_uboot(void)
+{
+	spl_image.size = CONFIG_SYS_MONITOR_LEN;
+	spl_image.entry_point = CONFIG_SYS_UBOOT_START;
+	spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
+	spl_image.os = IH_OS_U_BOOT;
+	spl_image.name = "U-Boot";
+}
+
 void spl_parse_image_header(const struct image_header *header)
 {
 	u32 header_size = sizeof(struct image_header);

@@ -93,11 +102,7 @@ void spl_parse_image_header(const struct image_header *header)
 		debug("mkimage signature not found - ih_magic = %x\n",
 			header->ih_magic);
 		/* Let's assume U-Boot will not be more than 200 KB */
-		spl_image.size = CONFIG_SYS_MONITOR_LEN;
-		spl_image.entry_point = CONFIG_SYS_UBOOT_START;
-		spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
-		spl_image.os = IH_OS_U_BOOT;
-		spl_image.name = "U-Boot";
+		spl_set_header_raw_uboot();
 	}
 }
 

index 9b200bc..b7801cb 100644
@@ -10,6 +10,18 @@
 #include <asm/io.h>
 #include <nand.h>
 
+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
+void spl_nand_load_image(void)
+{
+	nand_init();
+
+	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			    CONFIG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+	spl_set_header_raw_uboot();
+	nand_deselect();
+}
+#else
 void spl_nand_load_image(void)
 {
 	struct image_header *header;

@@ -82,3 +94,4 @@ void spl_nand_load_image(void)
 		spl_image.size, (void *)spl_image.load_addr);
 	nand_deselect();
 }
+#endif

index a7e41da..6d2040d 100644
@@ -35,6 +35,7 @@ extern struct spl_image_info spl_image;
 void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(void);
+void spl_set_header_raw_uboot(void);
 void spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
 void __noreturn jump_to_image_linux(void *arg);

index 9114a86..d506e42 100644
@@ -18,6 +18,7 @@
 #include <malloc.h>
 #include <nand.h>
 #include <watchdog.h>
+#include <linux/mtd/nand_ecc.h>
 
 #ifdef CONFIG_ATMEL_NAND_HWECC
 

index d506e42..276d820 100644
@@ -1274,6 +1274,39 @@ static int nand_read_page(int block, int page, void *dst)
 
 	return 0;
 }
+
+int nand_erase_one(int block, int page)
+{
+	struct nand_chip *this = mtd.priv;
+	void (*hwctrl)(struct mtd_info *mtd, int cmd,
+			unsigned int ctrl) = this->cmd_ctrl;
+	int page_addr;
+
+	if (nand_chip.select_chip)
+		nand_chip.select_chip(&mtd, 0);
+
+	page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+	hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	/* Row address */
+	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+	/* One more address cycle for devices > 128MiB */
+	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+#endif
+
+	hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	udelay(2000);
+
+	while (!this->dev_ready(&mtd))
+		;
+
+	nand_deselect();
+
+	return 0;
+}
 #else
 static int nand_read_page(int block, int page, void *dst)
 {

index 8438490..ee2c3fe 100644
@@ -1020,5 +1020,6 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
 uint8_t nand_read_byte(struct mtd_info *mtd);
+int nand_erase_one(int block, int page);
 #endif
 #endif /* __LINUX_MTD_NAND_H */

index 276d820..4f04ed8 100644
@@ -1188,7 +1188,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (this->dev_ready(&mtd))
+	while (!this->dev_ready(&mtd))
 		;
 
 	if (cmd == NAND_CMD_READOOB) {

@@ -1213,7 +1213,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 	hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	while (this->dev_ready(&mtd))
+	while (!this->dev_ready(&mtd))
 		;
 
 	return 0;

@@ -1353,7 +1353,7 @@ int at91_nand_wait_ready(struct mtd_info *mtd)
 
 	udelay(this->chip_delay);
 
-	return 0;
+	return 1;
 }
 
 int board_nand_init(struct nand_chip *nand)

index cae4abc..7a7fd7d 100644
@@ -8,8 +8,10 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/gpio.h>
 
 /*

@@ -207,3 +209,23 @@ void at91_mci_hw_init(void)
 #endif
 }
 #endif
+
+void at91_sdram_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
+}

63 lines not on this page · raw message

index 36ed4a6..363081a 100644
@@ -111,6 +111,33 @@ int at91_clock_init(unsigned long main_clock)
 	return 0;
 }
 
+void at91_plla_init(u32 pllar)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(pllar, &pmc->pllar);
+	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
+		;
+}
+
+void at91_mck_init(u32 mckr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
+		 AT91_PMC_MCKR_MDIV_MASK |
+		 AT91_PMC_MCKR_PLLADIV_2);
+	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
+		       AT91_PMC_MCKR_MDIV_MASK |
+		       AT91_PMC_MCKR_PLLADIV_2);
+	writel(tmp, &pmc->mckr);
+
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+}
+
 void at91_periph_clk_enable(int id)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

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index 59e2f43..2d94090 100644
@@ -23,9 +23,13 @@ void at91_udp_hw_init(void);
 void at91_uhp_hw_init(void);
 void at91_lcd_hw_init(void);
 void at91_plla_init(u32 pllar);
+void at91_pllb_init(u32 pllar);
 void at91_mck_init(u32 mckr);
 void at91_pmc_init(void);
 void mem_init(void);
 void at91_phy_reset(void);
+void at91_sdram_hw_init(void);
+void at91_mck_init(u32 mckr);
+void at91_spl_board_init(void);
 
 #endif /* AT91_COMMON_H */

index 27331ff..5f64583 100644
@@ -95,7 +95,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_MAIN		0x00000001
 #define AT91_PMC_MCKR_CSS_PLLA		0x00000002
 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
-#define AT91_PMC_MCKR_CSS_MASK		0x00000003
+#define AT91_PMC_MCKR_CSS_MASK		0x00000007
 
 #ifdef CONFIG_SAMA5D3
 #define AT91_PMC_MCKR_PRES_1		0x00000000

@@ -114,7 +114,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PRES_16		0x00000010
 #define AT91_PMC_MCKR_PRES_32		0x00000014
 #define AT91_PMC_MCKR_PRES_64		0x00000018
-#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+#define AT91_PMC_MCKR_PRES_MASK		0x0000003C
 #endif
 
 #ifdef CONFIG_AT91RM9200

@@ -133,6 +133,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
 #endif
 
+#define AT91_PMC_MCKR_PLLADIV_MASK	0x00003000
 #define AT91_PMC_MCKR_PLLADIV_1		0x00000000
 #define AT91_PMC_MCKR_PLLADIV_2		0x00001000
 

index 2e902ee..1e613fa 100644
@@ -95,6 +95,7 @@
 #define ATMEL_BASE_SDRAMC	0xffffea00
 #define ATMEL_BASE_SMC		0xffffec00
 #define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_CCFG         0xffffef14
 #define ATMEL_BASE_AIC		0xfffff000
 #define ATMEL_BASE_DBGU		0xfffff200
 #define ATMEL_BASE_PIOA		0xfffff400

index 4755fa1..dc61f48 100644
@@ -61,5 +61,10 @@ struct at91_matrix {
 #define AT91_MATRIX_DBPUC		(1 << 8)
 #define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
 #define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+#define AT91_MATRIX_EBI_IOSR_SEL	(1 << 17)
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_SLOT_CYCLE		(0xff << 0)
+#define AT91_MATRIX_SLOT_CYCLE_(x)	(x << 0)
 
 #endif

index 5c98cc7..3a076c6 100644
@@ -25,6 +25,21 @@
 #define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
 #define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
 
+#else
+struct sdramc_reg {
+	u32	mr;
+	u32	tr;
+	u32	cr;
+	u32	lpr;
+	u32	ier;
+	u32	idr;
+	u32	imr;
+	u32	isr;
+	u32	mdr;
+};
+
+int sdramc_initialize(unsigned int sdram_address,
+		      const struct sdramc_reg *p);
 #endif
 
 /* SDRAM Controller (SDRAMC) registers */

@@ -62,11 +77,17 @@
 #define			AT91_SDRAMC_DBW_32	(0 << 7)
 #define			AT91_SDRAMC_DBW_16	(1 << 7)
 #define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
+#define		AT91_SDRAMC_TWR_VAL(x)	(x << 8)
 #define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
+#define			AT91_SDRAMC_TRC_VAL(x)	(x << 12)
 #define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
+#define		AT91_SDRAMC_TRP_VAL(x)	(x << 16)
 #define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
+#define			AT91_SDRAMC_TRCD_VAL(x)	(x << 20)
 #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
+#define		AT91_SDRAMC_TRAS_VAL(x)	(x << 24)
 #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
+#define		AT91_SDRAMC_TXSR_VAL(x)	(x << 28)
 
 #define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */

@@ -93,5 +114,4 @@
 #define			AT91_SDRAMC_MD_SDRAM		0
 #define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
 
-
 #endif

index 98ce441..abf4e7f 100644
@@ -21,6 +21,8 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/clk.h>
+#include <linux/mtd/nand.h>
 #include <atmel_mci.h>
 #include <asm/arch/at91_spi.h>
 #include <spi.h>

@@ -30,7 +32,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_CMD_NAND
 static void taurus_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

@@ -63,15 +64,68 @@ static void taurus_nand_hw_init(void)
 	/* Enable NandFlash */
 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	taurus_nand_hw_init();
+
+	/* Configure recovery button PINs */
+	at91_set_gpio_input(AT91_PIN_PA31, 1);
+
+	/* check if button is pressed */
+	if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
+		u32 boot_device;
+
+		debug("Recovery button pressed\n");
+		boot_device = spl_boot_device();
+		switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+		case BOOT_DEVICE_NAND:
+			nand_init();
+			nand_erase_one(0, 0);
+			break;
+#endif
+		}
+	}
+}
+
+void mem_init(void)
+{
+	struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct sdramc_reg setting;
+
+	at91_sdram_hw_init();
+	setting.cr = (AT91_SDRAMC_NC_9 |
+		      AT91_SDRAMC_NR_13 |
+		      AT91_SDRAMC_CAS_3 |
+		      AT91_SDRAMC_NB_4 |
+		      AT91_SDRAMC_DBW_32 |
+		      AT91_SDRAMC_TWR_VAL(3) |
+		      AT91_SDRAMC_TRC_VAL(9) |
+		      AT91_SDRAMC_TRP_VAL(3) |
+		      AT91_SDRAMC_TRCD_VAL(3) |
+		      AT91_SDRAMC_TRAS_VAL(6) |
+		      AT91_SDRAMC_TXSR_VAL(10));
+	setting.mdr = AT91_SDRAMC_MD_SDRAM;
+	setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+
+
+	writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
+		AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
+		&ma->ebicsa);
+	sdramc_initialize(ATMEL_BASE_CS1, &setting);
+}
 #endif
 
 #ifdef CONFIG_MACB
 static void taurus_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable EMAC clock */
-	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_EMAC0);
 
 	/*
 	 * Disable pull-up on:

@@ -119,12 +173,12 @@ int board_mmc_init(bd_t *bd)
 
 int board_early_init_f(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable clocks for all PIOs */
-	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
-		(1 << ATMEL_ID_PIOC),
-		&pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+	at91_seriald_hw_init();
 
 	return 0;
 }

@@ -153,7 +207,6 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	taurus_nand_hw_init();
 #endif

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index f1e93ef..b78e795 100644
@@ -31,12 +31,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_CMD_NAND
 static void corvus_nand_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	unsigned long csa;
 
 	/* Enable CS3 */

@@ -63,22 +61,111 @@ static void corvus_nand_hw_init(void)
 	       AT91_SMC_MODE_TDF_CYCLE(3),
 	       &smc->cs[3].mode);
 
-	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
-
-	/* Configure RDY/BSY */
-	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
 
 	/* Enable NandFlash */
 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	/*
+	 * For on the sam9m10g45ek board, the chip wm9711 stay in the test
+	 * mode, so it need do some action to exit mode.
+	 */
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+
+	corvus_nand_hw_init();
+
+	/* Configure recovery button PINs */
+	at91_set_gpio_input(AT91_PIN_PB7, 1);
+
+	/* check if button is pressed */
+	if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
+		u32 boot_device;
+
+		debug("Recovery button pressed\n");
+		boot_device = spl_boot_device();
+		switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+		case BOOT_DEVICE_NAND:
+			nand_init();
+			nand_erase_one(0, 0);
+			break;
 #endif
+		}
+	}
+}
 
-#ifdef CONFIG_CMD_USB
-static void taurus_usb_hw_init(void)
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_EBISHARE |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
 
-	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+	/* enable DDR2 clock */
+	writel(0x4, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void taurus_usb_hw_init(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
 
 	at91_set_gpio_output(AT91_PIN_PD1, 0);
 	at91_set_gpio_output(AT91_PIN_PD3, 0);

@@ -88,10 +175,8 @@ static void taurus_usb_hw_init(void)
 #ifdef CONFIG_MACB
 static void corvus_macb_hw_init(void)
 {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
 	/* Enable clock */
-	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+	at91_periph_clk_enable(ATMEL_ID_EMAC);
 
 	/*
 	 * Disable pull-up on:

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