ARM: mediatek: Add basic support for mt6592
Subsystems (6)
PATCH v4 1/3 ARM: mediatek: Add basic support for mt6592
* A dtsi for boards based on Mediatek MT6592 SoCs
* Compatible string in arch/arm/mach-mediatek/mediatek.c
Signed-off-by Howard Chen <[email protected]>
--- arch/arm/boot/dts/mt6592.dtsi | 138 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mediatek/mediatek.c | 1 + 2 files changed, 139 insertions(+) create mode 100644 arch/arm/boot/dts/mt6592.dtsi
arch/arm/boot/dts/mt6592.dtsi new file +138 -0
@@ -0,0 +1,138 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Howard Chen <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt6592"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + cpu at 4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x4>; + }; + cpu at 5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x5>; + }; + cpu at 6 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x6>; + }; + cpu at 7 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x7>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: uart_clk { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer at 10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + gic: interrupt-controller at 10211000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>; + }; + + uart0: serial at 11002000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial at 11003000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial at 11004000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial at 11005000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; +};
arch/arm/mach-mediatek/mediatek.c +1 -0
@@ -19,6 +19,7 @@static const char *const mediatek_board_dt_compat[] = {"mediatek,mt6589" , +"mediatek,mt6592" ,NULL , };
Signature · 1 line
1.9.1
PATCH v4 2/3 ARM: mediatek: add dts for mt6592-evb
The mt6592-evb is an evaluation board based on the MT6592 SoC.
Signed-off-by Howard Chen <[email protected]>
--- arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/mt6592-evb.dts | 45 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mt6592-evb.dts
arch/arm/boot/dts/Makefile +2 -1
@@ -514,7 +514,8 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ dove-d2plug.dtb \ dove-d3plug.dtb \ dove-dove-db.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \ + mt6592-evb.dtb targets += dtbs dtbs_install targets += $(dtb-y)
arch/arm/boot/dts/mt6592-evb.dts new file +45 -0
45 lines not on this page · raw message
Signature · 1 line
1.9.1
PATCH v4 3/3 dt-bindings: add documentation for Mediatek SoC
In reply to Howard ChenThis adds a DT binding documentation for the MT6592 SoC from Mediatek.
Signed-off-by Howard Chen <[email protected]>
--- Documentation/devicetree/bindings/arm/mediatek.txt | 7 +++++-- Documentation/devicetree/bindings/serial/mtk-uart.txt | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/arm/mediatek.txt +5 -2
@@ -1,10 +1,10 @@ Mediatek MT6589 Platforms Device Tree Bindings -Boards with a SoC of the Mediatek MT6589 shall have the following property: +Boards with a SoC from Mediatek shall have the following property: Required root node property: -compatible: must contain "mediatek,mt6589" +compatible: must contain one of "mediatek,mt6589", "mediatek,mt6592" Supported boards:
@@ -12,3 +12,6 @@ Supported boards: - bq Aquaris5 smart phone: Required root node properties: - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; + +- Evaluation board for MT6592: + - compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
Documentation/devicetree/bindings/serial/mtk-uart.txt +2 -1
@@ -2,9 +2,10 @@ Required properties: - compatible should contain: + * "mediatek,mt6592-uart" for MT6592 compatible UARTS * "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6582-uart" for MT6582 compatible UARTS - * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577) + * "mediatek,mt6577-uart" for all compatible UARTS on MT65xx - reg: The base address of the UART register bank.
Signature · 1 line
1.9.1
Matthias Brugger
maintainer2014-10-20 5:23 GMT+02:00 Howard Chen <[email protected]>:
Quoted 102 lines
* A dtsi for boards based on Mediatek MT6592 SoCs
* Compatible string inarch/arm/mach-mediatek/mediatek.cSigned-off-by Howard Chen <[email protected]>--- arch/arm/boot/dts/mt6592.dtsi | 138 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mediatek/mediatek.c | 1 + 2 files changed, 139 insertions(+) create mode 100644 arch/arm/boot/dts/mt6592.dtsiarch/arm/boot/dts/mt6592.dtsi new file +86
-0@@ -0,0 +1,138 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Howard Chen <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt6592"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + cpu at 4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x4>; + }; + cpu at 5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x5>; + }; + cpu at 6 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x6>; + }; + cpu at 7 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x7>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: uart_clk { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; +
arch/arm/boot/dts/mt6592.dtsi line 96
Quoted 10 lines
arch/arm/boot/dts/mt6592.dtsi new file +10
-0+ timer: timer at 10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + gic: interrupt-controller at 10211000 { + compatible = "arm,cortex-a9-gic";
Should be arm,cortex-a7-gic, right?
arch/arm/boot/dts/mt6592.dtsi line 107
Quoted 11 lines
arch/arm/boot/dts/mt6592.dtsi new file +11
-0+ interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>; + }; + + uart0: serial at 11002000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
I tried this on v3.18-rc1 but it does not boot for me. I think this depends on different bootloader on the different platforms. This is critical for me. Can you send me your intpol register values, so that I can check with my values when booting the kernel?
Quoted 46 lines
arch/arm/boot/dts/mt6592.dtsi new file +31
-0+ clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial at 11003000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial at 11004000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial at 11005000 { + compatible = "mediatek,mt6592-uart", "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + reg-shift = <2>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>; + status = "disabled"; + }; +};arch/arm/mach-mediatek/mediatek.c +1
-1@@ -19,6 +19,7 @@static const char *const mediatek_board_dt_compat[] = {"mediatek,mt6589" , +"mediatek,mt6592" ,NULL , }; --1.9.1
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