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4xx: EP405 boards support for arch/powerpc

POWERPC Dan Carpenter 3 participants 3 messages Oct 20, 2014

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Dan Carpenter

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#0 lore raw

Hello Benjamin Herrenschmidt,

The patch 619740384ceb: "[POWERPC] 4xx: EP405 boards support for arch/powerpc" from Dec 21, 2007, leads to the following static checker warning:

	arch/powerpc/boot/4xx.c:567 ibm405gp_fixup_clocks()
	warn: shifting and masking to zero

arch/powerpc/boot/4xx.c
562 fbdv = (pllmr & 0x1e000000) >> 25;
563 if (fbdv == 0)
564 fbdv = 16;

   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
                         ^^^^^^^^^^^^^^^^^^^^^^^^^

This mask and shift means that ppdv is always 1.

   568          epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
   569          udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
   570  
   571          /* check for 405GPr */
   572          if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
   573                  fwdvb = 8 - (pllmr & 0x00000007);
   574                  if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
   575                          if (psr & 0x00000020) /* New mode enable */
   576                                  m = fwdvb * 2 * ppdv;
   577                          else
   578                                  m = fwdvb * cbdv * ppdv;

regards,
dan carpenter

#1 lore raw
Quoted 5 lines · Dan Carpenter

Hello Benjamin Herrenschmidt,

The patch 619740384ceb: "[POWERPC] 4xx: EP405 boards support for arch/powerpc" from Dec 21, 2007, leads to the following static checker warning:

Ah, I even forgot I wrote that ... I'll have to dig out the docs of that chip, maybe later this week. Thanks !

Cheers,
Ben.

Quoted 27 lines
	arch/powerpc/boot/4xx.c:567 ibm405gp_fixup_clocks()
	warn: shifting and masking to zero

arch/powerpc/boot/4xx.c

   562          fbdv = (pllmr & 0x1e000000) >> 25;
   563          if (fbdv == 0)
   564                  fbdv = 16;
   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
                         ^^^^^^^^^^^^^^^^^^^^^^^^^

This mask and shift means that ppdv is always 1.

   568          epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
   569          udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
   570  
   571          /* check for 405GPr */
   572          if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
   573                  fwdvb = 8 - (pllmr & 0x00000007);
   574                  if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
   575                          if (psr & 0x00000020) /* New mode enable */
   576                                  m = fwdvb * 2 * ppdv;
   577                          else
   578                                  m = fwdvb * cbdv * ppdv;

regards,
dan carpenter

#2 lore raw

Dear Ben,

Quoted 3 lines · In message <1413802359.18300.7.camel@pasglop> you wrote:

Ah, I even forgot I wrote that ... I'll have to dig out the docs of that chip, maybe later this week. Thanks !

...

Quoted 5 lines
Quoted 5 lines
   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
                         ^^^^^^^^^^^^^^^^^^^^^^^^^

This mask and shift means that ppdv is always 1.

See 7.7.1 PLL Mode Register (CPC0_PLLMR) page 7.10f:

Bits 17:18 PPDV PCI­PLB Frequency Divisor

So that should be (... & 0x00006000) >> 13 ?

Best regards,

Wolfgang Denk

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