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ARM: sunxi: Add Allwinner A23 (sun8i) support

PATCH New Chen-Yu Tsai 2 participants 10 messages Oct 22, 2014

Subsystems (3)
Arm (32-bit) MMC, SD and SDIO Arm/Allwinner sunXi SoC support
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Chen-Yu Tsai

author
#0 lore raw

v2 cover ARM: sunxi: Add Allwinner A23 (sun8i) support

Hi everyone,

This series adds support for Allwinner's A23 SoC. All the patches are either direct cherry-picks or changes manually merged from u-boot-sunxi.

Patch 1 adds uart0 pinmux values for A23.

Patch 2 adds support for using uart0 on port F, either using a breakout board or soldering wires to exposed pads. At least one version of A23 tablets requires this, as no other uarts are exposed.

Patch 3 adds support for sun8i in the mmc driver. This is the same as sun6i.

Patch 4 adds machine support for sun8i.

Patch 5 adds support for gpio banks L and beyond, which is used by r_uart, p2wi (on sun6i) and rsb (on sun8i).

Patch 6 makes the prcm apb0 clock enabling function to take an argument for which modules should be enabled.

Patch 7 adds support for using r_uart as a console (with CONS_INDEX=5).

Patch 8 adds a defconfig for the Ippo Q8H A23 tablet board.

Changes since v1:

- Dropped "ARM: sunxi: Fix build break when CONFIG_MMC is not defined" (already merged)
- Add clarifying comment about SUNXI_GPIO_BANKS macro
- Correct R_PIO L pin bank starting offset
- Check for R_PIO pins by matching against L pin bank start pin number

Cheers
ChenYu

Chen-Yu Tsai (7):
ARM: sunxi: Add sun8i (A23) UART0 pin mux support
ARM: sunxi: Add support for uart0 on port F (mmc0)
mmc: sunxi: Add support for sun8i (A23)
ARM: sunxi: Add basic A23 support
ARM: sunxi: Allow specifying module in prcm apb0 init function
ARM: sunxi: Add support for using R_UART as console
ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig

Hans de Goede (1):
ARM: sunxi: Add support for R_PIO gpio banks

 arch/arm/Kconfig                        |  3 +++
 arch/arm/cpu/armv7/sunxi/Makefile       |  2 ++
 arch/arm/cpu/armv7/sunxi/board.c        | 18 +++++++++++++--
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c  |  6 +++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c     |  2 ++
 arch/arm/cpu/armv7/sunxi/prcm.c         | 12 +++++-----
 arch/arm/include/asm/arch-sunxi/clock.h |  2 +-
 arch/arm/include/asm/arch-sunxi/cpu.h   |  1 +
 arch/arm/include/asm/arch-sunxi/gpio.h  | 40 +++++++++++++++++++++++++++++++--
 arch/arm/include/asm/arch-sunxi/mmc.h   |  2 +-
 arch/arm/include/asm/arch-sunxi/prcm.h  |  2 +-
 board/sunxi/Kconfig                     |  3 ++-
 board/sunxi/MAINTAINERS                 |  5 +++++
 configs/Ippo_q8h_defconfig              |  4 ++++
 drivers/mmc/sunxi_mmc.c                 |  2 +-
 include/configs/sun8i.h                 | 23 +++++++++++++++++++
 include/configs/sunxi-common.h          |  3 +++
 17 files changed, 116 insertions(+), 14 deletions(-)
 create mode 100644 configs/Ippo_q8h_defconfig
 create mode 100644 include/configs/sun8i.h
Signature · 1 line
2.1.1
author
#1 lore raw

PATCH v2 1/8 ARM: sunxi: Add sun8i (A23) UART0 pin mux support

UART0 pin muxes on the A23 have a different function value.

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/include/asm/arch-sunxi/gpio.h +6 -0
index 59122db..7e2b169 100644
@@ -127,8 +127,14 @@ enum sunxi_gpio_number {
 #define SUNXI_GPF0_SDC0		2
 
 #define SUNXI_GPF2_SDC0		2
+
+#ifdef CONFIG_SUN8I
+#define SUNXI_GPF2_UART0_TX	3
+#define SUNXI_GPF4_UART0_RX	3
+#else
 #define SUNXI_GPF2_UART0_TX	4
 #define SUNXI_GPF4_UART0_RX	4
+#endif
 
 #define SUN4I_GPG0_SDC1		4
Signature · 1 line
2.1.1
author
#2 lore raw

PATCH v2 2/8 ARM: sunxi: Add support for uart0 on port F (mmc0)

In reply to Chen-Yu Tsai

Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0.

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 arch/arm/cpu/armv7/sunxi/board.c | 11 ++++++++++-
 include/configs/sunxi-common.h   |  2 ++
 2 files changed, 12 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/sunxi/board.c +10 -1
index b6d63db..29d45b6 100644
@@ -50,7 +50,16 @@ u32 spl_boot_mode(void)
 
 int gpio_init(void)
 {
-#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
include/configs/sunxi-common.h +2 -0
index a8d08b4..6ba9df6 100644
@@ -77,6 +77,7 @@
 #define CONFIG_INITRD_TAG
 
 /* mmc config */
+#if !defined(CONFIG_UART0_PORT_F)
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_MMC

@@ -84,6 +85,7 @@
 #define CONFIG_MMC_SUNXI_SLOT		0
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
+#endif
 
 /* 4MB of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
Signature · 1 line
2.1.1
author
#3 lore raw

PATCH v2 3/8 mmc: sunxi: Add support for sun8i (A23)

In reply to Chen-Yu Tsai

The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i.

Re-use code added for sun6i.

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/mmc.h | 2 +-
 drivers/mmc/sunxi_mmc.c               | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-sunxi/mmc.h +1 -1
index 70d7875..8a21674 100644
@@ -43,7 +43,7 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-#if defined(CONFIG_SUN6I)
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
 	u32 res2[64];
 #endif
 	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
drivers/mmc/sunxi_mmc.c +1 -1
index d3b1039..16592e3 100644
@@ -75,7 +75,7 @@ static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
-#if defined(CONFIG_SUN6I)
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
 	/* unassert reset */
 	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 #endif
Signature · 1 line
2.1.1
author
#4 lore raw

PATCH v2 4/8 ARM: sunxi: Add basic A23 support

In reply to Chen-Yu Tsai

The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.

There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization.

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 arch/arm/Kconfig                        |  3 +++
 arch/arm/cpu/armv7/sunxi/Makefile       |  2 ++
 arch/arm/cpu/armv7/sunxi/board.c        |  3 ++-
 arch/arm/cpu/armv7/sunxi/cpu_info.c     |  2 ++
 arch/arm/include/asm/arch-sunxi/clock.h |  2 +-
 board/sunxi/Kconfig                     |  3 ++-
 include/configs/sun8i.h                 | 23 +++++++++++++++++++++++
 7 files changed, 35 insertions(+), 3 deletions(-)
 create mode 100644 include/configs/sun8i.h
arch/arm/Kconfig +3 -0
index 8bcb7e3..cff7ad9 100644
@@ -450,6 +450,9 @@ config TARGET_SUN6I
 config TARGET_SUN7I
 	bool "Support sun7i"
 
+config TARGET_SUN8I
+	bool "Support sun8i"
+
 config TARGET_SNOWBALL
 	bool "Support snowball"
arch/arm/cpu/armv7/sunxi/Makefile +2 -0
index 2a42dca..24f1dae 100644
@@ -12,10 +12,12 @@ obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= pinmux.o
 obj-$(CONFIG_SUN6I)	+= prcm.o
+obj-$(CONFIG_SUN8I)	+= prcm.o
 obj-$(CONFIG_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_SUN7I)	+= clock_sun4i.o
+obj-$(CONFIG_SUN8I)	+= clock_sun6i.o
 
 ifndef CONFIG_SPL_BUILD
 obj-y	+= cpu_info.o
arch/arm/cpu/armv7/sunxi/board.c +2 -1
index 29d45b6..61c1ba9 100644
@@ -100,7 +100,8 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
+		defined CONFIG_SUN6I || defined CONFIG_SUN8I)
 	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 	asm volatile(
 		"mrc p15, 0, r0, c1, c0, 1\n"
arch/arm/cpu/armv7/sunxi/cpu_info.c +2 -0
index 40c4e13..4f2a09c 100644
@@ -27,6 +27,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner A31 (SUN6I)\n");
 #elif defined CONFIG_SUN7I
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
+#elif defined CONFIG_SUN8I
+	puts("CPU:   Allwinner A23 (SUN8I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
arch/arm/include/asm/arch-sunxi/clock.h +1 -1
index 8f5d860..012c2af 100644
@@ -15,7 +15,7 @@
 #define CLK_GATE_CLOSE			0x0
 
 /* clock control module regs definition */
-#ifdef CONFIG_SUN6I
+#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
 #include <asm/arch/clock_sun6i.h>
 #else
 #include <asm/arch/clock_sun4i.h>
board/sunxi/Kconfig +2 -1
index 4ac562c..7fe9005 100644
@@ -1,4 +1,4 @@
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
 
 config SYS_CONFIG_NAME
 	string

@@ -6,6 +6,7 @@ config SYS_CONFIG_NAME
 	default "sun5i" if TARGET_SUN5I
 	default "sun6i" if TARGET_SUN5I
 	default "sun7i" if TARGET_SUN7I
+	default "sun8i" if TARGET_SUN8I
 
 config SYS_CPU
 	default "armv7"
include/configs/sun8i.h new file +23 -0
new file mode 100644
index 0000000..1c1a7cd
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Chen-Yu Tsai <[email protected]>
+ *
+ * Configuration settings for the Allwinner A23 (sun8i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A23 specific configuration
+ */
+#define CONFIG_SUN8I		/* sun8i SoC generation */
+#define CONFIG_SYS_PROMPT	"sun8i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
Signature · 1 line
2.1.1
author
#5 lore raw

PATCH v2 5/8 ARM: sunxi: Add support for R_PIO gpio banks

In reply to Chen-Yu Tsai

From: Hans de Goede <[email protected]>

The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.

Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller.

Signed-off-by Hans de Goede <[email protected]>
[wens at csie.org: expanded commit message]
[wens at csie.org: add pin bank M and expand comments]
[wens at csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by Chen-Yu Tsai <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/gpio.h | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-sunxi/gpio.h +29 -2
index 7e2b169..de7a86a 100644
@@ -10,6 +10,7 @@
 #define _SUNXI_GPIO_H
 
 #include <linux/types.h>
+#include <asm/arch/cpu.h>
 
 /*
  * sunxi has 9 banks of gpio, they are:

@@ -27,8 +28,27 @@
 #define SUNXI_GPIO_G	6
 #define SUNXI_GPIO_H	7
 #define SUNXI_GPIO_I	8
+
+/*
+ * This defines the number of GPIO banks for the _main_ GPIO controller.
+ * You should fix up the padding in struct sunxi_gpio_reg below if you
+ * change this.
+ */
 #define SUNXI_GPIO_BANKS 9
 
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8  | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ */
+#define SUNXI_GPIO_L	11
+#define SUNXI_GPIO_M	12
+
 struct sunxi_gpio {
 	u32 cfg[4];
 	u32 dat;

@@ -50,8 +70,9 @@ struct sunxi_gpio_reg {
 	struct sunxi_gpio_int gpio_int;
 };
 
-#define BANK_TO_GPIO(bank) \
-	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]
+#define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
+	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
 
 #define GPIO_BANK(pin)		((pin) >> 5)
 #define GPIO_NUM(pin)		((pin) & 0x1f)

@@ -75,6 +96,8 @@ struct sunxi_gpio_reg {
 #define SUNXI_GPIO_G_NR		32
 #define SUNXI_GPIO_H_NR		32
 #define SUNXI_GPIO_I_NR		32
+#define SUNXI_GPIO_L_NR		32
+#define SUNXI_GPIO_M_NR		32
 
 #define SUNXI_GPIO_NEXT(__gpio) \
 	((__gpio##_START) + (__gpio##_NR) + 0)

@@ -89,6 +112,8 @@ enum sunxi_gpio_number {
 	SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
 	SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
 	SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+	SUNXI_GPIO_L_START = 352,
+	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
 };
 
 /* SUNXI GPIO number definitions */

@@ -101,6 +126,8 @@ enum sunxi_gpio_number {
 #define SUNXI_GPG(_nr)	(SUNXI_GPIO_G_START + (_nr))
 #define SUNXI_GPH(_nr)	(SUNXI_GPIO_H_START + (_nr))
 #define SUNXI_GPI(_nr)	(SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr)	(SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
 
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
Signature · 1 line
2.1.1
#6 lore raw

PATCH v2 5/8 ARM: sunxi: Add support for R_PIO gpio banks

Quoted 5 lines · Chen-Yu Tsai

From: Hans de Goede <[email protected]>

The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.

Quoted 8 lines

Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller.

Signed-off-by Hans de Goede <[email protected]>
[wens at csie.org: expanded commit message]
[wens at csie.org: add pin bank M and expand comments]
[wens at csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
author
#7 lore raw

PATCH v2 6/8 ARM: sunxi: Allow specifying module in prcm apb0 init function

In reply to Chen-Yu Tsai

The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused.

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 arch/arm/cpu/armv7/sunxi/prcm.c        | 12 +++++++-----
 arch/arm/include/asm/arch-sunxi/prcm.h |  2 +-
 2 files changed, 8 insertions(+), 6 deletions(-)
arch/arm/cpu/armv7/sunxi/prcm.c +7 -5
index 7b3ee89..19b4938 100644
@@ -21,13 +21,15 @@
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
-void prcm_init_apb0(void)
+/* APB0 clock gate and reset bit offsets are the same. */
+void prcm_apb0_enable(u32 flags)
 {
 	struct sunxi_prcm_reg *prcm =
 		(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
 
-	setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
-				       PRCM_APB0_GATE_PIO);
-	setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
-					PRCM_APB0_RESET_PIO);
+	/* open the clock for module */
+	setbits_le32(&prcm->apb0_gate, flags);
+
+	/* deassert reset for module */
+	setbits_le32(&prcm->apb0_reset, flags);
 }
arch/arm/include/asm/arch-sunxi/prcm.h +1 -1
index 1b40f09..3d3bfa6 100644
@@ -233,6 +233,6 @@ struct sunxi_prcm_reg {
 	u32 dram_tst;		/* 0x190 */
 };
 
-void prcm_init_apb0(void);
+void prcm_apb0_enable(u32 flags);
 #endif /* __ASSEMBLY__ */
 #endif /* _PRCM_H */
Signature · 1 line
2.1.1
author
#8 lore raw

PATCH v2 7/8 ARM: sunxi: Add support for using R_UART as console

In reply to Chen-Yu Tsai

The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a console while using mmc.

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 arch/arm/cpu/armv7/sunxi/board.c       | 4 ++++
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++++++
 arch/arm/include/asm/arch-sunxi/cpu.h  | 1 +
 arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
 include/configs/sunxi-common.h         | 1 +
 5 files changed, 15 insertions(+)
arch/arm/cpu/armv7/sunxi/board.c +4 -0
index 61c1ba9..aeb2c2f 100644
@@ -75,6 +75,10 @@ int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
 	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
 #endif
arch/arm/cpu/armv7/sunxi/clock_sun6i.c +6 -0
index 8387b93..1eae976 100644
@@ -13,6 +13,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
 void clock_init_uart(void)

@@ -20,6 +21,7 @@ void clock_init_uart(void)
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+#if CONFIG_CONS_INDEX < 5
 	/* uart clock source is apb2 */
 	writel(APB2_CLK_SRC_OSC24M|
 	       APB2_CLK_RATE_N_1|

@@ -35,6 +37,10 @@ void clock_init_uart(void)
 	setbits_le32(&ccm->apb2_reset_cfg,
 		     1 << (APB2_RESET_UART_SHIFT +
 			   CONFIG_CONS_INDEX - 1));
+#else
+	/* enable R_PIO and R_UART clocks, and de-assert resets */
+	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
 
 	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
arch/arm/include/asm/arch-sunxi/cpu.h +1 -0
index 313e6c8..0de79a0 100644
@@ -111,6 +111,7 @@
 #define SUNXI_AVG_BASE			0x01ea0000
 
 #define SUNXI_PRCM_BASE			0x01f01400
+#define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUNXI_P2WI_BASE			0x01f03400
arch/arm/include/asm/arch-sunxi/gpio.h +3 -0
index de7a86a..7bb6499 100644
@@ -172,6 +172,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPI4_SDC3		2
 
+#define SUN8I_GPL2_R_UART_TX	2
+#define SUN8I_GPL3_R_UART_RX	2
+
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
 #define SUNXI_GPIO_PULL_UP	1
include/configs/sunxi-common.h +1 -0
index 6ba9df6..97fd9e2 100644
@@ -42,6 +42,7 @@
 #define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
 #define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
 #define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+#define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
Signature · 1 line
2.1.1
author
#9 lore raw

PATCH v2 8/8 ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig

In reply to Chen-Yu Tsai

Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same.

See: http://linux-sunxi.org/Ippo_q8h

Signed-off-by Chen-Yu Tsai <[email protected]>
Acked-by Ian Campbell <[email protected]>
---
 board/sunxi/MAINTAINERS    | 5 +++++
 configs/Ippo_q8h_defconfig | 4 ++++
 2 files changed, 9 insertions(+)
 create mode 100644 configs/Ippo_q8h_defconfig
board/sunxi/MAINTAINERS +5 -0
index 7afe45e..febd126 100644
@@ -50,3 +50,8 @@ COLOMBUS BOARD
 M:	Maxime Ripard <[email protected]>
 S:	Maintained
 F:	configs/Colombus_defconfig
+
+IPPO-Q8H-V5 BOARD
+M:	CHen-Yu Tsai <[email protected]>
+S:	Maintained
+F:	configs/Ippo_q8h_v5_defconfig
configs/Ippo_q8h_defconfig new file +4 -0
new file mode 100644
index 0000000..781f137
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="IPPO_Q8H_V5,CONS_INDEX=5"
+CONFIG_ARM=y
+CONFIG_TARGET_SUN8I=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
Signature · 1 line
2.1.1