Legacy instruction emulation for arm64
Subsystems (2)
v3 cover Legacy instruction emulation for arm64
Hi,
This is the third posting of the legacy instruction support for arm64. Previous postings can be found at [1][2].
The patchset creates the infrastructure to support legacy instruction emulation and then uses this to add support for the emulation of SWP{B} and CP15 Barrier instructions from ARMv7 to the v8 port of Linux. When available, the common infrastructure allows for enabling the hardware execution of legacy instructions. Runtime support for changing the execution mode - undef, legacy, or hw execution is provided via nodes in sysctl. The default behaviour varies with the state of the instruction in the architecture (deprecated or obsolete) and is documented as part of this series.
Patches 1-2/5 add infrastructure code to add support for undefined instruction hooks and decoding condition checks.
Patch 3-4/5 adds infrastructure to support legacy instruction emulation and uses this to then add support for SWP and CP15 barriers respectively.
Patch 5/5 introduces a trace point to log instruction emulation and then uses this to trace the usage of the above instructions when using emulation.
Cheers,
Punit
Changes since [2]:
* Made trace point local to arm64
* Re-factored infrastructure to handle registration / un-registration of undefined hooks as well as handle enabling hardware execution when supported
* Added documentation for default execution modes and how to change it via sysctl
Changes since [1]:
* Added support for Thumb instructions when registering undefined hooks as well
* Emulation support is now added to armv8_deprecated.c (was previously v7_obsolete.c)
* Instruction support level - Off, Emulate or Enable (when supported in hardware) - is now controlled through sysctl
* Using trace points instead of debugfs for stats reporting
[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/351054
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/292213.html
Punit Agrawal (5):
arm64: Add support for hooks to handle undefined instructions
arm64: Add AArch32 instruction set condition code checks
arm64: Port SWP/SWPB emulation support from arm
arm64: Emulate CP15 Barrier instructions
arm64: Trace emulation of AArch32 legacy instructions
Documentation/arm64/legacy_instructions.txt | 45 +++ arch/arm64/Kconfig | 54 +++ arch/arm64/include/asm/insn.h | 10 + arch/arm64/include/asm/opcodes.h | 1 + arch/arm64/include/asm/traps.h | 16 + arch/arm64/kernel/Makefile | 6 +- arch/arm64/kernel/armv8_deprecated.c | 541 ++++++++++++++++++++++++++++ arch/arm64/kernel/insn.c | 26 ++ arch/arm64/kernel/trace-events-emulation.h | 40 ++ arch/arm64/kernel/traps.c | 68 ++++ 10 files changed, 806 insertions(+), 1 deletion(-) create mode 100644 Documentation/arm64/legacy_instructions.txt create mode 100644 arch/arm64/include/asm/opcodes.h create mode 100644 arch/arm64/kernel/armv8_deprecated.c create mode 100644 arch/arm64/kernel/trace-events-emulation.h
Signature · 1 line
2.1.1
PATCH v3 1/5 arm64: Add support for hooks to handle undefined instructions
Add support to register hooks for undefined instructions. The handlers will be called when the undefined instruction and the processor state (as contained in pstate) match criteria used at registration.
--- arch/arm64/include/asm/insn.h | 2 ++ arch/arm64/include/asm/traps.h | 16 ++++++++++ arch/arm64/kernel/insn.c | 5 ++++ arch/arm64/kernel/traps.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+)
arch/arm64/include/asm/insn.h +2 -0
@@ -354,6 +354,8 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);int aarch64_insn_patch_text_nosync (void *addr,u32 insn);int aarch64_insn_patch_text_sync (void *addrs[],u32 insns[],int cnt);int aarch64_insn_patch_text (void *addrs[],u32 insns[],int cnt); + +bool aarch32_insn_is_wide_instruction (u32 insn);#endif /* __ASSEMBLY__ */ #endif /* __ASM_INSN_H */
arch/arm64/include/asm/traps.h +16 -0
@@ -18,6 +18,22 @@#ifndef __ASM_TRAP_H#define __ASM_TRAP_H +#include <linux/list.h> + +struct pt_regs ; + +struct undef_hook { +struct list_head node; +u32 instr_mask; +u32 instr_val; +u64 pstate_mask; +u64 pstate_val; +int (*fn)(struct pt_regs *regs,u32 instr); +}; + +int register_undef_hook (struct undef_hook *hook); +void unregister_undef_hook (struct undef_hook *hook); +static inline int in_exception_text (unsigned long ptr) {extern char __exception_text_start[];
arch/arm64/kernel/insn.c +5 -0
@@ -959,3 +959,8 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,return aarch64_insn_encode_immediate (AARCH64_INSN_IMM_6 , insn, shift); } + +bool aarch32_insn_is_wide_instruction (u32 insn) +{ +return insn >=0xe800 ; +}
arch/arm64/kernel/traps.c +33 -0
@@ -259,3 +259,36 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, } } +static LIST_HEAD (undef_hook); +static DEFINE_RAW_SPINLOCK (undef_lock); + +int register_undef_hook (struct undef_hook *hook) +{ +unsigned long flags; + +raw_spin_lock_irqsave (&undef_lock, flags); +list_add (&hook->node, &undef_hook); +raw_spin_unlock_irqrestore (&undef_lock, flags); + +return 0 ; +} + +void unregister_undef_hook (struct undef_hook *hook) +{ +unsigned long flags; + +raw_spin_lock_irqsave (&undef_lock, flags); +list_del (&hook->node); +raw_spin_unlock_irqrestore (&undef_lock, flags); +} + +static int call_undef_hook (struct pt_regs *regs) +{ +struct undef_hook *hook; +unsigned long flags; +u32 instr; +int (*fn)(struct pt_regs *regs,u32 instr) =NULL ; +void __user *pc = (void __user *)instruction_pointer (regs); + +if (!user_mode (regs)) +return 1 ;
+
+ if (compat_thumb_mode(regs)) {
+ /* 16-bit Thumb instruction */
+ if (get_user(instr, (u16 __user *)pc))
+ goto exit;
+ instr = le16_to_cpu(instr);
+ if (aarch32_insn_is_wide_instruction(instr)) {
+ u32 instr2;
+
+ if (get_user(instr2, (u16 __user *)(pc + 2)))
+ goto exit;
+ instr2 = le16_to_cpu(instr2);
+ instr = (instr << 16) | instr2;
+ }
+ } else {
+ /* 32-bit ARM instruction */
+ if (get_user(instr, (u32 __user *)pc))
+ goto exit;
+ instr = le32_to_cpu(instr);
+ }
+
+ raw_spin_lock_irqsave(&undef_lock, flags);
+ list_for_each_entry(hook, &undef_hook, node)
+ if ((instr & hook->instr_mask) == hook->instr_val &&
+ (regs->pstate & hook->pstate_mask) == hook->pstate_val)
+ fn = hook->fn;
+
+ raw_spin_unlock_irqrestore(&undef_lock, flags);
+exit:
+ return fn ? fn(regs, instr) : 1;
+}
+
asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
{
siginfo_t info;
@@ -268,6 +333,9 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
if (!aarch32_break_handler(regs))
return;
+ if (call_undef_hook(regs) == 0)
+ return;
+
if (show_unhandled_signals && unhandled_signal(current, SIGILL) &&
printk_ratelimit()) {
pr_info("%s[%d]: undefined instruction: pc=%p\n",
Signature · 1 line
2.1.1
Catalin Marinas
maintainerPATCH v3 1/5 arm64: Add support for hooks to handle undefined instructions
arch/arm64/include/asm/insn.h bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); · line 358
Quoted 8 lines · Punit Agrawal
arch/arm64/include/asm/insn.h +2
-0@@ -354,6 +354,8 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);int aarch64_insn_patch_text_nosync (void *addr,u32 insn);int aarch64_insn_patch_text_sync (void *addrs[],u32 insns[],int cnt);int aarch64_insn_patch_text (void *addrs[],u32 insns[],int cnt); + +bool aarch32_insn_is_wide_instruction (u32 insn);
Nitpick: too wide function name ;). Maybe aarch32_insn_is_wide().
Otherwise the patch looks fine.
PATCH v3 1/5 arm64: Add support for hooks to handle undefined instructions
Quoted 11 lines · Catalin Marinas
arch/arm64/include/asm/insn.h bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); · line 358
Quoted 8 lines · Punit Agrawal
arch/arm64/include/asm/insn.h +2
-0@@ -354,6 +354,8 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);int aarch64_insn_patch_text_nosync (void *addr,u32 insn);int aarch64_insn_patch_text_sync (void *addrs[],u32 insns[],int cnt);int aarch64_insn_patch_text (void *addrs[],u32 insns[],int cnt); + +bool aarch32_insn_is_wide_instruction (u32 insn);Nitpick: too wide function name ;). Maybe
aarch32_insn_is_wide().
Agreed. I'll change it to aarch32_insn_is_wide(). Please shout if you can think of a better name.
Quoted 4 lines
Otherwise the patch looks fine.
Reviewed-by Catalin Marinas <[email protected]>
Thanks.
Quoted 5 lines
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linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v3 1/5 arm64: Add support for hooks to handle undefined instructions
In reply to Punit AgrawalAdd support to register hooks for undefined instructions. The handlers will be called when the undefined instruction and the processor state (as contained in pstate) match criteria used at registration.
--- arch/arm64/include/asm/insn.h | 2 ++ arch/arm64/include/asm/traps.h | 16 ++++++++++ arch/arm64/kernel/insn.c | 5 ++++ arch/arm64/kernel/traps.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+)
arch/arm64/include/asm/insn.h +2 -0
@@ -354,6 +354,8 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);int aarch64_insn_patch_text_nosync (void *addr,u32 insn);int aarch64_insn_patch_text_sync (void *addrs[],u32 insns[],int cnt);int aarch64_insn_patch_text (void *addrs[],u32 insns[],int cnt); + +bool aarch32_insn_is_wide_instruction (u32 insn);#endif /* __ASSEMBLY__ */ #endif /* __ASM_INSN_H */
arch/arm64/include/asm/traps.h +16 -0
@@ -18,6 +18,22 @@#ifndef __ASM_TRAP_H#define __ASM_TRAP_H +#include <linux/list.h> + +struct pt_regs ; + +struct undef_hook { +struct list_head node; +u32 instr_mask; +u32 instr_val; +u64 pstate_mask; +u64 pstate_val; +int (*fn)(struct pt_regs *regs,u32 instr); +}; + +int register_undef_hook (struct undef_hook *hook); +void unregister_undef_hook (struct undef_hook *hook); +static inline int in_exception_text (unsigned long ptr) {extern char __exception_text_start[];
arch/arm64/kernel/insn.c +5 -0
@@ -959,3 +959,8 @@ u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,return aarch64_insn_encode_immediate (AARCH64_INSN_IMM_6 , insn, shift); } + +bool aarch32_insn_is_wide_instruction (u32 insn) +{ +return insn >=0xe800 ; +}
arch/arm64/kernel/traps.c +68 -0
80 lines not on this page · raw message
Signature · 1 line
2.1.1
PATCH v3 1/5 arm64: Add support for hooks to handle undefined instructions
Quoted 4 lines · Punit Agrawal
Add support to register hooks for undefined instructions. The handlers will be called when the undefined instruction and the processor state (as contained in pstate) match criteria used at registration.
Quoted 8 lines
Signed-off-by Punit Agrawal <[email protected]>--- arch/arm64/include/asm/insn.h | 2 ++ arch/arm64/include/asm/traps.h | 16 ++++++++++ arch/arm64/kernel/insn.c | 5 ++++ arch/arm64/kernel/traps.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 91 insertions(+)
This patch was sent twice by mistake. Please ignore this copy.
[...]
PATCH v3 2/5 arm64: Add AArch32 instruction set condition code checks
In reply to Punit AgrawalPort support for AArch32 instruction condition code checking from arm to arm64.
--- arch/arm64/include/asm/opcodes.h | 1 + arch/arm64/kernel/Makefile | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/opcodes.h
arch/arm64/include/asm/opcodes.h new file +1 -0
@@ -0,0 +1 @@ +#include <../../arm/include/asm/opcodes.h>
arch/arm64/kernel/Makefile +3 -1
@@ -18,7 +18,9 @@ arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ cpuinfo.o arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ - sys_compat.o + sys_compat.o \ + $(addprefix ../../arm/kernel/, \ + opcodes.o) arm64-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o
Signature · 1 line
2.1.1
PATCH v3 2/5 arm64: Add AArch32 instruction set condition code checks
arch/arm64/kernel/Makefile arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ · line 23
Quoted 5 lines · Punit Agrawal
arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
arch/arm64/kernel/Makefile +3
-1- sys_compat.o + sys_compat.o \ + $(addprefix ../../arm/kernel/, \ + opcodes.o)
This is not particularly nice. While it means that this file gets built on both arm64 and arm, it means that it routinely won't get tested on arm64 when changes to it happen.
The second reason it's not nice is that the whole $(addprefix thing really isn't needed. You're only adding the prefix to one name. So, a simpler way to write it is "../../arm/kernel/opcodes.o".
Signature · 2 lines
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net.
PATCH v3 2/5 arm64: Add AArch32 instruction set condition code checks
Hi Russell,
Thanks for having a look.
Quoted 10 lines · Russell King - ARM Linux
arch/arm64/kernel/Makefile arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ · line 23
Quoted 5 lines · Punit Agrawal
arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
arch/arm64/kernel/Makefile +3
-1- sys_compat.o + sys_compat.o \ + $(addprefix ../../arm/kernel/, \ + opcodes.o)This is not particularly nice. While it means that this file gets built on both arm64 and arm, it means that it routinely won't get tested on arm64 when changes to it happen.
I agree. An earlier version of this patch copied opcodes.c to arm64 but then it wouldn't benefit from any fixes that would go in the original. The current approach misses out on the testing. Although better than the previous approach, it is not optimal.
Quoted 4 lines
The second reason it's not nice is that the whole $(addprefix thing really isn't needed. You're only adding the prefix to one name. So, a simpler way to write it is "
../../arm/kernel/opcodes.o".
This one is easy to make nice. Fixed in my local copy.
Cheers,
Punit
Catalin Marinas
maintainerPATCH v3 2/5 arm64: Add AArch32 instruction set condition code checks
In reply to Russell King - ARM LinuxQuoted 8 lines · Russell King - ARM Linux
arch/arm64/kernel/Makefile arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ · line 23
Quoted 5 lines · Punit Agrawal
arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
arch/arm64/kernel/Makefile +3
-1- sys_compat.o + sys_compat.o \ + $(addprefix ../../arm/kernel/, \ + opcodes.o)This is not particularly nice.
Not that bad, you can look at it as a decoding library.
Quoted 3 lines
While it means that this file gets built on both arm64 and arm, it means that it routinely won't get tested on arm64 when changes to it happen.
Low risk, it's a small file unlikely to change in the future.
Anyway, since you mention testing, I wonder how regularly SWP emulation gets tested on arm32 (and in future arm64). If Punit has some tests already, it may be good to add them somewhere like tools/testing/selftests/arm/ (probably separately from this series).
Signature · 1 line
Catalin
PATCH v3 2/5 arm64: Add AArch32 instruction set condition code checks
Quoted 4 lines · Catalin Marinas
Anyway, since you mention testing, I wonder how regularly SWP emulation gets tested on arm32 (and in future arm64). If Punit has some tests already, it may be good to add them somewhere like
tools/testing/selftests/arm/(probably separately from this series).
Sounds like you want atomic.h implemented using SWP and CP15 barriers ;)
There *is* lib/atomic64_test.c but, perversely, it's single-threaded and unlikely to spot issues even if we got it running in userspace.
Will
Catalin Marinas
maintainerPATCH v3 2/5 arm64: Add AArch32 instruction set condition code checks
In reply to Punit AgrawalQuoted 22 lines · Punit Agrawal
Port support for AArch32 instruction condition code checking from arm to arm64.
Signed-off-by Punit Agrawal <[email protected]>--- arch/arm64/include/asm/opcodes.h | 1 + arch/arm64/kernel/Makefile | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/opcodes.harch/arm64/include/asm/opcodes.h new file +1
-0@@ -0,0 +1 @@ +#include <../../arm/include/asm/opcodes.h> arch/arm64/kernel/Makefile +0
-0
arch/arm64/kernel/Makefile arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ · line 23
Quoted 7 lines
arch/arm64/kernel/Makefile +3
-1@@ -18,7 +18,9 @@ arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ cpuinfo.o arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ - sys_compat.o + sys_compat.o \ + $(addprefix ../../arm/kernel/, \ + opcodes.o)
Apart from the addprefix that Russell mentioned:
PATCH v3 3/5 arm64: Port SWP/SWPB emulation support from arm
In reply to Punit AgrawalTypically, providing support for legacy instructions requires emulating the behaviour of instructions whose encodings have become undefined. If the instructions haven't been removed from the architecture, there maybe an option in the implementation to turn on/off the support for these instructions.
Create common infrastructure to support legacy instruction emulation. In addition to emulation, also provide an option to support hardware execution when supported. The default execution mode (one of undef, emulate, hw exeuction) is dependent on the state of the instruction (deprecated or obsolete) in the architecture and can specified at the time of registering the instruction handlers. The runtime state of the emulation can be controlled by writing to individual nodes in sysctl. The expected default behaviour is documented as part of this patch.
Use the new infrastructure to port the emulation of the SWP and SWPB instructions using LDXR/STXR sequences from the arm port to arm64.
--- Documentation/arm64/legacy_instructions.txt | 40 +++ arch/arm64/Kconfig | 39 +++ arch/arm64/include/asm/insn.h | 6 + arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/armv8_deprecated.c | 402 ++++++++++++++++++++++++++++ arch/arm64/kernel/insn.c | 8 + 6 files changed, 496 insertions(+) create mode 100644 Documentation/arm64/legacy_instructions.txt create mode 100644 arch/arm64/kernel/armv8_deprecated.c
Documentation/arm64/legacy_instructions.txt new file +40 -0
@@ -0,0 +1,40 @@ +The arm64 port of the Linux kernel provides infrastructure to support +emulation of instructions which have been deprecated, or obsoleted in +the architecture. The infrastructure code uses undefined instruction +hooks to support emulation. Where available it also allows turning on +the instruction execution in hardware. + +The emulation mode can be controlled by writing to sysctl nodes +(/proc/sys/abi). The following explains the different execution +behaviours and the corresponding values of the sysctl nodes - + +* Undef + Value: 0 + Generates undefined instruction abort. Default for instructions that + have been obsoleted in the architecture, e.g., SWP + +* Emulate + Value: 1 + Uses software emulation. To aid migration of software, in this mode + usage of emulated instruction is traced as well as rate limited + warnings are issued. This is the default for deprecated + instructions, .e.g., CP15 barriers + +* Hardware Execution + Value: 2 + Although marked as deprecated, some implementations may support the + enabling/disabling of hardware support for the execution of these + instructions. Using hardware execution generally provides better + performance, but at the loss of ability to gather runtime statistics + about the use of the deprecated instructions. + +The default mode depends on the status of the instruction in the +architecture. Deprecated instructions should default to emulation +while obsolete instructions must be undefined by default. + +Supported legacy instructions +----------------------------- +* SWP{B} +Node: /proc/sys/abi/swp +Status: Obsolete +Default: Undef (0)
arch/arm64/Kconfig +39 -0
@@ -162,6 +162,45 @@ config ARCH_XGENE help This enables support for AppliedMicro X-Gene SOC Family +comment "Processor Features" + +menuconfig ARMV8_DEPRECATED + bool "Emulate deprecated/obsolete ARMv8 instructions" + depends on COMPAT + help + Legacy software support may require certain instructions + that have been deprecated or obsoleted in the architecture. + + Enable this config to enable selective emulation of these + features. + + If unsure, say N + +if ARMV8_DEPRECATED + +config SWP_EMULATION + bool "Emulate SWP/SWPB instructions" + help + ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that + they are always undefined. Say Y here to enable software + emulation of these instructions for userspace using LDXR/STXR. + + In some older versions of glibc [<=2.8] SWP is used during futex + trylock() operations with the assumption that the code will not + be preempted. This invalid assumption may be more likely to fail + with SWP emulation enabled, leading to deadlock of the user + application. + + NOTE: when accessing uncached shared regions, LDXR/STXR rely + on an external transaction monitoring block called a global + monitor to maintain update atomicity. If your system does not + implement a global monitor, this option can cause programs that + perform SWP operations to uncached memory to deadlock. + + If unsure, say N + +endif + endmenu menu "Bus support"
arch/arm64/include/asm/insn.h +6 -0
@@ -356,6 +356,12 @@ int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);int aarch64_insn_patch_text (void *addrs[],u32 insns[],int cnt);bool aarch32_insn_is_wide_instruction (u32 insn); + +#define A32_RN_OFFSET 16 +#define A32_RT_OFFSET 12 +#define A32_RT2_OFFSET 0 + +u32 aarch32_insn_extract_reg_num (u32 insn,int offset);#endif /* __ASSEMBLY__ */ #endif /* __ASM_INSN_H */
arch/arm64/kernel/Makefile +1 -0
@@ -33,6 +33,7 @@ arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o arm64-obj-$(CONFIG_PCI) += pci.o +arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m)
arch/arm64/kernel/armv8_deprecated.c new file +402 -0
402 lines not on this page · raw message
arch/arm64/kernel/insn.c +8 -0
@@ -964,3 +964,11 @@ bool aarch32_insn_is_wide_instruction(u32 insn) {return insn >=0xe800 ; } + +/* +* Macros/defines for extracting register numbers from instruction. +*/ +u32 aarch32_insn_extract_reg_num (u32 insn,int offset) +{ +return (insn & (0xf << offset)) >> offset; +}
Signature · 1 line
2.1.1
Catalin Marinas
maintainerPATCH v3 3/5 arm64: Port SWP/SWPB emulation support from arm
Quoted 54 lines · Punit Agrawal
Documentation/arm64/legacy_instructions.txt new file +40
-0@@ -0,0 +1,40 @@ +The arm64 port of the Linux kernel provides infrastructure to support +emulation of instructions which have been deprecated, or obsoleted in +the architecture. The infrastructure code uses undefined instruction +hooks to support emulation. Where available it also allows turning on +the instruction execution in hardware. + +The emulation mode can be controlled by writing to sysctl nodes +(/proc/sys/abi). The following explains the different execution +behaviours and the corresponding values of the sysctl nodes - + +* Undef + Value: 0 + Generates undefined instruction abort. Default for instructions that + have been obsoleted in the architecture, e.g., SWP + +* Emulate + Value: 1 + Uses software emulation. To aid migration of software, in this mode + usage of emulated instruction is traced as well as rate limited + warnings are issued. This is the default for deprecated + instructions, .e.g., CP15 barriers + +* Hardware Execution + Value: 2 + Although marked as deprecated, some implementations may support the + enabling/disabling of hardware support for the execution of these + instructions. Using hardware execution generally provides better + performance, but at the loss of ability to gather runtime statistics + about the use of the deprecated instructions. + +The default mode depends on the status of the instruction in the +architecture. Deprecated instructions should default to emulation +while obsolete instructions must be undefined by default. + +Supported legacy instructions +----------------------------- +* SWP{B} +Node: /proc/sys/abi/swp +Status: Obsolete +Default: Undef (0)arch/arm64/Kconfig +3
-0@@ -162,6 +162,45 @@ config ARCH_XGENE help This enables support for AppliedMicro X-Gene SOC Family +comment "Processor Features" + +menuconfig ARMV8_DEPRECATED
arch/arm64/Kconfig config ARCH_XGENE · line 177
Quoted 10 lines
arch/arm64/Kconfig +10
-0+ bool "Emulate deprecated/obsolete ARMv8 instructions" + depends on COMPAT + help + Legacy software support may require certain instructions + that have been deprecated or obsoleted in the architecture. + + Enable this config to enable selective emulation of these + features. + + If unsure, say N
I think if unsure we should say Y. It should probably be disabled if you know for sure you are not going to have legacy applications using deprecated instructions. We could even have a "default y".
arch/arm64/Kconfig config ARCH_XGENE · line 179
Quoted 2 lines
arch/arm64/Kconfig +2
-0+ +if ARMV8_DEPRECATED
Does menuconfig automatically imply an "if"? Not sure.
Quoted 11 lines
arch/arm64/Kconfig +11
-0+ +config SWP_EMULATION + bool "Emulate SWP/SWPB instructions" + help + ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that + they are always undefined. Say Y here to enable software + emulation of these instructions for userspace using LDXR/STXR. + + In some older versions of glibc [<=2.8] SWP is used during futex + trylock() operations with the assumption that the code will not + be preempted. This invalid assumption may be more likely to fail
arch/arm64/Kconfig config ARCH_XGENE · line 200
Quoted 10 lines
arch/arm64/Kconfig +10
-0+ with SWP emulation enabled, leading to deadlock of the user + application. + + NOTE: when accessing uncached shared regions, LDXR/STXR rely + on an external transaction monitoring block called a global + monitor to maintain update atomicity. If your system does not + implement a global monitor, this option can cause programs that + perform SWP operations to uncached memory to deadlock. + + If unsure, say N
Same here, I think we should default to y.
Quoted 19 lines
arch/arm64/Kconfig +19
-0+static void update_insn_emulation_mode(struct insn_emulation *insn, + enum insn_emulation_mode prev) +{ + switch (prev) { + case INSN_UNDEF: /* Nothing to be done */ + break; + case INSN_EMULATE: + remove_emulation_hooks(insn->ops); + break; + case INSN_HW: + if (insn->ops->set_hw_mode) { + insn->ops->set_hw_mode(false); + pr_notice("Disabled %s support\n", insn->ops->name); + } + break; + } + + switch (insn->current_mode) { + case INSN_UNDEF:
arch/arm64/Kconfig config ARCH_XGENE
Quoted 10 lines
arch/arm64/Kconfig +10
-0+ break; + case INSN_EMULATE: + register_emulation_hooks(insn->ops); + break; + case INSN_HW: + if (insn->ops->set_hw_mode) { + insn->ops->set_hw_mode(true); + pr_notice("Enabled %s support\n", insn->ops->name); + } + break;
Here we should return -EINVAL all the way to the sysctl hook when !set_hw_mode. SWP doesn't have a hw mode on ARMv8, so we should let the user know. We even remove the emulation in this case falling back to undef.
Signature · 1 line
Catalin
PATCH v3 3/5 arm64: Port SWP/SWPB emulation support from arm
Quoted 61 lines · Catalin Marinas
Quoted 60 lines · Punit Agrawal
Documentation/arm64/legacy_instructions.txt new file +40
-0@@ -0,0 +1,40 @@ +The arm64 port of the Linux kernel provides infrastructure to support +emulation of instructions which have been deprecated, or obsoleted in +the architecture. The infrastructure code uses undefined instruction +hooks to support emulation. Where available it also allows turning on +the instruction execution in hardware. + +The emulation mode can be controlled by writing to sysctl nodes +(/proc/sys/abi). The following explains the different execution +behaviours and the corresponding values of the sysctl nodes - + +* Undef + Value: 0 + Generates undefined instruction abort. Default for instructions that + have been obsoleted in the architecture, e.g., SWP + +* Emulate + Value: 1 + Uses software emulation. To aid migration of software, in this mode + usage of emulated instruction is traced as well as rate limited + warnings are issued. This is the default for deprecated + instructions, .e.g., CP15 barriers + +* Hardware Execution + Value: 2 + Although marked as deprecated, some implementations may support the + enabling/disabling of hardware support for the execution of these + instructions. Using hardware execution generally provides better + performance, but at the loss of ability to gather runtime statistics + about the use of the deprecated instructions. + +The default mode depends on the status of the instruction in the +architecture. Deprecated instructions should default to emulation +while obsolete instructions must be undefined by default. + +Supported legacy instructions +----------------------------- +* SWP{B} +Node: /proc/sys/abi/swp +Status: Obsolete +Default: Undef (0)arch/arm64/Kconfig +9
-0@@ -162,6 +162,45 @@ config ARCH_XGENE help This enables support for AppliedMicro X-Gene SOC Family +comment "Processor Features" + +menuconfig ARMV8_DEPRECATED + bool "Emulate deprecated/obsolete ARMv8 instructions" + depends on COMPAT + help + Legacy software support may require certain instructions + that have been deprecated or obsoleted in the architecture. +
Quoted 8 lines
arch/arm64/Kconfig config ARCH_XGENE · line 177
Quoted 4 lines
arch/arm64/Kconfig +4
-0+ Enable this config to enable selective emulation of these + features. + + If unsure, say NI think if unsure we should say Y. It should probably be disabled if you know for sure you are not going to have legacy applications using deprecated instructions. We could even have a "default y".
I replied in another email to why this wasn't turned off by default. Let me know if you'd like to change it.
Quoted 21 lines
arch/arm64/Kconfig config ARCH_XGENE · line 179
Quoted 3 lines
arch/arm64/Kconfig +2
-0+ +if ARMV8_DEPRECATEDDoes menuconfig automatically imply an "if"? Not sure.
Quoted 15 lines
arch/arm64/Kconfig +15
-0+ +config SWP_EMULATION + bool "Emulate SWP/SWPB instructions" + help + ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that + they are always undefined. Say Y here to enable software + emulation of these instructions for userspace using LDXR/STXR. + + In some older versions of glibc [<=2.8] SWP is used during futex + trylock() operations with the assumption that the code will not + be preempted. This invalid assumption may be more likely to fail + with SWP emulation enabled, leading to deadlock of the user + application. + + NOTE: when accessing uncached shared regions, LDXR/STXR rely
Quoted 8 lines
arch/arm64/Kconfig config ARCH_XGENE · line 200
Quoted 6 lines
arch/arm64/Kconfig +6
-0+ on an external transaction monitoring block called a global + monitor to maintain update atomicity. If your system does not + implement a global monitor, this option can cause programs that + perform SWP operations to uncached memory to deadlock. + + If unsure, say NSame here, I think we should default to y.
Again, same as above.
Quoted 27 lines
Quoted 27 lines
arch/arm64/Kconfig +26
-0+static void update_insn_emulation_mode(struct insn_emulation *insn, + enum insn_emulation_mode prev) +{ + switch (prev) { + case INSN_UNDEF: /* Nothing to be done */ + break; + case INSN_EMULATE: + remove_emulation_hooks(insn->ops); + break; + case INSN_HW: + if (insn->ops->set_hw_mode) { + insn->ops->set_hw_mode(false); + pr_notice("Disabled %s support\n", insn->ops->name); + } + break; + } + + switch (insn->current_mode) { + case INSN_UNDEF: + break; + case INSN_EMULATE: + register_emulation_hooks(insn->ops); + break; + case INSN_HW: + if (insn->ops->set_hw_mode) { + insn->ops->set_hw_mode(true);
Quoted 8 lines
arch/arm64/Kconfig
Quoted 3 lines
arch/arm64/Kconfig +3
-0+ pr_notice("Enabled %s support\n", insn->ops->name); + } + break;Here we should return
-EINVALall the way to the sysctl hook when !set_hw_mode. SWP doesn't have a hw mode on ARMv8, so we should let the user know. We even remove the emulation in this case falling back to undef.
If set_hw_mode callback is not provided- which swp doesn't, then the min-max check performed when parsing the value written to sysctl will fail. So it already works as you suggest for swp - but I take your point about erroring out all the way to userspace if something doesn't succeed.
I'll audit the code to make sure all code paths behave accordingly.
Thanks for your feedback. I'll post a new version with the updates.
PATCH v3 4/5 arm64: Emulate CP15 Barrier instructions
In reply to Punit AgrawalThe CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB instructions respectively. Some implementations may provide the ability to disable the CP15 barriers by disabling the CP15BEN bit in SCTLR_EL1. If not enabled, the encodings for these instructions become undefined.
To support legacy software using these instructions, this patch register hooks to -
* emulate CP15 barriers and warn the user about their use
* toggle CP15BEN in SCTLR_EL1
--- Documentation/arm64/legacy_instructions.txt | 5 ++ arch/arm64/Kconfig | 15 ++++ arch/arm64/include/asm/insn.h | 2 + arch/arm64/kernel/armv8_deprecated.c | 124 ++++++++++++++++++++++++++++ arch/arm64/kernel/insn.c | 13 +++ 5 files changed, 159 insertions(+)
Documentation/arm64/legacy_instructions.txt +5 -0
@@ -38,3 +38,8 @@ Supported legacy instructions Node: /proc/sys/abi/swp Status: Obsolete Default: Undef (0) + +* CP15 Barriers +Node: /proc/sys/abi/cp15_barrier +Status: Deprecated +Default: Emulate (1)
arch/arm64/Kconfig +15 -0
@@ -199,6 +199,21 @@ config SWP_EMULATION If unsure, say N +config CP15_BARRIER_EMULATION + bool "Emulate CP15 Barrier instructions" + help + The CP15 barrier instructions - CP15ISB, CP15DSB, and + CP15DMB - are deprecated in ARMv8 (and ARMv7). It is + strongly recommended to use the ISB, DSB, and DMB + instructions instead. + + Say Y here to enable software emulation of these + instructions for AArch32 userspace code. When this option is + enabled, CP15 barrier usage is traced which can help + identify software that needs updating. + + If unsure, say N + endif endmenu
arch/arm64/include/asm/insn.h +2 -0
@@ -362,6 +362,8 @@ bool aarch32_insn_is_wide_instruction(u32 insn);#define A32_RT2_OFFSET 0u32 aarch32_insn_extract_reg_num (u32 insn,int offset); +u32 aarch32_insn_mcr_extract_opc2 (u32 insn); +u32 aarch32_insn_mcr_extract_crm (u32 insn);#endif /* __ASSEMBLY__ */ #endif /* __ASM_INSN_H */
arch/arm64/kernel/armv8_deprecated.c +124 -0
142 lines not on this page · raw message
arch/arm64/kernel/insn.c +13 -0
@@ -972,3 +972,16 @@ u32 aarch32_insn_extract_reg_num(u32 insn, int offset) {return (insn & (0xf << offset)) >> offset; } + +#define OPC2_MASK 0x7 +#define OPC2_OFFSET 5 +u32 aarch32_insn_mcr_extract_opc2 (u32 insn) +{ +return (insn & (OPC2_MASK <<OPC2_OFFSET )) >>OPC2_OFFSET ; +} + +#define CRM_MASK 0xf +u32 aarch32_insn_mcr_extract_crm (u32 insn) +{ +return insn &CRM_MASK ; +}
Signature · 1 line
2.1.1
Catalin Marinas
maintainerPATCH v3 4/5 arm64: Emulate CP15 Barrier instructions
Quoted 27 lines · Punit Agrawal
Documentation/arm64/legacy_instructions.txt +5
-0@@ -38,3 +38,8 @@ Supported legacy instructions Node: /proc/sys/abi/swp Status: Obsolete Default: Undef (0) + +* CP15 Barriers +Node: /proc/sys/abi/cp15_barrier +Status: Deprecated +Default: Emulate (1)arch/arm64/Kconfig +6
-0@@ -199,6 +199,21 @@ config SWP_EMULATION If unsure, say N +config CP15_BARRIER_EMULATION + bool "Emulate CP15 Barrier instructions" + help + The CP15 barrier instructions - CP15ISB, CP15DSB, and + CP15DMB - are deprecated in ARMv8 (and ARMv7). It is + strongly recommended to use the ISB, DSB, and DMB
arch/arm64/Kconfig config SWP_EMULATION · line 217
Quoted 10 lines
arch/arm64/Kconfig +9
-0+ instructions instead. + + Say Y here to enable software emulation of these + instructions for AArch32 userspace code. When this option is + enabled, CP15 barrier usage is traced which can help + identify software that needs updating. + + If unsure, say N + endif
default y (I think we had a discussion in private whether deprecated should default to y and obsolete to y or n but I don't remember the conclusion; it's worth adding it to the Documentation/ file).
Quoted 23 lines
arch/arm64/Kconfig +23
-0+#define SCTLR_EL1_CP15BEN (1 << 5) + +static inline void config_sctlr_el1(u32 clear, u32 set) +{ + u32 val; + + asm volatile("mrs %0, sctlr_el1" : "=r" (val)); + val &= ~clear; + val |= set; + asm volatile("msr sctlr_el1, %0" : : "r" (val)); +} + +static void enable_cp15_ben(void *info) +{ + config_sctlr_el1(0, SCTLR_EL1_CP15BEN); +} + +static void disable_cp15_ben(void *info) +{ + config_sctlr_el1(SCTLR_EL1_CP15BEN, 0); +} + +static int cpu_hotplug_notify(struct notifier_block *b, unsigned long action,
arch/arm64/Kconfig config SWP_EMULATION
Quoted 10 lines
arch/arm64/Kconfig +10
-0+ void *hcpu) +{ + switch (action) { + case CPU_STARTING: + enable_cp15_ben(NULL); + return NOTIFY_DONE; + } + + return NOTIFY_OK; +}
Do we need CPU_STARTING_FROZEN as well?
This code always enables the CP15 barriers in hardware but it should take into account the actual state (emulation, undef).
Signature · 1 line
Catalin
PATCH v3 4/5 arm64: Emulate CP15 Barrier instructions
Quoted 34 lines · Catalin Marinas
Quoted 33 lines · Punit Agrawal
Documentation/arm64/legacy_instructions.txt +5
-0@@ -38,3 +38,8 @@ Supported legacy instructions Node: /proc/sys/abi/swp Status: Obsolete Default: Undef (0) + +* CP15 Barriers +Node: /proc/sys/abi/cp15_barrier +Status: Deprecated +Default: Emulate (1)arch/arm64/Kconfig +12
-0@@ -199,6 +199,21 @@ config SWP_EMULATION If unsure, say N +config CP15_BARRIER_EMULATION + bool "Emulate CP15 Barrier instructions" + help + The CP15 barrier instructions - CP15ISB, CP15DSB, and + CP15DMB - are deprecated in ARMv8 (and ARMv7). It is + strongly recommended to use the ISB, DSB, and DMB + instructions instead. + + Say Y here to enable software emulation of these + instructions for AArch32 userspace code. When this option is + enabled, CP15 barrier usage is traced which can help + identify software that needs updating.
Quoted 8 lines
arch/arm64/Kconfig config SWP_EMULATION · line 217
Quoted 4 lines
arch/arm64/Kconfig +3
-0+ + If unsure, say N + endifdefault y (I think we had a discussion in private whether deprecated should default to y and obsolete to y or n but I don't remember the conclusion; it's worth adding it to the
Documentation/file).
Based on the outcome of the discussion, I've documented the runtime defaults ('undef' for obsolete and 'emulation' for deprecated instructions) in the previous patch (3/5).
As for Kconfig, the conclusion was to keep them off by default. The rationale was that they can be enabled quite easily and would form another way to communicate that certain features are deprecated and software might need updating.
Quoted 28 lines
Quoted 28 lines
arch/arm64/Kconfig +27
-0+#define SCTLR_EL1_CP15BEN (1 << 5) + +static inline void config_sctlr_el1(u32 clear, u32 set) +{ + u32 val; + + asm volatile("mrs %0, sctlr_el1" : "=r" (val)); + val &= ~clear; + val |= set; + asm volatile("msr sctlr_el1, %0" : : "r" (val)); +} + +static void enable_cp15_ben(void *info) +{ + config_sctlr_el1(0, SCTLR_EL1_CP15BEN); +} + +static void disable_cp15_ben(void *info) +{ + config_sctlr_el1(SCTLR_EL1_CP15BEN, 0); +} + +static int cpu_hotplug_notify(struct notifier_block *b, unsigned long action, + void *hcpu) +{ + switch (action) { + case CPU_STARTING:
Quoted 8 lines
arch/arm64/Kconfig
Quoted 6 lines
arch/arm64/Kconfig +6
-0+ enable_cp15_ben(NULL); + return NOTIFY_DONE; + } + + return NOTIFY_OK; +}Do we need
CPU_STARTING_FROZENas well?
Added this now.
Thinking about this, I think I want to disable this bit for CPUs being hot-unplugged otherwise we might end up with an inconsistent state across cores. I'll fix this up for the next version.
Quoted 3 lines
This code always enables the CP15 barriers in hardware but it should take into account the actual state (emulation, undef).
The actual state is taken into account in the previous patch (3/5
function: update_insn_emulation_mode) and the hotplug notifier is only installed to handle offlined CPUs when hardware execution is requested.
Catalin Marinas
maintainerPATCH v3 4/5 arm64: Emulate CP15 Barrier instructions
Quoted 44 lines · Punit Agrawal
Quoted 34 lines · Catalin Marinas
Quoted 33 lines · Punit Agrawal
Documentation/arm64/legacy_instructions.txt +5
-0@@ -38,3 +38,8 @@ Supported legacy instructions Node: /proc/sys/abi/swp Status: Obsolete Default: Undef (0) + +* CP15 Barriers +Node: /proc/sys/abi/cp15_barrier +Status: Deprecated +Default: Emulate (1)arch/arm64/Kconfig +12
-0@@ -199,6 +199,21 @@ config SWP_EMULATION If unsure, say N +config CP15_BARRIER_EMULATION + bool "Emulate CP15 Barrier instructions" + help + The CP15 barrier instructions - CP15ISB, CP15DSB, and + CP15DMB - are deprecated in ARMv8 (and ARMv7). It is + strongly recommended to use the ISB, DSB, and DMB + instructions instead. + + Say Y here to enable software emulation of these + instructions for AArch32 userspace code. When this option is + enabled, CP15 barrier usage is traced which can help + identify software that needs updating.Quoted 8 lines
arch/arm64/Kconfig config SWP_EMULATION · line 217
Quoted 4 lines
arch/arm64/Kconfig +3
-0+ + If unsure, say N + endifdefault y (I think we had a discussion in private whether deprecated should default to y and obsolete to y or n but I don't remember the conclusion; it's worth adding it to the
Documentation/file).
Quoted 8 lines
Based on the outcome of the discussion, I've documented the runtime defaults ('undef' for obsolete and 'emulation' for deprecated instructions) in the previous patch (3/5).
As for
Kconfig, the conclusion was to keep them off by default. The rationale was that they can be enabled quite easily and would form another way to communicate that certain features are deprecated and software might need updating.
Sounds fine.
Signature · 1 line
Catalin
Catalin Marinas
maintainerPATCH v3 4/5 arm64: Emulate CP15 Barrier instructions
In reply to Punit AgrawalQuoted 25 lines · Punit Agrawal
arch/arm64/kernel/armv8_deprecated.c +25
-0+static int cp15barrier_handler (struct pt_regs *regs,u32 instr) +{ +perf_sw_event (PERF_COUNT_SW_EMULATION_FAULTS ,1 , regs, regs->pc); + +switch (arm_check_condition (instr, regs->pstate)) { +case ARM_OPCODE_CONDTEST_PASS : +break ; +case ARM_OPCODE_CONDTEST_FAIL : +/* Condition failed - return to next instruction */ + goto ret; +case ARM_OPCODE_CONDTEST_UNCOND : +/* If unconditional encoding - not a barrier instruction */ +return -EFAULT ; +default : +return -EINVAL ; + } + +switch (aarch32_insn_mcr_extract_crm (instr)) { +case 10 : +/* +* dmb - mcr p15, 0, Rt, c7, c10, 5 +* dsb - mcr p15, 0, Rt, c7, c10, 4 +*/ +if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) +dmb (sy);
arch/arm64/kernel/armv8_deprecated.c static struct insn_emulation_ops swp_ops = { · line 274
Quoted 10 lines
arch/arm64/kernel/armv8_deprecated.c +10
-0+else +dsb (sy); +break ; +case 5 : +/* +* isb - mcr p15, 0, Rt, c7, c5, 4 +*/ +isb (); +break ; + }
IIRC we concluded that an isb() isn't needed here as taking an exception or returning from one would act as an instruction barrier.
Signature · 1 line
Catalin
PATCH v3 4/5 arm64: Emulate CP15 Barrier instructions
Quoted 31 lines · Catalin Marinas
Quoted 30 lines · Punit Agrawal
arch/arm64/kernel/armv8_deprecated.c +30
-0+static int cp15barrier_handler (struct pt_regs *regs,u32 instr) +{ +perf_sw_event (PERF_COUNT_SW_EMULATION_FAULTS ,1 , regs, regs->pc); + +switch (arm_check_condition (instr, regs->pstate)) { +case ARM_OPCODE_CONDTEST_PASS : +break ; +case ARM_OPCODE_CONDTEST_FAIL : +/* Condition failed - return to next instruction */ + goto ret; +case ARM_OPCODE_CONDTEST_UNCOND : +/* If unconditional encoding - not a barrier instruction */ +return -EFAULT ; +default : +return -EINVAL ; + } + +switch (aarch32_insn_mcr_extract_crm (instr)) { +case 10 : +/* +* dmb - mcr p15, 0, Rt, c7, c10, 5 +* dsb - mcr p15, 0, Rt, c7, c10, 4 +*/ +if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) +dmb (sy); +else +dsb (sy); +break ; +case 5 : +/*
Quoted 8 lines
arch/arm64/kernel/armv8_deprecated.c static struct insn_emulation_ops swp_ops = { · line 274
Quoted 5 lines
arch/arm64/kernel/armv8_deprecated.c +5
-0+* isb - mcr p15, 0, Rt, c7, c5, 4 +*/ +isb (); +break ; + }IIRC we concluded that an
isb()isn't needed here as taking an exception or returning from one would act as an instruction barrier.
I don't remember what the conclusion was - the isb was introduced to err on the side of caution. I've removed it now.
Thanks.
PATCH v3 5/5 arm64: Trace emulation of AArch32 legacy instructions
In reply to Punit AgrawalIntroduce an event to trace the usage of emulated instructions. The trace event is intended to help identify and encourage the migration of legacy software using the emulation features.
Use this event to trace usage of swp and CP15 barrier emulation.
--- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/armv8_deprecated.c | 19 ++++++++++++-- arch/arm64/kernel/trace-events-emulation.h | 40 ++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/kernel/trace-events-emulation.h
arch/arm64/kernel/Makefile +1 -0
@@ -5,6 +5,7 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) CFLAGS_efi-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +CFLAGS_armv8_deprecated.o := -I$(src) CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_insn.o = -pg
arch/arm64/kernel/armv8_deprecated.c +17 -2
@@ -15,6 +15,9 @@#include <linux/slab.h> #include <linux/sysctl.h> +#define CREATE_TRACE_POINTS +#include "trace-events-emulation.h" +#include <asm/insn.h> #include <asm/opcodes.h> #include <asm/system_misc.h>
@@ -203,6 +206,11 @@ static int swp_handler(struct pt_regs *regs, u32 instr) regs->user_regs.regs[destreg] = data; ret: +if (type ==TYPE_SWPB ) +trace_instruction_emulation ("swpb" , regs->pc); +else +trace_instruction_emulation ("swp" , regs->pc); +pr_warn_ratelimited ("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n" , current->comm, (unsigned long )current->pid, regs->pc);
@@ -260,16 +268,23 @@ static int cp15barrier_handler(struct pt_regs *regs, u32 instr)* dmb - mcr p15, 0, Rt, c7, c10, 5 * dsb - mcr p15, 0, Rt, c7, c10, 4 */ -if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) +if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) {dmb (sy); -else +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c10, 5" , regs->pc); + }else {dsb (sy); +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c10, 4" , regs->pc); + }break ;case 5 :/* * isb - mcr p15, 0, Rt, c7, c5, 4 */ isb (); +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c5, 4" , regs->pc);break ; }
arch/arm64/kernel/trace-events-emulation.h new file +40 -0
@@ -0,0 +1,40 @@ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM emulation + +#if !defined(_TRACE_EMULATION_H) || defined(TRACE_HEADER_MULTI_READ ) +#define _TRACE_EMULATION_H + +#include <linux/tracepoint.h> + +TRACE_EVENT (instruction_emulation, + + TP_PROTO(const char *instr, u64 addr), +TP_ARGS (instr, addr), + +TP_STRUCT__entry ( + __array(char, comm, TASK_COMM_LEN) + __field(pid_t, pid) + __string(instr, instr) +__field (u64, addr) + ), + +TP_fast_assign ( + memcpy(__entry->comm, current->comm, TASK_COMM_LEN); + __entry->pid = current->pid; + __assign_str(instr, instr); + __entry->addr = addr; + ), + +TP_printk ("instr=%s comm=%s pid=%d addr=0x%llx" ,__get_str (instr), + __entry->comm, __entry->pid, __entry->addr) +); + +#endif /* _TRACE_EMULATION_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . + +#define TRACE_INCLUDE_FILE trace-events-emulation +#include <trace/define_trace.h>
Signature · 1 line
2.1.1
Catalin Marinas
maintainerPATCH v3 5/5 arm64: Trace emulation of AArch32 legacy instructions
Quoted 20 lines · Punit Agrawal
Introduce an event to trace the usage of emulated instructions. The trace event is intended to help identify and encourage the migration of legacy software using the emulation features.
Use this event to trace usage of swp and CP15 barrier emulation.
Cc Steven Rostedt <[email protected]>Signed-off-by Punit Agrawal <[email protected]>--- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/armv8_deprecated.c | 19 ++++++++++++-- arch/arm64/kernel/trace-events-emulation.h | 40 ++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/kernel/trace-events-emulation.harch/arm64/kernel/Makefile +0
-0
arch/arm64/kernel/Makefile line 8
Quoted 4 lines
arch/arm64/kernel/Makefile +1
-0@@ -5,6 +5,7 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) CFLAGS_efi-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +CFLAGS_armv8_deprecated.o := -I$(src)
Why do you need this?
arch/arm64/kernel/armv8_deprecated.c line 19
Quoted 12 lines
arch/arm64/kernel/Makefile +0
-0CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_insn.o = -pgarch/arm64/kernel/armv8_deprecated.c +2
-0@@ -15,6 +15,9 @@#include <linux/slab.h> #include <linux/sysctl.h> +#define CREATE_TRACE_POINTS +#include "trace-events-emulation.h"
Using double quotes should be fine for the current directory.
Signature · 1 line
Catalin
PATCH v3 5/5 arm64: Trace emulation of AArch32 legacy instructions
Quoted 16 lines · On Wed, 5 Nov 2014 14:46:19 +0000 Catalin Marinas <[email protected]>…
Quoted 15 lines · Punit Agrawal
Introduce an event to trace the usage of emulated instructions. The trace event is intended to help identify and encourage the migration of legacy software using the emulation features.
Use this event to trace usage of swp and CP15 barrier emulation.
Cc Steven Rostedt <[email protected]>Signed-off-by Punit Agrawal <[email protected]>--- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/armv8_deprecated.c | 19 ++++++++++++-- arch/arm64/kernel/trace-events-emulation.h | 40 ++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/kernel/trace-events-emulation.h
Quoted 11 lines
arch/arm64/kernel/Makefile line 8
Quoted 9 lines
arch/arm64/kernel/Makefile +1
-0@@ -5,6 +5,7 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) CFLAGS_efi-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +CFLAGS_armv8_deprecated.o := -I$(src)Why do you need this?
It has to do with the TRACE_EVENT magic.
Read samples/trace_events/Makefile
Quoted 11 lines
Quoted 11 lines
arch/arm64/kernel/Makefile +0
-0CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_insn.o = -pgarch/arm64/kernel/armv8_deprecated.c +0
-0@@ -15,6 +15,9 @@#include <linux/slab.h> #include <linux/sysctl.h>
Quoted 5 lines
arch/arm64/kernel/armv8_deprecated.c line 19
Quoted 2 lines
arch/arm64/kernel/armv8_deprecated.c +2
-0+#define CREATE_TRACE_POINTS +#include "trace-events-emulation.h" Using double quotes should be fine for the current directory.
No it is not enough. It not only gets included by this file, but also gets included by include/trace/ftrace.h with:
#include TRACE_INCLUDE(TRACE_INCLUDE_FILE)
Without that -I$(src) added, this include will fail.
-- Steve
Catalin Marinas
maintainerPATCH v3 5/5 arm64: Trace emulation of AArch32 legacy instructions
Quoted 34 lines · Steven Rostedt
Quoted 10 lines · On Wed, 5 Nov 2014 14:46:19 +0000 Catalin Marinas <[email protected]>…
arch/arm64/kernel/Makefile line 8
Quoted 7 lines · Punit Agrawal
arch/arm64/kernel/Makefile +1
-0@@ -5,6 +5,7 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) CFLAGS_efi-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +CFLAGS_armv8_deprecated.o := -I$(src)Why do you need this?
It has to do with the
TRACE_EVENTmagic.Read
samples/trace_events/MakefileQuoted 11 lines
Quoted 11 lines
arch/arm64/kernel/Makefile +0
-0CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_insn.o = -pgarch/arm64/kernel/armv8_deprecated.c +0
-0@@ -15,6 +15,9 @@#include <linux/slab.h> #include <linux/sysctl.h> Quoted 4 lines
arch/arm64/kernel/armv8_deprecated.c line 19
Quoted 2 lines
arch/arm64/kernel/armv8_deprecated.c +2
-0+#define CREATE_TRACE_POINTS +#include "trace-events-emulation.h" Using double quotes should be fine for the current directory.
Quoted 6 lines
No it is not enough. It not only gets included by this file, but also gets included by
include/trace/ftrace.hwith:#include
TRACE_INCLUDE(TRACE_INCLUDE_FILE)Without that -I$(src) added, this include will fail.
Ah, thanks for clarification.
Signature · 1 line
Catalin
PATCH v3 5/5 arm64: Trace emulation of AArch32 legacy instructions
In reply to Punit AgrawalQuoted 66 lines · Punit Agrawal
Introduce an event to trace the usage of emulated instructions. The trace event is intended to help identify and encourage the migration of legacy software using the emulation features.
Use this event to trace usage of swp and CP15 barrier emulation.
Cc Steven Rostedt <[email protected]>Signed-off-by Punit Agrawal <[email protected]>--- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/armv8_deprecated.c | 19 ++++++++++++-- arch/arm64/kernel/trace-events-emulation.h | 40 ++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/kernel/trace-events-emulation.harch/arm64/kernel/Makefile +1
-0@@ -5,6 +5,7 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) CFLAGS_efi-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +CFLAGS_armv8_deprecated.o := -I$(src) CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_insn.o = -pgarch/arm64/kernel/armv8_deprecated.c +13
-2@@ -15,6 +15,9 @@#include <linux/slab.h> #include <linux/sysctl.h> +#define CREATE_TRACE_POINTS +#include "trace-events-emulation.h" +#include <asm/insn.h> #include <asm/opcodes.h> #include <asm/system_misc.h> @@ -203,6 +206,11 @@ static int swp_handler(struct pt_regs *regs, u32 instr) regs->user_regs.regs[destreg] = data; ret: +if (type ==TYPE_SWPB ) +trace_instruction_emulation ("swpb" , regs->pc); +else +trace_instruction_emulation ("swp" , regs->pc); +pr_warn_ratelimited ("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n" , current->comm, (unsigned long )current->pid, regs->pc);@@ -260,16 +268,23 @@ static int cp15barrier_handler(struct pt_regs *regs, u32 instr)* dmb - mcr p15, 0, Rt, c7, c10, 5 * dsb - mcr p15, 0, Rt, c7, c10, 4 */ -if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) +if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) {dmb (sy); -else +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c10, 5" , regs->pc); + }else {dsb (sy); + trace_instruction_emulation(
arch/arm64/kernel/armv8_deprecated.c static int cp15barrier_handler(struct pt_regs *regs, u32 instr) · line 287
Quoted 10 lines
arch/arm64/kernel/armv8_deprecated.c +4
-0+ "mcr p15, 0, Rt, c7, c10, 4", regs->pc); + }break ;case 5 :/* * isb - mcr p15, 0, Rt, c7, c5, 4 */ isb (); +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c5, 4" , regs->pc);
Any chance you can put the barrier name in here too please? Maybe as an asm comment, e.g.:
"mcr p15, 0, Rt, c7, c5, 4 ; isb"
Will
PATCH v3 5/5 arm64: Trace emulation of AArch32 legacy instructions
Hi Will,
Thanks for taking a look.
Quoted 10 lines · Will Deacon
Quoted 9 lines · Punit Agrawal
Introduce an event to trace the usage of emulated instructions. The trace event is intended to help identify and encourage the migration of legacy software using the emulation features.
Use this event to trace usage of swp and CP15 barrier emulation.
Cc Steven Rostedt <[email protected]>Signed-off-by Punit Agrawal <[email protected]>---
[...]
Quoted 27 lines
Quoted 13 lines
arch/arm64/kernel/armv8_deprecated.c +5
-2@@ -260,16 +268,23 @@ static int cp15barrier_handler(struct pt_regs *regs, u32 instr)* dmb - mcr p15, 0, Rt, c7, c10, 5 * dsb - mcr p15, 0, Rt, c7, c10, 4 */ -if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) +if (aarch32_insn_mcr_extract_opc2 (instr) ==5 ) {dmb (sy); -else +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c10, 5" , regs->pc); + }else {dsb (sy); + trace_instruction_emulation(arch/arm64/kernel/armv8_deprecated.c static int cp15barrier_handler(struct pt_regs *regs, u32 instr) · line 287
Quoted 10 lines
arch/arm64/kernel/armv8_deprecated.c +4
-0+ "mcr p15, 0, Rt, c7, c10, 4", regs->pc); + }break ;case 5 :/* * isb - mcr p15, 0, Rt, c7, c5, 4 */ isb (); +trace_instruction_emulation ( +"mcr p15, 0, Rt, c7, c5, 4" , regs->pc);Any chance you can put the barrier name in here too please? Maybe as an asm comment, e.g.:
Quoted 1 line
"mcr p15, 0, Rt, c7, c5, 4 ; isb"
Good point. I've added the barrier names as assembler comments.
Thanks.
Quoted 7 lines
Will
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