Add full DDR init for Marvell Armada-XP MV78xx0 (AXP)

This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the AXP boot image. Not linked with the main U-Boot. With this code addition and the also included SERDES / PHY setup code, the Armada-XP support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Hopefully other MVEBU SoC's will follow here.

Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and on a custom fixed DDR configuration board (maxbcm with MV78460).

Thanks,
Stefan

Stefan Roese (9):
arm: mvebu: drivers/ddr: Add DDR3 driver with training code from
Marvell bin_hdr
arm: mvebu: Add Serdes PHY config code
arm: armada-xp: Add SPL support used to include the DDR training code scripts/Makefile.spl: Add MVEBU DDR code to SPL
tools: kwbimage: Support u-boot.img padding to
CONFIG_SYS_SPI_U_BOOT_OFFS
Makefile: Add another kwb build target used on Marvell Armada-XP (AXP)
arm: db-mv784mp-gp: Enable SPL to include DDR training code into
U-Boot
arm: maxbcm: Enable SPL to include DDR training code into U-Boot
arm: armada-xp: Change built target to include the SPL binary as
bin_hdr

 Makefile                                           |    6 +
 arch/arm/Kconfig                                   |    2 +
 arch/arm/cpu/armv7/armada-xp/Makefile              |    2 +
 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S        |   62 +
 arch/arm/cpu/armv7/armada-xp/spl.c                 |   38 +
 arch/arm/include/asm/arch-armada-xp/config.h       |    4 +
 arch/arm/include/asm/arch-armada-xp/cpu.h          |   16 +
 arch/arm/mvebu-common/Makefile                     |    2 +
 arch/arm/mvebu-common/serdes/Makefile              |    6 +
 arch/arm/mvebu-common/serdes/board_env_spec.h      |  262 ++++
 arch/arm/mvebu-common/serdes/high_speed_env_lib.c  | 1572 +++++++++++++++++++
 arch/arm/mvebu-common/serdes/high_speed_env_spec.c |  185 +++
 arch/arm/mvebu-common/serdes/high_speed_env_spec.h |   87 ++
 arch/arm/mvebu-common/u-boot-spl.lds               |   57 +
 board/Marvell/db-mv784mp-gp/kwbimage.cfg           |    2 +-
 board/maxbcm/kwbimage.cfg                          |    2 +-
 board/maxbcm/maxbcm.c                              |   83 +-
 configs/db-mv784mp-gp_defconfig                    |    5 +-
 configs/maxbcm_defconfig                           |    5 +-
 drivers/ddr/mvebu/Makefile                         |   14 +
 drivers/ddr/mvebu/ddr3_axp.h                       |  510 +++++++
 drivers/ddr/mvebu/ddr3_axp_config.h                |  146 ++
 drivers/ddr/mvebu/ddr3_axp_mc_static.h             |  284 ++++
 drivers/ddr/mvebu/ddr3_axp_training_static.h       |  770 ++++++++++
 drivers/ddr/mvebu/ddr3_axp_vars.h                  |  226 +++
 drivers/ddr/mvebu/ddr3_dfs.c                       | 1552 +++++++++++++++++++
 drivers/ddr/mvebu/ddr3_dqs.c                       | 1374 +++++++++++++++++
 drivers/ddr/mvebu/ddr3_hw_training.c               | 1115 ++++++++++++++
 drivers/ddr/mvebu/ddr3_hw_training.h               |  392 +++++
 drivers/ddr/mvebu/ddr3_init.c                      | 1219 +++++++++++++++
 drivers/ddr/mvebu/ddr3_init.h                      |  143 ++
 drivers/ddr/mvebu/ddr3_patterns_64bit.h            |  924 ++++++++++++
 drivers/ddr/mvebu/ddr3_pbs.c                       | 1592 ++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_read_leveling.c             | 1214 +++++++++++++++
 drivers/ddr/mvebu/ddr3_sdram.c                     |  669 ++++++++
 drivers/ddr/mvebu/ddr3_spd.c                       | 1300 ++++++++++++++++
 drivers/ddr/mvebu/ddr3_write_leveling.c            | 1366 +++++++++++++++++
 drivers/ddr/mvebu/xor.c                            |  436 ++++++
 drivers/ddr/mvebu/xor.h                            |   70 +
 drivers/ddr/mvebu/xor_regs.h                       |  103 ++
 include/configs/db-mv784mp-gp.h                    |   49 +
 include/configs/maxbcm.h                           |   47 +
 scripts/Makefile.spl                               |    3 +
 tools/kwbimage.c                                   |   11 +
 44 files changed, 17919 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
 create mode 100644 arch/arm/cpu/armv7/armada-xp/spl.c
 create mode 100644 arch/arm/mvebu-common/serdes/Makefile
 create mode 100644 arch/arm/mvebu-common/serdes/board_env_spec.h
 create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_lib.c
 create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.c
 create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.h
 create mode 100644 arch/arm/mvebu-common/u-boot-spl.lds
 create mode 100644 drivers/ddr/mvebu/Makefile
 create mode 100644 drivers/ddr/mvebu/ddr3_axp.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_config.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_mc_static.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_training_static.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_vars.h
 create mode 100644 drivers/ddr/mvebu/ddr3_dfs.c
 create mode 100644 drivers/ddr/mvebu/ddr3_dqs.c
 create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.c
 create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.h
 create mode 100644 drivers/ddr/mvebu/ddr3_init.c
 create mode 100644 drivers/ddr/mvebu/ddr3_init.h
 create mode 100644 drivers/ddr/mvebu/ddr3_patterns_64bit.h
 create mode 100644 drivers/ddr/mvebu/ddr3_pbs.c
 create mode 100644 drivers/ddr/mvebu/ddr3_read_leveling.c
 create mode 100644 drivers/ddr/mvebu/ddr3_sdram.c
 create mode 100644 drivers/ddr/mvebu/ddr3_spd.c
 create mode 100644 drivers/ddr/mvebu/ddr3_write_leveling.c
 create mode 100644 drivers/ddr/mvebu/xor.c
 create mode 100644 drivers/ddr/mvebu/xor.h
 create mode 100644 drivers/ddr/mvebu/xor_regs.h

2.1.2

This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the AXP boot image. Not linked with the main U-Boot. With this code addition and the following serdes/PHY setup code, the Armada-XP support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Hopefully other MVEBU SoC's will follow here.

Support for some SoC's has been removed in this version. This is:

MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its not really planned to support this in mainline. So lets remove it to make the code clearer and increase the readability.

MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused. And its partial and not sufficient for this device in this stage. So lets remove it to make the code clearer and increase the readability.

MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its not really planned to support this in mainline. So lets remove it to make the code clearer and increase the readability.

MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.

Remove support for Z1 & A0 AXP revisions (steppings). The current stepping is B0 and this is the only one that is actively supported in this code version.

Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and on a custom fixed DDR configuration board (maxbcm).

Note:
This code has undergone many hours of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. This might be some task to tackly later on.

---

 drivers/ddr/mvebu/Makefile                   |   14 +
 drivers/ddr/mvebu/ddr3_axp.h                 |  510 +++++++++
 drivers/ddr/mvebu/ddr3_axp_config.h          |  146 +++
 drivers/ddr/mvebu/ddr3_axp_mc_static.h       |  284 +++++
 drivers/ddr/mvebu/ddr3_axp_training_static.h |  770 +++++++++++++
 drivers/ddr/mvebu/ddr3_axp_vars.h            |  226 ++++
 drivers/ddr/mvebu/ddr3_dfs.c                 | 1552 +++++++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_dqs.c                 | 1374 ++++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_hw_training.c         | 1115 ++++++++++++++++++
 drivers/ddr/mvebu/ddr3_hw_training.h         |  392 +++++++
 drivers/ddr/mvebu/ddr3_init.c                | 1219 ++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_init.h                |  143 +++
 drivers/ddr/mvebu/ddr3_patterns_64bit.h      |  924 +++++++++++++++
 drivers/ddr/mvebu/ddr3_pbs.c                 | 1592 ++++++++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_read_leveling.c       | 1214 ++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_sdram.c               |  669 +++++++++++
 drivers/ddr/mvebu/ddr3_spd.c                 | 1300 +++++++++++++++++++++
 drivers/ddr/mvebu/ddr3_write_leveling.c      | 1366 ++++++++++++++++++++++
 drivers/ddr/mvebu/xor.c                      |  436 +++++++
 drivers/ddr/mvebu/xor.h                      |   70 ++
 drivers/ddr/mvebu/xor_regs.h                 |  103 ++
 21 files changed, 15419 insertions(+)
 create mode 100644 drivers/ddr/mvebu/Makefile
 create mode 100644 drivers/ddr/mvebu/ddr3_axp.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_config.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_mc_static.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_training_static.h
 create mode 100644 drivers/ddr/mvebu/ddr3_axp_vars.h
 create mode 100644 drivers/ddr/mvebu/ddr3_dfs.c
 create mode 100644 drivers/ddr/mvebu/ddr3_dqs.c
 create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.c
 create mode 100644 drivers/ddr/mvebu/ddr3_hw_training.h
 create mode 100644 drivers/ddr/mvebu/ddr3_init.c
 create mode 100644 drivers/ddr/mvebu/ddr3_init.h
 create mode 100644 drivers/ddr/mvebu/ddr3_patterns_64bit.h
 create mode 100644 drivers/ddr/mvebu/ddr3_pbs.c
 create mode 100644 drivers/ddr/mvebu/ddr3_read_leveling.c
 create mode 100644 drivers/ddr/mvebu/ddr3_sdram.c
 create mode 100644 drivers/ddr/mvebu/ddr3_spd.c
 create mode 100644 drivers/ddr/mvebu/ddr3_write_leveling.c
 create mode 100644 drivers/ddr/mvebu/xor.c
 create mode 100644 drivers/ddr/mvebu/xor.h
 create mode 100644 drivers/ddr/mvebu/xor_regs.h

new file mode 100644
index 0000000..50a69ea
@@ -0,0 +1,14 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += ddr3_dfs.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_dqs.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_hw_training.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_pbs.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_read_leveling.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_sdram.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_spd.o
+obj-$(CONFIG_SPL_BUILD) += ddr3_write_leveling.o
+obj-$(CONFIG_SPL_BUILD) += xor.o

2.1.2

Part of the diff is not shown here. View the raw message.

This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly.

---

 arch/arm/mvebu-common/Makefile                     |    2 +
 arch/arm/mvebu-common/serdes/Makefile              |    6 +
 arch/arm/mvebu-common/serdes/board_env_spec.h      |  262 ++++
 arch/arm/mvebu-common/serdes/high_speed_env_lib.c  | 1572 ++++++++++++++++++++
 arch/arm/mvebu-common/serdes/high_speed_env_spec.c |  185 +++
 arch/arm/mvebu-common/serdes/high_speed_env_spec.h |   87 ++
 6 files changed, 2114 insertions(+)
 create mode 100644 arch/arm/mvebu-common/serdes/Makefile
 create mode 100644 arch/arm/mvebu-common/serdes/board_env_spec.h
 create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_lib.c
 create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.c
 create mode 100644 arch/arm/mvebu-common/serdes/high_speed_env_spec.h

index 9dcab69..de243fe 100644
@@ -10,3 +10,5 @@ obj-y	= dram.o
 obj-y	+= gpio.o
 obj-$(CONFIG_ARMADA_XP) += mbus.o
 obj-y	+= timer.o
+
+obj-y	+= serdes/

new file mode 100644
index 0000000..a380fee
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD)	= high_speed_env_lib.o
+obj-$(CONFIG_SPL_BUILD)	+= high_speed_env_spec.o

2.1.2

This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot.

---

 arch/arm/cpu/armv7/armada-xp/Makefile       |  2 +
 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S | 62 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/armada-xp/spl.c          | 38 ++++++++++++++++++
 arch/arm/include/asm/arch-armada-xp/cpu.h   | 13 ++++++
 arch/arm/mvebu-common/u-boot-spl.lds        | 57 ++++++++++++++++++++++++++
 scripts/Makefile.spl                        |  2 +
 6 files changed, 174 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S
 create mode 100644 arch/arm/cpu/armv7/armada-xp/spl.c
 create mode 100644 arch/arm/mvebu-common/u-boot-spl.lds

index 885dcee..737159b 100644
@@ -5,3 +5,5 @@
 #
 
 obj-y	= cpu.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o

new file mode 100644
index 0000000..402e520
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+	/* Right now only booting via SPI NOR flash is supported */
+	return BOOT_DEVICE_SPI;
+}
+
+void board_init_f(ulong dummy)
+{
+	/* Set global data pointer */
+	gd = &gdata;
+
+	/* Linux expects the internal registers to be at 0xf1000000 */
+	arch_cpu_init();
+
+	preloader_console_init();
+
+	/* First init the serdes PHY's */
+	serdes_phy_config();
+
+	/* Setup DDR */
+	ddr3_init();
+
+	board_init_r(NULL, 0);
+}

index 6b60c21..45fb1ff 100644
@@ -103,5 +103,18 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
+
+/*
+ * Highspeed SERDES PHY config init, ported from bin_hdr
+ * to mainline U-Boot
+ */
+int serdes_phy_config(void);
+
+/*
+ * DDR3 init / training code ported from Marvell bin_hdr. Now
+ * available in mainline U-Boot in:
+ * drivers/ddr/mvebu/
+ */
+int ddr3_init(void);
 #endif /* __ASSEMBLY__ */
 #endif /* _ARMADA_XP_CPU_H */

index 7afe437..d11b2de 100644
@@ -100,6 +100,8 @@ ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35
 libs-y += arch/$(ARCH)/imx-common/
 endif
 
+libs-$(CONFIG_ARMADA_XP) += arch/$(ARCH)/mvebu-common/
+
 libs-$(CONFIG_ARM) += arch/arm/cpu/
 libs-$(CONFIG_PPC) += arch/powerpc/cpu/
 

2.1.2

---

 scripts/Makefile.spl | 1 +
 1 file changed, 1 insertion(+)

index d11b2de..e11e96d 100644
@@ -101,6 +101,7 @@ libs-y += arch/$(ARCH)/imx-common/
 endif
 
 libs-$(CONFIG_ARMADA_XP) += arch/$(ARCH)/mvebu-common/
+libs-$(CONFIG_SYS_MVEBU_DDR) += drivers/ddr/mvebu/
 
 libs-$(CONFIG_ARM) += arch/arm/cpu/
 libs-$(CONFIG_PPC) += arch/powerpc/cpu/

2.1.2

This is used on the AXP boards, to pad u-boot.img to the desired offset in SPI flash (only this boot target supported right now). This offset is used by the SPL then to load u-boot.img into SDRAM and execute it there.

---

 tools/kwbimage.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

index 1120e9b..9f37a36 100644
@@ -15,6 +15,7 @@
 #include <image.h>
 #include <stdint.h>
 #include "kwbimage.h"
+#include <config.h>
 
 #define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
 

@@ -845,6 +846,16 @@ static int kwbimage_generate(struct image_tool_params *params,
 			sizeof(struct ext_hdr_v0);
 	} else {
 		alloc_len = image_headersz_v1(params, NULL);
+#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
+		if (alloc_len > CONFIG_SYS_SPI_U_BOOT_OFFS) {
+			fprintf(stderr, "Error: Image header (incl. SPL image) too big!\n");
+			fprintf(stderr, "header=0x%x CONFIG_SYS_SPI_U_BOOT_OFFS=0x%x!\n",
+				alloc_len, CONFIG_SYS_SPI_U_BOOT_OFFS);
+			fprintf(stderr, "Increase CONFIG_SYS_SPI_U_BOOT_OFFS!\n");
+		} else {
+			alloc_len = CONFIG_SYS_SPI_U_BOOT_OFFS;
+		}
+#endif
 	}
 
 	hdr = malloc(alloc_len);

2.1.2

This build target now includes the SPL binary as the bin_hdr into the kwb image. Its used on the AXP port with the mainlined DDR training code.

---

 Makefile | 6 ++++++
 1 file changed, 6 insertions(+)

index 26dacee..4a3351d 100644
@@ -852,12 +852,18 @@ MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
 MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
 	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
 
+MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
+	-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
+
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
 	$(call if_changed,mkimage)
 
+u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
+	$(call if_changed,mkimage)
+
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
 
 u-boot-dtb.img: u-boot-dtb.bin FORCE

2.1.2

This patch adds SPL support to the db-mv784mp-gp eval board.

---

 arch/arm/Kconfig                         |  1 +
 board/Marvell/db-mv784mp-gp/kwbimage.cfg |  2 +-
 configs/db-mv784mp-gp_defconfig          |  5 ++--
 include/configs/db-mv784mp-gp.h          | 49 ++++++++++++++++++++++++++++++++
 4 files changed, 54 insertions(+), 3 deletions(-)

index 3415927..c757f30 100644
@@ -143,6 +143,7 @@ config KIRKWOOD
 
 config TARGET_DB_MV784MP_GP
 	bool "Support db-mv784mp-gp"
+	select SUPPORT_SPL
 
 config TARGET_MAXBCM
 	bool "Support maxbcm"

index d7ef407..cc05792 100644
@@ -9,4 +9,4 @@ VERSION		1
 BOOT_FROM	spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068
+BINARY spl/u-boot-spl.bin 0000005b 00000068

index 7aa216c..a7f13e2 100644
@@ -1,2 +1,3 @@
-CONFIG_ARM=y
-CONFIG_TARGET_DB_MV784MP_GP=y
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_DB_MV784MP_GP=y

2.1.2

This patch adds SPL support to the maxbcm MV78460 based board. Including the fixed DDR configuratrion needed for the DDR training code. And the the serdes PHY init code.

---

 arch/arm/Kconfig                          |  1 +
 arch/arm/include/asm/arch-armada-xp/cpu.h |  3 ++
 board/maxbcm/kwbimage.cfg                 |  2 +-
 board/maxbcm/maxbcm.c                     | 83 ++++++++++++++++++++++++++++++-
 configs/maxbcm_defconfig                  |  5 +-
 include/configs/maxbcm.h                  | 47 +++++++++++++++++
 6 files changed, 136 insertions(+), 5 deletions(-)

index c757f30..047d7a0 100644
@@ -147,6 +147,7 @@ config TARGET_DB_MV784MP_GP
 
 config TARGET_MAXBCM
 	bool "Support maxbcm"
+	select SUPPORT_SPL
 
 config TARGET_DEVKIT3250
 	bool "Support devkit3250"

index 45fb1ff..4f5ff96 100644
@@ -96,6 +96,9 @@ struct kwgpio_registers {
 	u32 irq_level;
 };
 
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
 /*
  * functions
  */

index 5a3bc67..cc05792 100644
@@ -9,4 +9,4 @@ VERSION		1
 BOOT_FROM	spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY board/maxbcm/binary.0 0000005b 00000068
+BINARY spl/u-boot-spl.bin 0000005b 00000068

index 4bcffd8..219586a 100644
@@ -1,2 +1,3 @@
-CONFIG_ARM=y
-CONFIG_TARGET_MAXBCM=y
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_MAXBCM=y

2.1.2

---

 arch/arm/include/asm/arch-armada-xp/config.h | 4 ++++
 1 file changed, 4 insertions(+)

index 00ee775..f9fd424 100644
@@ -31,7 +31,11 @@
 #endif /* CONFIG_SYS_KWD_CONFIG */
 
 /* Add target to build it automatically upon "make" */
+#ifdef CONFIG_SPL
+#define CONFIG_BUILD_TARGET	"u-boot-spl.kwb"
+#else
 #define CONFIG_BUILD_TARGET	"u-boot.kwb"
+#endif
 
 /* end of 16M scrubbed by training in bootrom */
 #define CONFIG_SYS_INIT_SP_ADDR		0x00FF0000

2.1.2

Hi Prafulla,

Prafulla, how should we continue with this patch-set? Do you have any comments on it? If you are okay with it, do you plan to pull it via your repository? Or should I pull it via some branch in one of my repositories?

Thanks,
Stefan

Hi Prafulla,

Any updates on this? Any comments on the patches? Should I pull them?

Thanks,
Stefan