drm/i915: don't try using training pattern 3 on pre-haswell
Subsystems (2)
Dave Airlie
maintainerPATCH 1/1 drm/i915: don't try using training pattern 3 on pre-haswell
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_dp.c +3 -1
@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) { +struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev)) training_pattern =DP_TRAINING_PATTERN_3 ;/* channel equalization */
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1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 7 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>
This regression has been introduced in
commit 06ea66b6bb445043dc25a9626254d5c130093199
Author: Todd Previte <[email protected]> Date: Mon Jan 20 10:19:39 2014 -0700
drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable devices
Jani, can you please pick this one up?
-Daniel
Quoted 32 lines
--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +3
-1@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) { +struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev)) training_pattern =DP_TRAINING_PATTERN_3 ;/* channel equalization */ Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/dri-devel
Quoted 19 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +0
-0@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) {
drivers/gpu/drm/i915/intel_dp.c intel_dp_start_link_train(struct intel_dp *intel_dp) · line 3558
Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +3
-1+struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev))
CHV has pattern 3.
Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +0
-0training_pattern =DP_TRAINING_PATTERN_3 ;/* channel equalization */ Signature · 6 lines
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Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 27 lines · Ville Syrjälä
Quoted 26 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +2
-0@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) { +struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;
Quoted 5 lines
drivers/gpu/drm/i915/intel_dp.c intel_dp_start_link_train(struct intel_dp *intel_dp) · line 3558
Quoted 3 lines
drivers/gpu/drm/i915/intel_dp.c +1
-1/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev))CHV has pattern 3.
Also what's that '!' doing there?
Quoted 19 lines
Quoted 11 lines
drivers/gpu/drm/i915/intel_dp.c +0
-0training_pattern =DP_TRAINING_PATTERN_3 ;/* channel equalization */ Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfxSignature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Ville Syrjälä Intel OTC _______________________________________________ dri-devel mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/dri-devel
Jani Nikula
maintainerQuoted 27 lines · Ville Syrjälä
Quoted 26 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +2
-0@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) { +struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;
Quoted 5 lines
drivers/gpu/drm/i915/intel_dp.c intel_dp_start_link_train(struct intel_dp *intel_dp) · line 3558
Quoted 3 lines
drivers/gpu/drm/i915/intel_dp.c +1
-1/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev))CHV has pattern 3.
Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We should abstract the check from intel_dp_max_link_bw.
Jani.
Quoted 19 lines
Quoted 11 lines
drivers/gpu/drm/i915/intel_dp.c +0
-0training_pattern =DP_TRAINING_PATTERN_3 ;/* channel equalization */ Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfxSignature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ dri-devel mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/dri-devel
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 28 lines · Jani Nikula
Quoted 27 lines · Ville Syrjälä
Quoted 26 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +2
-0@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) { +struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;
Quoted 8 lines
Quoted 5 lines
drivers/gpu/drm/i915/intel_dp.c intel_dp_start_link_train(struct intel_dp *intel_dp) · line 3558
Quoted 3 lines
drivers/gpu/drm/i915/intel_dp.c +1
-1/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev))CHV has pattern 3.
Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We should abstract the check from
intel_dp_max_link_bw.
Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
Quoted 26 lines
Jani.
Quoted 19 lines
Quoted 11 lines
drivers/gpu/drm/i915/intel_dp.c +0
-0training_pattern =DP_TRAINING_PATTERN_3 ;/* channel equalization */ Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfxSignature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ dri-devel mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/dri-develSignature · 1 line
Jani Nikula, Intel Open Source Technology Center
Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ dri-devel mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/dri-devel
Jani Nikula
maintainerQuoted 35 lines · Ville Syrjälä
Quoted 34 lines · Jani Nikula
Quoted 32 lines · Ville Syrjälä
Quoted 19 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +0
-0@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) {drivers/gpu/drm/i915/intel_dp.c intel_dp_start_link_train(struct intel_dp *intel_dp) · line 3558
Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +3
-1+struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev))CHV has pattern 3.
Quoted 4 lines
Quoted 2 lines
Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We should abstract the check from
intel_dp_max_link_bw.Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
How about [1] instead? I forgot --in-reply-to, sorry.
BR,
Jani.
[1] http://mid.gmane.org/[email protected]
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Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 41 lines · On Wed, 29 Oct 2014 11:07:32 +0200 Jani Nikula <[email protected]>…
Quoted 35 lines · Ville Syrjälä
Quoted 34 lines · Jani Nikula
Quoted 32 lines · Ville Syrjälä
Quoted 19 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Ivybridge + 30" monitor prints a drm error on every modeset, since IVB doesn't support DP3 we should even bother trying to use it.
Reviewed-by Daniel Vetter <[email protected]> (on irc)Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/i915/intel_dp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)drivers/gpu/drm/i915/intel_dp.c +0
-0@@ -3547,13 +3547,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)void intel_dp_complete_link_train (struct intel_dp *intel_dp) {drivers/gpu/drm/i915/intel_dp.c intel_dp_start_link_train(struct intel_dp *intel_dp) · line 3558
Quoted 10 lines
drivers/gpu/drm/i915/intel_dp.c +3
-1+struct drm_encoder *encoder = &dp_to_dig_port (intel_dp)->base.base; +struct drm_device *dev = encoder->dev;bool channel_eq = false;int tries, cr_tries;uint32_t DP = intel_dp->DP;uint32_t training_pattern =DP_TRAINING_PATTERN_2 ;/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ -if (intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) +if ((intel_dp->link_bw ==DP_LINK_BW_5_4 || intel_dp->use_tps3) && !HAS_DDI (dev))CHV has pattern 3.
Quoted 4 lines
Quoted 2 lines
Is "supports tps3" the same set of platforms as "supports 5.4 Gbps"? We should abstract the check from
intel_dp_max_link_bw.Not quite. HSW-ULX supports pattern 3 even though it doesn't do 5.4 Gbps.
Quoted 7 lines
How about [1] instead? I forgot --in-reply-to, sorry.
BR,
Jani.
Looks like we need something like that at least, assuming we're not hitting the link_bw == DP_LINK_BW_5_4 case.
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Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx