arm, at91, spl: add spl support for the taurus and corvus boards

PATCH Superseded Heiko Schocher 4 participants 23 messages Oct 30, 2014 – Oct 31, 2014

Subsystems (5)

Arm (32-bit) Memory technology devices (MTD) SPI Arm/Microchip (AT91) SoC support +1 more subsystems

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Heiko Schocher

author

2014-10-30 08:14 UTC #0 lore raw

v2 cover arm, at91, spl: add spl support for the taurus and corvus boards

This patchset add SPL support for the AT91SAM9G20 based taurus board, and the AT91SAM9M10G45 based corvus board from siemens, and replaces the at91bootstrap code.

The boot.bin which replaces the at91bootstrap image can created with mkimage:

./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin

For other SoC this step is done in one step ... should we add this also for AT91 based boards?

For example add a "u-boot.at91" target in the Makefile?

This patchset is based on the common updates for the taurus and corvus board:

Patchwork [U-Boot] arm, at91: add generic board support for the taurus and corvus board
http://patchwork.ozlabs.org/patch/395398/
(now in mainline)

Patchwork [U-Boot] arm, at91: add spi dataflash support for the taurus board
http://patchwork.ozlabs.org/patch/395400/

Changes in v2:
- rebased against d58a9451e7339ed4cf2b2627e534611f427fb791
- spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header new in v2
- add comment from Jagan Teki:
- remove spi_init_f() from board file
- remove CONFIG_SYS_SPI_WRITE_TOUT from board config file instead define a default in the spi driver -> new patch for v2
- add Reviewed-by: Andreas Bie?mann <[email protected]>
- add comment from Andreas Biessmann:
rename "MPDDRC_CR_EBISHARE" to "MPDDRC_CR_DQMS_SHARED"
- add comment from scott wood:
move nand_erase_one into "include/nand.h" and rename it to spl_nand_erase_one

Heiko Schocher (12):
spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header arm, at91: add spi dataflash support for the taurus board arm, at91, mpddrc: fix typo in ddr2_init()
arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45 arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define spl, nand: add option to boot raw u-boot.bin image only
mtd: atmel_nand: add missign include
spl, nand, atmel_nand: add erase one block function spl, mtd, nand, atmel_nand: invert device ready pin logic arm, spl, at91: add at91sam9260 and at91sam9g45 spl support arm, at91, spl: add spl support for the taurus board arm, spl, at91: add spl support for the corvus board

 README                                             |   4 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c  |  22 +++
 arch/arm/cpu/arm926ejs/at91/clock.c                |  60 +++++++
 arch/arm/cpu/armv7/at91/clock.c                    |  27 +++
 arch/arm/cpu/at91-common/Makefile                  |   7 +-
 arch/arm/cpu/at91-common/mpddrc.c                  |  14 +-
 arch/arm/cpu/at91-common/sdram.c                   |  77 +++++++++
 arch/arm/cpu/at91-common/spl.c                     | 185 +++++++++++++++------
 arch/arm/include/asm/arch-at91/at91_common.h       |   4 +
 arch/arm/include/asm/arch-at91/at91_pmc.h          |   5 +-
 arch/arm/include/asm/arch-at91/at91sam9260.h       |   1 +
 .../arm/include/asm/arch-at91/at91sam9260_matrix.h |   5 +
 arch/arm/include/asm/arch-at91/at91sam9_sdramc.h   |  22 ++-
 arch/arm/include/asm/arch-at91/atmel_mpddrc.h      |   1 +
 board/siemens/corvus/board.c                       | 109 ++++++++++--
 board/siemens/taurus/taurus.c                      |  91 ++++++++--
 common/spl/spl.c                                   |  15 +-
 common/spl/spl_nand.c                              |  13 ++
 configs/corvus_defconfig                           |   5 +-
 configs/taurus_defconfig                           |   5 +-
 drivers/mtd/nand/atmel_nand.c                      |  40 ++++-
 drivers/spi/atmel_spi.h                            |   4 +
 include/configs/afeb9260.h                         |   1 -
 include/configs/at91sam9260ek.h                    |   1 -
 include/configs/at91sam9261ek.h                    |   1 -
 include/configs/at91sam9263ek.h                    |   1 -
 include/configs/at91sam9rlek.h                     |   1 -
 include/configs/corvus.h                           |  54 +++++-
 include/configs/ethernut5.h                        |   1 -
 include/configs/meesc.h                            |   1 -
 include/configs/otc570.h                           |   1 -
 include/configs/pm9261.h                           |   1 -
 include/configs/pm9263.h                           |   1 -
 include/configs/sbc35_a9g20.h                      |   1 -
 include/configs/taurus.h                           |  64 ++++++-
 include/configs/tny_a9260.h                        |   1 -
 include/configs/usb_a9263.h                        |   1 -
 include/nand.h                                     |   1 +
 include/spl.h                                      |   1 +
 40 files changed, 746 insertions(+), 105 deletions(-)
 create mode 100644 arch/arm/cpu/at91-common/sdram.c

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:14 UTC #1 lore raw

PATCH v2 1/12 spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header

move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value).

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2:
rebased against d58a9451e7339ed4cf2b2627e534611f427fb791 new in v2

 drivers/spi/atmel_spi.h         | 4 ++++
 include/configs/afeb9260.h      | 1 -
 include/configs/at91sam9260ek.h | 1 -
 include/configs/at91sam9261ek.h | 1 -
 include/configs/at91sam9263ek.h | 1 -
 include/configs/at91sam9rlek.h  | 1 -
 include/configs/ethernut5.h     | 1 -
 include/configs/meesc.h         | 1 -
 include/configs/otc570.h        | 1 -
 include/configs/pm9261.h        | 1 -
 include/configs/pm9263.h        | 1 -
 include/configs/sbc35_a9g20.h   | 1 -
 include/configs/tny_a9260.h     | 1 -
 include/configs/usb_a9263.h     | 1 -
 14 files changed, 4 insertions(+), 13 deletions(-)

drivers/spi/atmel_spi.h +4 -0

index d240945..1538a23 100644
@@ -94,3 +94,7 @@ static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave)
 	readl(as->regs + ATMEL_SPI_##reg)
 #define spi_writel(as, reg, value)				\
 	writel(value, as->regs + ATMEL_SPI_##reg)
+
+#if !defined(CONFIG_SYS_SPI_WRITE_TOUT)
+#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
+#endif

include/configs/afeb9260.h +0 -1

index 14bac15..932a309 100644
@@ -77,7 +77,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */

include/configs/at91sam9260ek.h +0 -1

index 73917b0..72247cc 100644
@@ -135,7 +135,6 @@
 #ifndef CONFIG_AT91SAM9G20EK_2MMC
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH		1
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */

include/configs/at91sam9261ek.h +0 -1

index 226f8c1..cb16bda 100644
@@ -107,7 +107,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */

include/configs/at91sam9263ek.h +0 -1

index b666d94..fa19e8b 100644
@@ -119,7 +119,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH		1
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define AT91_SPI_CLK			15000000

include/configs/at91sam9rlek.h +0 -1

index b8d5dd1..d5f0197 100644
@@ -100,7 +100,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH			1
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define AT91_SPI_CLK				15000000

include/configs/ethernut5.h +0 -1

index 4c69af6..ce61a16 100644
@@ -78,7 +78,6 @@
 
 /* SPI */
 #define CONFIG_ATMEL_SPI
-#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
 #define AT91_SPI_CLK			15000000
 
 /* Serial port */

include/configs/meesc.h +0 -1

index 86ce5f2..955d0e2 100644
@@ -124,7 +124,6 @@
 #ifdef CONFIG_SYS_USE_DATAFLASH
 # define CONFIG_ATMEL_DATAFLASH_SPI
 # define CONFIG_HAS_DATAFLASH
-# define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 # define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 # define AT91_SPI_CLK				15000000

include/configs/otc570.h +0 -1

index 629967d..2390beb 100644
@@ -174,7 +174,6 @@
 #ifdef CONFIG_SYS_USE_DATAFLASH
 # define CONFIG_ATMEL_DATAFLASH_SPI
 # define CONFIG_HAS_DATAFLASH
-# define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 # define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 # define AT91_SPI_CLK				15000000

include/configs/pm9261.h +0 -1

index 4a71927..0746056 100644
@@ -202,7 +202,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */

include/configs/pm9263.h +0 -1

index d9c04d1..f0f12af 100644
@@ -216,7 +216,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH			1
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define AT91_SPI_CLK				15000000

include/configs/sbc35_a9g20.h +0 -1

index a1b5751..e7c35ec 100644
@@ -80,7 +80,6 @@
 #define CONFIG_SPI
 #define CONFIG_CMD_SPI
 #define CONFIG_ATMEL_SPI
-#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
 
 #define CONFIG_CMD_EEPROM
 #define CONFIG_SPI_M95XXX

include/configs/tny_a9260.h +0 -1

index 32f6b00..79c7fc5 100644
@@ -85,7 +85,6 @@
 #define CONFIG_SPI
 #define CONFIG_CMD_SPI
 #define CONFIG_ATMEL_SPI
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 
 #define CONFIG_CMD_EEPROM
 #define CONFIG_SPI_M95XXX

include/configs/usb_a9263.h +0 -1

index 3c54870..84571f6 100644
@@ -85,7 +85,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
 #define AT91_SPI_CLK				8000000

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:14 UTC #2 lore raw

PATCH v2 2/12 arm, at91: add spi dataflash support for the taurus board

In reply to Heiko Schocher

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2:
- add comment from Jagan Teki:
- remove spi_init_f() from board file
- remove CONFIG_SYS_SPI_WRITE_TOUT from board config file instead define a default in the spi driver -> new patch for v2

 board/siemens/taurus/taurus.c | 18 ++++++++++++++++++
 include/configs/taurus.h      | 10 ++++++++++
 2 files changed, 28 insertions(+)

board/siemens/taurus/taurus.c +18 -0

index 673b302..76609c7 100644
@@ -22,6 +22,8 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9_sdramc.h>
 #include <atmel_mci.h>
+#include <asm/arch/at91_spi.h>
+#include <spi.h>
 
 #include <net.h>
 #include <netdev.h>

@@ -127,6 +129,21 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
+}
+
 int board_init(void)
 {
 	/* adress of boot parameters */

@@ -139,6 +156,7 @@ int board_init(void)
 #ifdef CONFIG_MACB
 	taurus_macb_hw_init();
 #endif
+	at91_spi0_hw_init(TAURUS_SPI_MASK);
 
 	return 0;
 }

include/configs/taurus.h +10 -0

index aadf4cd..ba9496f 100644
@@ -127,6 +127,16 @@
 #define CONFIG_USB_STORAGE
 #endif
 
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define TAURUS_SPI_MASK (1 << 4)
+#define TAURUS_SPI_CS_PIN	AT91_PIN_PA3
+
 /* load address */
 #define CONFIG_SYS_LOAD_ADDR			0x22000000

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:14 UTC #3 lore raw

PATCH v2 3/12 arm, at91, mpddrc: fix typo in ddr2_init()

In reply to Heiko Schocher

use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support.

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Andreas Bie?mann <[email protected]>

---

Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>

 arch/arm/cpu/at91-common/mpddrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

arch/arm/cpu/at91-common/mpddrc.c +2 -1

index 8136396..76668d2 100644
@@ -26,7 +26,8 @@ int ddr2_init(const unsigned int ram_address,
 	/* Compute bank offset according to NC in configuration register */
 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
 	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
-		ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2)
+			   + 11;
 
 	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;

Signature · 1 line

1.8.3.1

Bo Shen

2014-10-31 01:55 UTC #4 lore raw

PATCH v2 3/12 arm, at91, mpddrc: fix typo in ddr2_init()

Hi Heiko,

Quoted 21 lines · Heiko Schocher

use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support.
Signed-off-by Heiko Schocher <[email protected]>
Reviewed-by Andreas Bie?mann <[email protected]>
---
Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>
  arch/arm/cpu/at91-common/mpddrc.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm/cpu/at91-common/mpddrc.c +0 -0
index 8136396..76668d2 100644

arch/arm/cpu/at91-common/mpddrc.c int ddr2_init(const unsigned int ram_address, · line 30

Quoted 6 lines

arch/arm/cpu/at91-common/mpddrc.c +2 -1

@@ -26,7 +26,8 @@ int ddr2_init(const unsigned int ram_address,
  	/* Compute bank offset according to NC in configuration register */
  	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
  	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
-		ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2)
+			   + 11;

As Andreas suggested, can we ignore the 80 character's warning here?

arch/arm/cpu/at91-common/mpddrc.c int ddr2_init(const unsigned int ram_address,

Quoted 3 lines

arch/arm/cpu/at91-common/mpddrc.c +0 -0

  	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;

Best Regards,
Bo Shen

Heiko Schocher

author

2014-10-31 05:33 UTC #5 lore raw

PATCH v2 3/12 arm, at91, mpddrc: fix typo in ddr2_init()

Hello Bo,

Am 31.10.2014 02:55, schrieb Bo Shen:

Quoted 19 lines

Hi Heiko,
Quoted 16 lines · Heiko Schocher
use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support.
Signed-off-by Heiko Schocher <[email protected]>
Reviewed-by Andreas Bie?mann <[email protected]>
---
Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>
arch/arm/cpu/at91-common/mpddrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

Quoted 13 lines

arch/arm/cpu/at91-common/mpddrc.c int ddr2_init(const unsigned int ram_address, · line 30
Quoted 11 lines
arch/arm/cpu/at91-common/mpddrc.c +2 -1
index 8136396..76668d2 100644
@@ -26,7 +26,8 @@ int ddr2_init(const unsigned int ram_address,
 /* Compute bank offset according to NC in configuration register */
 ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
 if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
- ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+ ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2)
+ + 11;
As Andreas suggested, can we ignore the 80 character's warning here?

Ok, changes this ... so I send a v3.

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Heiko Schocher

author

2014-10-30 08:14 UTC #6 lore raw

PATCH v2 4/12 arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45

In reply to Heiko Schocher

- compile mpddrc ram init code also for AT91SAM9M10G45
based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED in the cr configuration

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Andreas Bie?mann <[email protected]>

---

Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>

 arch/arm/cpu/at91-common/Makefile |  6 +++++-
 arch/arm/cpu/at91-common/mpddrc.c | 11 ++++++++++-
 2 files changed, 15 insertions(+), 2 deletions(-)

arch/arm/cpu/at91-common/Makefile +5 -1

index 5b97838..f62863a 100644
@@ -9,4 +9,8 @@
 #
 
 obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
-obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
+ifneq ($(CONFIG_SPL_BUILD),)
+obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o
+obj-$(CONFIG_SAMA5D3) += mpddrc.o
+obj-y += spl.o
+endif

arch/arm/cpu/at91-common/mpddrc.c +10 -1

index 76668d2..602e71e 100644
@@ -17,6 +17,15 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
 	writel(0, ram_address);
 }
 
+static int ddr2_decodtype_is_seq(u32 cr)
+{
+#if defined(CONFIG_SAMA5D3)
+	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
+		return 0;
+#endif
+	return 1;
+}
+
 int ddr2_init(const unsigned int ram_address,
 	      const struct atmel_mpddr *mpddr_value)
 {

@@ -25,7 +34,7 @@ int ddr2_init(const unsigned int ram_address,
 
 	/* Compute bank offset according to NC in configuration register */
 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
-	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+	if (ddr2_decodtype_is_seq(mpddr_value->cr))
 		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2)
 			   + 11;

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:14 UTC #7 lore raw

PATCH v2 5/12 arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define

In reply to Heiko Schocher

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2:
add comment from Andreas Biessmann:
- rename "MPDDRC_CR_EBISHARE" to "MPDDRC_CR_DQMS_SHARED"

 arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 1 +
 1 file changed, 1 insertion(+)

arch/arm/include/asm/arch-at91/atmel_mpddrc.h +1 -0

index 5741f6e..130a85a 100644
@@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address,
 #define ATMEL_MPDDRC_CR_DIC_DS			(0x1 << 8)
 #define ATMEL_MPDDRC_CR_DIS_DLL			(0x1 << 9)
 #define ATMEL_MPDDRC_CR_OCD_DEFAULT		(0x7 << 12)
+#define ATMEL_MPDDRC_CR_DQMS_SHARED		(0x1 << 16)
 #define ATMEL_MPDDRC_CR_ENRDM_ON		(0x1 << 17)
 #define ATMEL_MPDDRC_CR_NB_8BANKS		(0x1 << 20)
 #define ATMEL_MPDDRC_CR_NDQS_DISABLED		(0x1 << 21)

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:15 UTC #8 lore raw

PATCH v2 6/12 spl, nand: add option to boot raw u-boot.bin image only

In reply to Heiko Schocher

enable to boot only a raw u-boot.bin image from nand with the CONFIG_SPL_NAND_RAW_ONLY define. This option saves space on boards where spl space is low.

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Andreas Bie?mann <[email protected]>

---
on the siemens taurus board, this option saved 0x14d bytes

Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>

 README                |  4 ++++
 common/spl/spl.c      | 15 ++++++++++-----
 common/spl/spl_nand.c | 13 +++++++++++++
 include/spl.h         |  1 +
 4 files changed, 28 insertions(+), 5 deletions(-)

README +4 -0

index 7b5538e..a34902b 100644
@@ -3605,6 +3605,10 @@ FIT uImage format:
 		Support for the MTD subsystem within SPL.  Useful for
 		environment on NAND support within SPL.
 
+		CONFIG_SPL_NAND_RAW_ONLY
+		Support to boot only raw u-boot.bin images. Use this only
+		if you need to save space.
+
 		CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 		Set for the SPL on PPC mpc8xxx targets, support for
 		drivers/ddr/fsl/libddr.o in SPL binary.

common/spl/spl.c +10 -5

index d85bab3..f01a21c 100644
@@ -62,6 +62,15 @@ __weak void spl_board_prepare_for_linux(void)
 	/* Nothing to do! */
 }
 
+void spl_set_header_raw_uboot(void)
+{
+	spl_image.size = CONFIG_SYS_MONITOR_LEN;
+	spl_image.entry_point = CONFIG_SYS_UBOOT_START;
+	spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
+	spl_image.os = IH_OS_U_BOOT;
+	spl_image.name = "U-Boot";
+}
+
 void spl_parse_image_header(const struct image_header *header)
 {
 	u32 header_size = sizeof(struct image_header);

@@ -93,11 +102,7 @@ void spl_parse_image_header(const struct image_header *header)
 		/* Signature not found - assume u-boot.bin */
 		debug("mkimage signature not found - ih_magic = %x\n",
 			header->ih_magic);
-		spl_image.size = CONFIG_SYS_MONITOR_LEN;
-		spl_image.entry_point = CONFIG_SYS_UBOOT_START;
-		spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
-		spl_image.os = IH_OS_U_BOOT;
-		spl_image.name = "U-Boot";
+		spl_set_header_raw_uboot();
 	}
 }

common/spl/spl_nand.c +13 -0

index 9b200bc..b7801cb 100644
@@ -10,6 +10,18 @@
 #include <asm/io.h>
 #include <nand.h>
 
+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
+void spl_nand_load_image(void)
+{
+	nand_init();
+
+	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			    CONFIG_SYS_NAND_U_BOOT_SIZE,
+			    (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+	spl_set_header_raw_uboot();
+	nand_deselect();
+}
+#else
 void spl_nand_load_image(void)
 {
 	struct image_header *header;

@@ -82,3 +94,4 @@ void spl_nand_load_image(void)
 		spl_image.size, (void *)spl_image.load_addr);
 	nand_deselect();
 }
+#endif

include/spl.h +1 -0

index 16b3566..b2e5bf7 100644
@@ -35,6 +35,7 @@ extern struct spl_image_info spl_image;
 void preloader_console_init(void);
 u32 spl_boot_device(void);
 u32 spl_boot_mode(void);
+void spl_set_header_raw_uboot(void);
 void spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
 void __noreturn jump_to_image_linux(void *arg);

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:15 UTC #9 lore raw

PATCH v2 7/12 mtd: atmel_nand: add missign include

In reply to Heiko Schocher

using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this.

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Andreas Bie?mann <[email protected]>

---

Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>

 drivers/mtd/nand/atmel_nand.c | 1 +
 1 file changed, 1 insertion(+)

drivers/mtd/nand/atmel_nand.c +1 -0

index 9114a86..d506e42 100644
@@ -18,6 +18,7 @@
 #include <malloc.h>
 #include <nand.h>
 #include <watchdog.h>
+#include <linux/mtd/nand_ecc.h>
 
 #ifdef CONFIG_ATMEL_NAND_HWECC

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:15 UTC #10 lore raw

PATCH v2 8/12 spl, nand, atmel_nand: add erase one block function

In reply to Heiko Schocher

erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support.

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2:
add comment from scott wood:
- move nand_erase_one into "include/nand.h" and rename it to spl_nand_erase_one

 drivers/mtd/nand/atmel_nand.c | 33 +++++++++++++++++++++++++++++++++
 include/nand.h                |  1 +
 2 files changed, 34 insertions(+)

drivers/mtd/nand/atmel_nand.c +33 -0

index d506e42..d6d6f85 100644
@@ -1274,6 +1274,39 @@ static int nand_read_page(int block, int page, void *dst)
 
 	return 0;
 }
+
+int spl_nand_erase_one(int block, int page)
+{
+	struct nand_chip *this = mtd.priv;
+	void (*hwctrl)(struct mtd_info *mtd, int cmd,
+			unsigned int ctrl) = this->cmd_ctrl;
+	int page_addr;
+
+	if (nand_chip.select_chip)
+		nand_chip.select_chip(&mtd, 0);
+
+	page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+	hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	/* Row address */
+	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+	/* One more address cycle for devices > 128MiB */
+	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+#endif
+
+	hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	udelay(2000);
+
+	while (!this->dev_ready(&mtd))
+		;
+
+	nand_deselect();
+
+	return 0;
+}
 #else
 static int nand_read_page(int block, int page, void *dst)
 {

include/nand.h +1 -0

index fc735d1..15e31ab 100644
@@ -167,3 +167,4 @@ __attribute__((noreturn)) void nand_boot(void);
 #define ENV_OFFSET_SIZE 8
 int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
 #endif
+int spl_nand_erase_one(int block, int page);

Signature · 1 line

1.8.3.1

Scott Wood

2014-10-30 23:16 UTC #11 lore raw

PATCH v2 8/12 spl, nand, atmel_nand: add erase one block function

Quoted 7 lines · Heiko Schocher

erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support.
Signed-off-by Heiko Schocher <[email protected]>
---

Quoted 8 lines

Changes in v2:
add comment from scott wood:
- move nand_erase_one into "include/nand.h" and rename it to spl_nand_erase_one
 drivers/mtd/nand/atmel_nand.c | 33 +++++++++++++++++++++++++++++++++
 include/nand.h                |  1 +
 2 files changed, 34 insertions(+)

Acked-by Scott Wood <[email protected]>

-Scott

Heiko Schocher

author

2014-10-30 08:15 UTC #12 lore raw

PATCH v2 9/12 spl, mtd, nand, atmel_nand: invert device ready pin logic

In reply to Heiko Schocher

device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c

Signed-off-by Heiko Schocher <[email protected]>

Reviewed-by Andreas Bie?mann <[email protected]>

---

Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>

 drivers/mtd/nand/atmel_nand.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

drivers/mtd/nand/atmel_nand.c +3 -3

index d6d6f85..3b6093a 100644
@@ -1188,7 +1188,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (this->dev_ready(&mtd))
+	while (!this->dev_ready(&mtd))
 		;
 
 	if (cmd == NAND_CMD_READOOB) {

@@ -1213,7 +1213,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 	hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	while (this->dev_ready(&mtd))
+	while (!this->dev_ready(&mtd))
 		;
 
 	return 0;

@@ -1353,7 +1353,7 @@ int at91_nand_wait_ready(struct mtd_info *mtd)
 
 	udelay(this->chip_delay);
 
-	return 0;
+	return 1;
 }
 
 int board_nand_init(struct nand_chip *nand)

Signature · 1 line

1.8.3.1

Scott Wood

2014-10-30 23:18 UTC #13 lore raw

PATCH v2 9/12 spl, mtd, nand, atmel_nand: invert device ready pin logic

Quoted 6 lines · Heiko Schocher

device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c
Signed-off-by Heiko Schocher <[email protected]>
Reviewed-by Andreas Bie?mann <[email protected]>

Quoted 7 lines

---
Changes in v2:
add Reviewed-by: Andreas Bie?mann <[email protected]>
 drivers/mtd/nand/atmel_nand.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Acked-by Scott Wood <[email protected]>

-Scott

Heiko Schocher

author

2014-10-30 08:15 UTC #14 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

In reply to Heiko Schocher

add support for using spl code on at91sam9260 and at91sam9g45 based boards.

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2: None

 arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c  |  22 +++
 arch/arm/cpu/arm926ejs/at91/clock.c                |  60 +++++++
 arch/arm/cpu/armv7/at91/clock.c                    |  27 +++
 arch/arm/cpu/at91-common/Makefile                  |   1 +
 arch/arm/cpu/at91-common/sdram.c                   |  77 +++++++++
 arch/arm/cpu/at91-common/spl.c                     | 185 +++++++++++++++------
 arch/arm/include/asm/arch-at91/at91_common.h       |   4 +
 arch/arm/include/asm/arch-at91/at91_pmc.h          |   5 +-
 arch/arm/include/asm/arch-at91/at91sam9260.h       |   1 +
 .../arm/include/asm/arch-at91/at91sam9260_matrix.h |   5 +
 arch/arm/include/asm/arch-at91/at91sam9_sdramc.h   |  22 ++-
 11 files changed, 359 insertions(+), 50 deletions(-)
 create mode 100644 arch/arm/cpu/at91-common/sdram.c

arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +22 -0

index cae4abc..7a7fd7d 100644
@@ -8,8 +8,10 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91sam9_sdramc.h>
 #include <asm/arch/gpio.h>
 
 /*

@@ -207,3 +209,23 @@ void at91_mci_hw_init(void)
 #endif
 }
 #endif
+
+void at91_sdram_hw_init(void)
+{
+	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
+	at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
+}

arch/arm/cpu/arm926ejs/at91/clock.c +60 -0

63 lines not on this page · raw message

arch/arm/cpu/armv7/at91/clock.c +27 -0

index 36ed4a6..363081a 100644
@@ -111,6 +111,33 @@ int at91_clock_init(unsigned long main_clock)
 	return 0;
 }
 
+void at91_plla_init(u32 pllar)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(pllar, &pmc->pllar);
+	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
+		;
+}
+
+void at91_mck_init(u32 mckr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
+		 AT91_PMC_MCKR_MDIV_MASK |
+		 AT91_PMC_MCKR_PLLADIV_2);
+	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
+		       AT91_PMC_MCKR_MDIV_MASK |
+		       AT91_PMC_MCKR_PLLADIV_2);
+	writel(tmp, &pmc->mckr);
+
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+}
+
 void at91_periph_clk_enable(int id)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

arch/arm/cpu/at91-common/Makefile +1 -0

index f62863a..5bdfb6a 100644
@@ -10,6 +10,7 @@
 
 obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
 ifneq ($(CONFIG_SPL_BUILD),)
+obj-$(CONFIG_AT91SAM9G20) += sdram.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o
 obj-y += spl.o

arch/arm/cpu/at91-common/sdram.c new file +77 -0

77 lines not on this page · raw message

arch/arm/cpu/at91-common/spl.c +138 ~~-47~~

232 lines not on this page · raw message

arch/arm/include/asm/arch-at91/at91_common.h +4 -0

index 59e2f43..2d94090 100644
@@ -23,9 +23,13 @@ void at91_udp_hw_init(void);
 void at91_uhp_hw_init(void);
 void at91_lcd_hw_init(void);
 void at91_plla_init(u32 pllar);
+void at91_pllb_init(u32 pllar);
 void at91_mck_init(u32 mckr);
 void at91_pmc_init(void);
 void mem_init(void);
 void at91_phy_reset(void);
+void at91_sdram_hw_init(void);
+void at91_mck_init(u32 mckr);
+void at91_spl_board_init(void);
 
 #endif /* AT91_COMMON_H */

arch/arm/include/asm/arch-at91/at91_pmc.h +3 -2

index 27331ff..5f64583 100644
@@ -95,7 +95,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_MAIN		0x00000001
 #define AT91_PMC_MCKR_CSS_PLLA		0x00000002
 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
-#define AT91_PMC_MCKR_CSS_MASK		0x00000003
+#define AT91_PMC_MCKR_CSS_MASK		0x00000007
 
 #ifdef CONFIG_SAMA5D3
 #define AT91_PMC_MCKR_PRES_1		0x00000000

@@ -114,7 +114,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PRES_16		0x00000010
 #define AT91_PMC_MCKR_PRES_32		0x00000014
 #define AT91_PMC_MCKR_PRES_64		0x00000018
-#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+#define AT91_PMC_MCKR_PRES_MASK		0x0000003C
 #endif
 
 #ifdef CONFIG_AT91RM9200

@@ -133,6 +133,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
 #endif
 
+#define AT91_PMC_MCKR_PLLADIV_MASK	0x00003000
 #define AT91_PMC_MCKR_PLLADIV_1		0x00000000
 #define AT91_PMC_MCKR_PLLADIV_2		0x00001000

arch/arm/include/asm/arch-at91/at91sam9260.h +1 -0

index 2e902ee..1e613fa 100644
@@ -95,6 +95,7 @@
 #define ATMEL_BASE_SDRAMC	0xffffea00
 #define ATMEL_BASE_SMC		0xffffec00
 #define ATMEL_BASE_MATRIX	0xffffee00
+#define ATMEL_BASE_CCFG         0xffffef14
 #define ATMEL_BASE_AIC		0xfffff000
 #define ATMEL_BASE_DBGU		0xfffff200
 #define ATMEL_BASE_PIOA		0xfffff400

arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +5 -0

index 4755fa1..dc61f48 100644
@@ -61,5 +61,10 @@ struct at91_matrix {
 #define AT91_MATRIX_DBPUC		(1 << 8)
 #define AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
 #define AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+#define AT91_MATRIX_EBI_IOSR_SEL	(1 << 17)
+
+/* Maximum Number of Allowed Cycles for a Burst */
+#define AT91_MATRIX_SLOT_CYCLE		(0xff << 0)
+#define AT91_MATRIX_SLOT_CYCLE_(x)	(x << 0)
 
 #endif

arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +21 -1

index 5c98cc7..3a076c6 100644
@@ -25,6 +25,21 @@
 #define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
 #define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
 
+#else
+struct sdramc_reg {
+	u32	mr;
+	u32	tr;
+	u32	cr;
+	u32	lpr;
+	u32	ier;
+	u32	idr;
+	u32	imr;
+	u32	isr;
+	u32	mdr;
+};
+
+int sdramc_initialize(unsigned int sdram_address,
+		      const struct sdramc_reg *p);
 #endif
 
 /* SDRAM Controller (SDRAMC) registers */

@@ -62,11 +77,17 @@
 #define			AT91_SDRAMC_DBW_32	(0 << 7)
 #define			AT91_SDRAMC_DBW_16	(1 << 7)
 #define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
+#define		AT91_SDRAMC_TWR_VAL(x)	(x << 8)
 #define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
+#define			AT91_SDRAMC_TRC_VAL(x)	(x << 12)
 #define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
+#define		AT91_SDRAMC_TRP_VAL(x)	(x << 16)
 #define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
+#define			AT91_SDRAMC_TRCD_VAL(x)	(x << 20)
 #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
+#define		AT91_SDRAMC_TRAS_VAL(x)	(x << 24)
 #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
+#define		AT91_SDRAMC_TXSR_VAL(x)	(x << 28)
 
 #define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */

@@ -93,5 +114,4 @@
 #define			AT91_SDRAMC_MD_SDRAM		0
 #define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
 
-
 #endif

Signature · 1 line

1.8.3.1

Bo Shen

2014-10-30 10:17 UTC #15 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

Hi Heiko,

arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 98

Quoted 10 lines · Heiko Schocher

arch/arm/include/asm/arch-at91/at91_pmc.h +1 -1

index 27331ff..5f64583 100644
@@ -95,7 +95,7 @@ typedef struct at91_pmc {
  #define AT91_PMC_MCKR_CSS_MAIN		0x00000001
  #define AT91_PMC_MCKR_CSS_PLLA		0x00000002
  #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
-#define AT91_PMC_MCKR_CSS_MASK		0x00000003
+#define AT91_PMC_MCKR_CSS_MASK		0x00000007

Where this come from, CSS only two bits.

arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 117

Quoted 8 lines

arch/arm/include/asm/arch-at91/at91_pmc.h +1 -1

  #ifdef CONFIG_SAMA5D3
  #define AT91_PMC_MCKR_PRES_1		0x00000000

@@ -114,7 +114,7 @@ typedef struct at91_pmc {
  #define AT91_PMC_MCKR_PRES_16		0x00000010
  #define AT91_PMC_MCKR_PRES_32		0x00000014
  #define AT91_PMC_MCKR_PRES_64		0x00000018
-#define AT91_PMC_MCKR_PRES_MASK		0x0000001C
+#define AT91_PMC_MCKR_PRES_MASK		0x0000003C

Ditto

arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 118

Quoted 1 line

arch/arm/include/asm/arch-at91/at91_pmc.h +0 -0
  #endif

Best Regards,
Bo Shen

Heiko Schocher

author

2014-10-30 11:41 UTC #16 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

Hello Bo,

Am 30.10.2014 11:17, schrieb Bo Shen:

Quoted 15 lines

Hi Heiko,
arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 98
Quoted 10 lines · Heiko Schocher
arch/arm/include/asm/arch-at91/at91_pmc.h +1 -1
index 27331ff..5f64583 100644
@@ -95,7 +95,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_MAIN 0x00000001
 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002
 #define AT91_PMC_MCKR_CSS_PLLB 0x00000003
-#define AT91_PMC_MCKR_CSS_MASK 0x00000003
+#define AT91_PMC_MCKR_CSS_MASK 0x00000007
Where this come from, CSS only two bits.

Good question ... looked again into the doc, it is only two bits.

Quoted 11 lines

arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 117

Quoted 9 lines

arch/arm/include/asm/arch-at91/at91_pmc.h +1 -1

 #ifdef CONFIG_SAMA5D3
 #define AT91_PMC_MCKR_PRES_1 0x00000000

@@ -114,7 +114,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PRES_16 0x00000010
 #define AT91_PMC_MCKR_PRES_32 0x00000014
 #define AT91_PMC_MCKR_PRES_64 0x00000018
-#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
+#define AT91_PMC_MCKR_PRES_MASK 0x0000003C

Ditto

Hmm... no idea, why I changed this ... good catch!

Is the rest of the patch (and the patchserie OK) ?

Then I can send a v3 ...

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Bo Shen

2014-10-31 01:55 UTC #17 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

Hi Heiko,

Quoted 34 lines · Heiko Schocher

Hello Bo,
Am 30.10.2014 11:17, schrieb Bo Shen:
Quoted 16 lines
Hi Heiko,
arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 98
Quoted 11 lines · Heiko Schocher
arch/arm/include/asm/arch-at91/at91_pmc.h +1 -1
index 27331ff..5f64583 100644
@@ -95,7 +95,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_MAIN 0x00000001
 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002
 #define AT91_PMC_MCKR_CSS_PLLB 0x00000003
-#define AT91_PMC_MCKR_CSS_MASK 0x00000003
+#define AT91_PMC_MCKR_CSS_MASK 0x00000007
Where this come from, CSS only two bits.
Good question ... looked again into the doc, it is only two bits.
Quoted 11 lines
arch/arm/include/asm/arch-at91/at91_pmc.h typedef struct at91_pmc { · line 117
Quoted 9 lines
arch/arm/include/asm/arch-at91/at91_pmc.h +1 -1
 #ifdef CONFIG_SAMA5D3
 #define AT91_PMC_MCKR_PRES_1 0x00000000
@@ -114,7 +114,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PRES_16 0x00000010
 #define AT91_PMC_MCKR_PRES_32 0x00000014
 #define AT91_PMC_MCKR_PRES_64 0x00000018
-#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
+#define AT91_PMC_MCKR_PRES_MASK 0x0000003C
Ditto

Quoted 3 lines

Hmm... no idea, why I changed this ... good catch!
Is the rest of the patch (and the patchserie OK) ?

Except one suggestion and nitpick sent just now, the rest patch seems good. For this whole series:

Reviewed-by Bo Shen <[email protected]>

Quoted 4 lines

Then I can send a v3 ...
bye,
Heiko

Best Regards,
Bo Shen

Bo Shen

2014-10-31 01:50 UTC #18 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

In reply to Heiko Schocher

Hi Heiko,

arch/arm/cpu/at91-common/spl.c

Quoted 4 lines · Heiko Schocher

arch/arm/cpu/at91-common/spl.c +0 -0
index 674a470..5c9a3ad 100644

I am thinking, whether it be better to keep this file as two copy? This will remove #ifdef, although a little code duplication.

If this solution acceptable, some suggestion as following:
- for armv5 (arm926ejs, now at91 series), named it spl_at91.c,
- for armv7 (cortex-a5, now, sama5d3), named it spl_atmel.c?
(As for arm9 series, we have at91 prefix for SoC name, and for armv7 SoC, we don't have at91 prefix, and it now changed to Atmel Smart)

Quoted 205 lines

arch/arm/cpu/at91-common/spl.c +113 ~~-47~~

@@ -8,11 +8,18 @@
  #include <common.h>
  #include <asm/io.h>
  #include <asm/arch/at91_common.h>
+#if !defined(CONFIG_SAMA5D3)
+#include <asm/arch/at91sam9_matrix.h>
+#endif
+#include <asm/arch/at91_pit.h>
  #include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
  #include <asm/arch/at91_wdt.h>
  #include <asm/arch/clk.h>
  #include <spl.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
  static void at91_disable_wdt(void)
  {
  	struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;

@@ -20,6 +27,33 @@ static void at91_disable_wdt(void)
  	writel(AT91_WDT_MR_WDDIS, &wdt->mr);
  }
 
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	return BOOT_DEVICE_MMC1;
+#elif CONFIG_SYS_USE_NANDFLASH
+	return BOOT_DEVICE_NAND;
+#elif CONFIG_SYS_USE_SERIALFLASH
+	return BOOT_DEVICE_SPI;
+#endif
+	return BOOT_DEVICE_NONE;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+#ifdef CONFIG_SYS_USE_MMC
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FS;
+		break;
+#endif
+	case BOOT_DEVICE_NONE:
+	default:
+		hang();
+	}
+}
+
+#if defined(CONFIG_SAMA5D3)
  static void switch_to_main_crystal_osc(void)
  {
  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

@@ -57,77 +91,134 @@ static void switch_to_main_crystal_osc(void)
  	writel(tmp, &pmc->mor);
  }
 
-void at91_plla_init(u32 pllar)
+void s_init(void)
  {
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	switch_to_main_crystal_osc();
 
-	writel(pllar, &pmc->pllar);
-	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
-		;
-}
+	/* disable watchdog */
+	at91_disable_wdt();
 
-void at91_mck_init(u32 mckr)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 tmp;
+	/* PMC configuration */
+	at91_pmc_init();
 
-	tmp = readl(&pmc->mckr);
-	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
-		 AT91_PMC_MCKR_MDIV_MASK |
-		 AT91_PMC_MCKR_PLLADIV_2);
-	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
-		       AT91_PMC_MCKR_MDIV_MASK |
-		       AT91_PMC_MCKR_PLLADIV_2);
-	writel(tmp, &pmc->mckr);
+	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
 
-	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
-		;
-}
+	timer_init();
 
+	board_early_init_f();
 
-u32 spl_boot_device(void)
+	preloader_console_init();
+
+	mem_init();
+}
+#else
+static void enable_ext_reset(void)
  {
-#ifdef CONFIG_SYS_USE_MMC
-	return BOOT_DEVICE_MMC1;
-#elif CONFIG_SYS_USE_NANDFLASH
-	return BOOT_DEVICE_NAND;
-#elif CONFIG_SYS_USE_SERIALFLASH
-	return BOOT_DEVICE_SPI;
-#endif
-	return BOOT_DEVICE_NONE;
+	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
+
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
  }
 
-u32 spl_boot_mode(void)
+#if defined(CONFIG_ATMEL_MATRIX_INIT)
+static void matrix_init(void)
  {
-	switch (spl_boot_device()) {
-#ifdef CONFIG_SYS_USE_MMC
-	case BOOT_DEVICE_MMC1:
-		return MMCSD_MODE_FS;
-		break;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+	writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
+			| AT91_MATRIX_SLOT_CYCLE_(0x40),
+			&mat->scfg[3]);
+}
  #endif
-	case BOOT_DEVICE_NONE:
-	default:
-		hang();
+
+void lowlevel_clock_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
+		/* Enable Main Oscillator */
+		writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
+
+		/* Wait until Main Oscillator is stable */
+		while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
+			;
  	}
+
+	/* After stabilization, switch to Main Oscillator */
+	if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
+		unsigned long tmp;
+
+		tmp = readl(&pmc->mckr);
+		tmp &= ~AT91_PMC_CSS;
+		tmp |= AT91_PMC_CSS_MAIN;
+		writel(tmp, &pmc->mckr);
+		while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+			;
+
+		tmp &= ~AT91_PMC_PRES;
+		tmp |= AT91_PMC_PRES_1;
+		writel(tmp, &pmc->mckr);
+		while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+			;
+	}
+
+	return;
  }
 
-void s_init(void)
+void __weak at91_spl_board_init(void)
  {
-	switch_to_main_crystal_osc();
+}
 
-	/* disable watchdog */
+void spl_board_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	lowlevel_clock_init();
  	at91_disable_wdt();
 
-	/* PMC configuration */
-	at91_pmc_init();
+	/*
+	 * At this stage the main oscillator is supposed to be enabled
+	 * PCK = MCK = MOSC
+	 */
+	writel(0x00, &pmc->pllicpr);
 
-	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+	at91_plla_init(CONFIG_SYS_AT91_PLLA);
 
-	timer_init();
+	/* PCK = PLLA = 2 * MCK */
+	at91_mck_init(CONFIG_SYS_MCKR);
 
-	board_early_init_f();
+	/* Switch MCK on PLLA output */
+	at91_mck_init(CONFIG_SYS_MCKR_CSS);
+
+#if defined(CONFIG_SYS_AT91_PLLB)
+	/* Configure PLLB */

arch/arm/cpu/at91-common/spl.c static void switch_to_main_crystal_osc(void) · line 204

Quoted 10 lines

arch/arm/cpu/at91-common/spl.c +9 -0

+	at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+#endif
+
+	/* Enable External Reset */
+	enable_ext_reset();
 
+#if defined(CONFIG_ATMEL_MATRIX_INIT)
+	/* Initialize matrix */
+	matrix_init();
+#endif

Can this also be weak function? And put matrix_init() code to SoC/board related file.

Quoted 9 lines

arch/arm/cpu/at91-common/spl.c +9 -0

+	gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
+	/*
+	 * init timer long enough for using in spl.
+	 */
+	timer_init();
+
+	/* enable clocks for all PIOs */
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);

arch/arm/cpu/at91-common/spl.c static void switch_to_main_crystal_osc(void) · line 224

Quoted 10 lines

arch/arm/cpu/at91-common/spl.c +6 -0

+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	/* init console */
+	at91_seriald_hw_init();
  	preloader_console_init();
 
  	mem_init();
+
+	at91_spl_board_init();
  }
+#endif

Best Regards,
Bo Shen

Heiko Schocher

author

2014-10-31 06:03 UTC #19 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

Hello Bo,

Am 31.10.2014 02:50, schrieb Bo Shen:

Quoted 10 lines

Hi Heiko,
arch/arm/cpu/at91-common/spl.c
Quoted 4 lines · Heiko Schocher
arch/arm/cpu/at91-common/spl.c +0 -0
index 674a470..5c9a3ad 100644
I am thinking, whether it be better to keep this file as two copy? This will remove #ifdef, although a little code duplication.

Quoted 4 lines

If this solution acceptable, some suggestion as following:
- for armv5 (arm926ejs, now at91 series), named it spl_at91.c,
- for armv7 (cortex-a5, now, sama5d3), named it spl_atmel.c?
(As for arm9 series, we have at91 prefix for SoC name, and for armv7 SoC, we don't have at91 prefix, and it now changed to Atmel Smart)

Ok, I look into this.

[...]

Quoted 1 line

Quoted 1 line
arch/arm/cpu/at91-common/spl.c +0 -0
@@ -57,77 +91,134 @@ static void switch_to_main_crystal_osc(void)

[...]

Quoted 36 lines

Quoted 36 lines
- /* disable watchdog */
arch/arm/cpu/at91-common/spl.c +5 -0
+void spl_board_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ lowlevel_clock_init();
at91_disable_wdt();
- /* PMC configuration */
- at91_pmc_init();
+ /*
+ * At this stage the main oscillator is supposed to be enabled
+ * PCK = MCK = MOSC
+ */
+ writel(0x00, &pmc->pllicpr);
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+ at91_plla_init(CONFIG_SYS_AT91_PLLA);
- timer_init();
+ /* PCK = PLLA = 2 * MCK */
+ at91_mck_init(CONFIG_SYS_MCKR);
- board_early_init_f();
+ /* Switch MCK on PLLA output */
+ at91_mck_init(CONFIG_SYS_MCKR_CSS);
arch/arm/cpu/at91-common/spl.c +8 -0
+
+#if defined(CONFIG_SYS_AT91_PLLB)
+ /* Configure PLLB */
+ at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+#endif
+
+ /* Enable External Reset */
+ enable_ext_reset();

Quoted 6 lines

arch/arm/cpu/at91-common/spl.c static void switch_to_main_crystal_osc(void) · line 204
Quoted 4 lines
arch/arm/cpu/at91-common/spl.c +4 -0
+#if defined(CONFIG_ATMEL_MATRIX_INIT)
+ /* Initialize matrix */
+ matrix_init();
+#endif
Can this also be weak function? And put matrix_init() code to SoC/board related file.

Changed.

Thanks!

bye,
Heiko

Signature · 2 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Wolfgang Denk

2014-10-31 06:08 UTC #20 lore raw

PATCH v2 10/12 arm, spl, at91: add at91sam9260 and at91sam9g45 spl support

In reply to Bo Shen

Dear Bo Shen,

Quoted 3 lines · In message <[email protected]> you wrote:

I am thinking, whether it be better to keep this file as two copy? This will remove #ifdef, although a little code duplication.

I agree that we should try and minimize #ifdef's, but code duplication is even worse.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The explanation requiring the fewest assumptions is the  most  likely
to be correct.                                    -- William of Occam

Heiko Schocher

author

2014-10-30 08:15 UTC #21 lore raw

PATCH v2 11/12 arm, at91, spl: add spl support for the taurus board

In reply to Heiko Schocher

replaces the at91bootstrap code with SPL code.

make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin

this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader.

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2:
- rename function "nand_erase_one" to "spl_nand_erase_one" as Scott Wood suggested

 arch/arm/Kconfig              |  1 +
 board/siemens/taurus/taurus.c | 73 +++++++++++++++++++++++++++++++++++++------
 configs/taurus_defconfig      |  5 +--
 include/configs/taurus.h      | 54 +++++++++++++++++++++++++++++++-
 4 files changed, 120 insertions(+), 13 deletions(-)

arch/arm/Kconfig +1 -0

index 7b20fab..abe1317 100644
@@ -128,6 +128,7 @@ config TARGET_CORVUS
 	bool "Support corvus"
 
 config TARGET_TAURUS
+	select SUPPORT_SPL
 	bool "Support taurus"
 
 config TARGET_STAMP9G20

board/siemens/taurus/taurus.c +63 ~~-10~~

110 lines not on this page · raw message

configs/taurus_defconfig +3 -2

index 9870048..438e25d 100644
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
-CONFIG_ARM=y
-CONFIG_TARGET_TAURUS=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_TAURUS=y

include/configs/taurus.h +53 -1

64 lines not on this page · raw message

Signature · 1 line

1.8.3.1

Heiko Schocher

author

2014-10-30 08:15 UTC #22 lore raw

PATCH v2 12/12 arm, spl, at91: add spl support for the corvus board

In reply to Heiko Schocher

replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin

this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader.

Signed-off-by Heiko Schocher <[email protected]>

---

Changes in v2:
- rename function "nand_erase_one" to "spl_nand_erase_one" as Scott Wood suggested
- add comment from Andreas Biessmann:
rename "MPDDRC_CR_EBISHARE" to "MPDDRC_CR_DQMS_SHARED"

 arch/arm/Kconfig             |   1 +
 board/siemens/corvus/board.c | 109 ++++++++++++++++++++++++++++++++++++++-----
 configs/corvus_defconfig     |   5 +-
 include/configs/corvus.h     |  54 +++++++++++++++++++--
 4 files changed, 151 insertions(+), 18 deletions(-)

arch/arm/Kconfig +1 -0

index abe1317..ff2d84c 100644
@@ -125,6 +125,7 @@ config TARGET_PM9G45
 	bool "Support pm9g45"
 
 config TARGET_CORVUS
+	select SUPPORT_SPL
 	bool "Support corvus"
 
 config TARGET_TAURUS

board/siemens/corvus/board.c +97 ~~-12~~

141 lines not on this page · raw message

configs/corvus_defconfig +3 -2

index 3fc8edb..5d60847 100644
@@ -1,3 +1,4 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
-CONFIG_ARM=y
-CONFIG_TARGET_CORVUS=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_CORVUS=y

include/configs/corvus.h +50 -4

77 lines not on this page · raw message

Signature · 1 line

1.8.3.1