Tegra124 PCIe
Subsystems (9)
cover Tegra124 PCIe
This series implements PCIe on Tegra124 aka K1. With this applied the Jetson-TK1 platform is finally useable for proper development, as the network is working now.
The series is spun against -next, as it depends on the previous Tegra PCIe work found there. I hope Sascha can still squeeze this in before the next release.
Lucas Stach (13):
net: rtl8169: add support for RTL-8168/8111g
net: rtl8169: clean receive buffer after net handler
tegra: defconfig: enable barebox OF drivers
pinctrl: tegra: try to select "boot" state
arm: dts: jetson-tk1: switch to upstream DT
clk: tegra: slow down MSELECT to 102MHz
tegra: pmc: work around power domain failure
tegra: jetson-tk1: enable 1.05V_RUN
clk: tegra124: add PLLE setup functions
clk: tegra124: add PCIe clocks
add generic PHY framework
pinctrl: tegra: add XUSB pad controller
pci: tegra: add tegra124 support
arch/arm/boards/nvidia-jetson-tk1/Makefile | 2 +- arch/arm/boards/nvidia-jetson-tk1/board.c | 50 + arch/arm/configs/tegra_v7_defconfig | 1 + arch/arm/dts/tegra124-jetson-tk1.dts | 1823 +--------------------------- arch/arm/mach-tegra/tegra20-pmc.c | 2 + drivers/Kconfig | 1 + drivers/Makefile | 1 + drivers/clk/tegra/clk-pll.c | 173 ++- drivers/clk/tegra/clk-tegra124.c | 37 +- drivers/clk/tegra/clk-tegra30.c | 2 +- drivers/clk/tegra/clk.h | 7 + drivers/net/rtl8169.c | 12 + drivers/pci/pci-tegra.c | 156 ++- drivers/phy/Kconfig | 18 + drivers/phy/Makefile | 5 + drivers/phy/phy-core.c | 318 +++++ drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-tegra-xusb.c | 519 ++++++++ drivers/pinctrl/pinctrl-tegra20.c | 8 +- drivers/pinctrl/pinctrl-tegra30.c | 8 +- include/linux/phy/phy.h | 240 ++++ 22 files changed, 1538 insertions(+), 1854 deletions(-) create mode 100644 arch/arm/boards/nvidia-jetson-tk1/board.c create mode 100644 drivers/phy/Kconfig create mode 100644 drivers/phy/Makefile create mode 100644 drivers/phy/phy-core.c create mode 100644 drivers/pinctrl/pinctrl-tegra-xusb.c create mode 100644 include/linux/phy/phy.h
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PATCH 1/13 net: rtl8169: add support for RTL-8168/8111g
This is the version of the chip found on Jetson-TK1.
Signed-off-by Lucas Stach <[email protected]>
--- drivers/net/rtl8169.c | 1 + 1 file changed, 1 insertion(+)
drivers/net/rtl8169.c +1 -0
@@ -166,6 +166,7 @@ static struct rtl8169_chip_info chip_info[] = { {"RTL-8168b/8111sb", 0x38, 0xff7e1880}, {"RTL-8168d/8111d", 0x28, 0xff7e1880}, {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880}, + {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, {"RTL-8101e", 0x34, 0xff7e1880}, {"RTL-8100e", 0x32, 0xff7e1880}, };
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 2/13 net: rtl8169: clean receive buffer after net handler
In reply to Lucas StachThe processing of the buffer might change some data, which will eventually trigger a cache writeback later on, corrupting data written by the network chip. Clean the cache range to make sure there is no writeback pending.
Signed-off-by Lucas Stach <[email protected]>
--- drivers/net/rtl8169.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
drivers/net/rtl8169.c +11 -0
@@ -233,6 +233,8 @@ static void rtl8169_init_ring(struct rtl8169_priv *priv) priv->rx_desc =dma_alloc_coherent (NUM_RX_DESC *sizeof (struct bufdesc )); priv->rx_buf =malloc (NUM_RX_DESC *PKT_BUF_SIZE ); +dma_clean_range ((unsigned long )priv->rx_buf, + (unsigned long )priv->rx_buf +NUM_RX_DESC *PKT_BUF_SIZE );memset (priv->tx_desc,0 ,NUM_TX_DESC *sizeof (struct bufdesc ));memset (priv->rx_desc,0 ,NUM_RX_DESC *sizeof (struct bufdesc ));
@@ -421,6 +423,15 @@ static int rtl8169_eth_rx(struct eth_device *edev)net_receive (edev, priv->rx_buf + entry *PKT_BUF_SIZE , pkt_size); +/* +* the buffer is going to be reused by HW, make sure to +* clean out any potentially modified data +*/ +dma_clean_range ((unsigned long )priv->rx_buf + + entry *PKT_BUF_SIZE , + (unsigned long )priv->rx_buf + + entry *PKT_BUF_SIZE + pkt_size); +if (entry ==NUM_RX_DESC -1 ) priv->rx_desc[entry].status =BD_STAT_OWN |BD_STAT_EOR |PKT_BUF_SIZE ;
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 3/13 tegra: defconfig: enable barebox OF drivers
In reply to Lucas StachWe use them to configure the environment location so it's a good idea to have them available by default.
Signed-off-by Lucas Stach <[email protected]>
--- arch/arm/configs/tegra_v7_defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm/configs/tegra_v7_defconfig +1 -0
@@ -38,6 +38,7 @@ CONFIG_CMD_DETECT=y CONFIG_CMD_GPIO=y CONFIG_CMD_OFTREE=y CONFIG_NET=y +CONFIG_OF_BAREBOX_DRIVERS=y CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_RTL8169=y CONFIG_MCI=y
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 4/13 pinctrl: tegra: try to select "boot" state
In reply to Lucas StachNew DTs call the initial pinctrl state "boot" in
order to avoid Linux reconfiguring the pinctrl
by default. The bootloader should explicitly set
this state.
Signed-off-by Lucas Stach <[email protected]>
--- drivers/pinctrl/pinctrl-tegra20.c | 8 ++++++-- drivers/pinctrl/pinctrl-tegra30.c | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-)
drivers/pinctrl/pinctrl-tegra20.c +6 -2
@@ -320,10 +320,14 @@ static int pinctrl_tegra20_probe(struct device_d *dev) ctrl->pinctrl.ops = &pinctrl_tegra20_ops; ret =pinctrl_register (&ctrl->pinctrl); -if (ret) +if (ret) {free (ctrl); +return ret; + } + +of_pinctrl_select_state (dev->device_node,"boot" ); -return ret; +return 0 ; }static __maybe_unused struct of_device_id pinctrl_tegra20_dt_ids[] = {
drivers/pinctrl/pinctrl-tegra30.c +6 -2
@@ -897,10 +897,14 @@ static int pinctrl_tegra30_probe(struct device_d *dev) ctrl->pinctrl.ops = &pinctrl_tegra30_ops; ret =pinctrl_register (&ctrl->pinctrl); -if (ret) +if (ret) {free (ctrl); +return ret; + } + +of_pinctrl_select_state (dev->device_node,"boot" ); -return ret; +return 0 ; }static __maybe_unused struct of_device_id pinctrl_tegra30_dt_ids[] = {
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 5/13 arm: dts: jetson-tk1: switch to upstream DT
In reply to Lucas StachAlmost everything is upstream now, so no need to
keep our private copy of the DT.
Signed-off-by Lucas Stach <[email protected]>
--- arch/arm/dts/tegra124-jetson-tk1.dts | 1823 +--------------------------------- 1 file changed, 1 insertion(+), 1822 deletions(-)
arch/arm/dts/tegra124-jetson-tk1.dts +1 -1822
@@ -1,17 +1,6 @@ -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include "tegra124.dtsi" +#include <arm/tegra124-jetson-tk1.dts> / { - model = "NVIDIA Tegra124 Jetson TK1"; - compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; - - aliases { - rtc0 = "/i2c@0,7000d000/pmic@40"; - rtc1 = "/rtc@0,7000e000"; - }; - chosen { environment@0 { compatible = "barebox,environment";
@@ -19,1817 +8,7 @@ }; }; - memory { - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - host1x@0,50000000 { - hdmi@0,54280000 { - status = "okay"; - - hdmi-supply = <&vdd_5v0_hdmi>; - pll-supply = <&vdd_hdmi_pll>; - vdd-supply = <&vdd_3v3_hdmi>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - }; - }; - - pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - clk_32k_out_pa0 { - nvidia,pins = "clk_32k_out_pa0"; - nvidia,function = "soc"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - uart3_cts_n_pa1 { - nvidia,pins = "uart3_cts_n_pa1"; - nvidia,function = "uartc"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap2_fs_pa2 { - nvidia,pins = "dap2_fs_pa2"; - nvidia,function = "i2s1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap2_sclk_pa3 { - nvidia,pins = "dap2_sclk_pa3"; - nvidia,function = "i2s1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4"; - nvidia,function = "i2s1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap2_dout_pa5 { - nvidia,pins = "dap2_dout_pa5"; - nvidia,function = "i2s1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_clk_pa6 { - nvidia,pins = "sdmmc3_clk_pa6"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - sdmmc3_cmd_pa7 { - nvidia,pins = "sdmmc3_cmd_pa7"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pb0 { - nvidia,pins = "pb0"; - nvidia,function = "uartd"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pb1 { - nvidia,pins = "pb1"; - nvidia,function = "uartd"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_dat3_pb4 { - nvidia,pins = "sdmmc3_dat3_pb4"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_dat2_pb5 { - nvidia,pins = "sdmmc3_dat2_pb5"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_dat1_pb6 { - nvidia,pins = "sdmmc3_dat1_pb6"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_dat0_pb7 { - nvidia,pins = "sdmmc3_dat0_pb7"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - uart3_rts_n_pc0 { - nvidia,pins = "uart3_rts_n_pc0"; - nvidia,function = "uartc"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - uart2_txd_pc2 { - nvidia,pins = "uart2_txd_pc2"; - nvidia,function = "irda"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3"; - nvidia,function = "irda"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gen1_i2c_scl_pc4 { - nvidia,pins = "gen1_i2c_scl_pc4"; - nvidia,function = "i2c1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - gen1_i2c_sda_pc5 { - nvidia,pins = "gen1_i2c_sda_pc5"; - nvidia,function = "i2c1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - pc7 { - nvidia,pins = "pc7"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pg0 { - nvidia,pins = "pg0"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pg1 { - nvidia,pins = "pg1"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pg2 { - nvidia,pins = "pg2"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pg3 { - nvidia,pins = "pg3"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pg4 { - nvidia,pins = "pg4"; - nvidia,function = "spi4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pg5 { - nvidia,pins = "pg5"; - nvidia,function = "spi4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pg6 { - nvidia,pins = "pg6"; - nvidia,function = "spi4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pg7 { - nvidia,pins = "pg7"; - nvidia,function = "spi4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ph1 { - nvidia,pins = "ph1"; - nvidia,function = "pwm1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ph3 { - nvidia,pins = "ph3"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ph4 { - nvidia,pins = "ph4"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ph5 { - nvidia,pins = "ph5"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ph6 { - nvidia,pins = "ph6"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ph7 { - nvidia,pins = "ph7"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pi0 { - nvidia,pins = "pi0"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pi1 { - nvidia,pins = "pi1"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pi2 { - nvidia,pins = "pi2"; - nvidia,function = "rsvd4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pi3 { - nvidia,pins = "pi3"; - nvidia,function = "spi4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pi4 { - nvidia,pins = "pi4"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pi5 { - nvidia,pins = "pi5"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pi7 { - nvidia,pins = "pi7"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pj0 { - nvidia,pins = "pj0"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pj2 { - nvidia,pins = "pj2"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5"; - nvidia,function = "uartb"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - uart2_rts_n_pj6 { - nvidia,pins = "uart2_rts_n_pj6"; - nvidia,function = "uartb"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pj7 { - nvidia,pins = "pj7"; - nvidia,function = "uartd"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pk0 { - nvidia,pins = "pk0"; - nvidia,function = "soc"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pk1 { - nvidia,pins = "pk1"; - nvidia,function = "rsvd4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pk2 { - nvidia,pins = "pk2"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pk3 { - nvidia,pins = "pk3"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pk4 { - nvidia,pins = "pk4"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - spdif_out_pk5 { - nvidia,pins = "spdif_out_pk5"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - spdif_in_pk6 { - nvidia,pins = "spdif_in_pk6"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pk7 { - nvidia,pins = "pk7"; - nvidia,function = "uartd"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap1_fs_pn0 { - nvidia,pins = "dap1_fs_pn0"; - nvidia,function = "i2s0"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1"; - nvidia,function = "i2s0"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap1_dout_pn2 { - nvidia,pins = "dap1_dout_pn2"; - nvidia,function = "sata"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap1_sclk_pn3 { - nvidia,pins = "dap1_sclk_pn3"; - nvidia,function = "i2s0"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; - nvidia,function = "usb"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - hdmi_int_pn7 { - nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - ulpi_data7_po0 { - nvidia,pins = "ulpi_data7_po0"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_data0_po1 { - nvidia,pins = "ulpi_data0_po1"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_data1_po2 { - nvidia,pins = "ulpi_data1_po2"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_data2_po3 { - nvidia,pins = "ulpi_data2_po3"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_data3_po4 { - nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_data5_po6 { - nvidia,pins = "ulpi_data5_po6"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ulpi_data6_po7 { - nvidia,pins = "ulpi_data6_po7"; - nvidia,function = "ulpi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap3_fs_pp0 { - nvidia,pins = "dap3_fs_pp0"; - nvidia,function = "i2s2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap3_din_pp1 { - nvidia,pins = "dap3_din_pp1"; - nvidia,function = "i2s2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap3_dout_pp2 { - nvidia,pins = "dap3_dout_pp2"; - nvidia,function = "rsvd4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap3_sclk_pp3 { - nvidia,pins = "dap3_sclk_pp3"; - nvidia,function = "rsvd3"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap4_fs_pp4 { - nvidia,pins = "dap4_fs_pp4"; - nvidia,function = "i2s3"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5"; - nvidia,function = "i2s3"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap4_dout_pp6 { - nvidia,pins = "dap4_dout_pp6"; - nvidia,function = "i2s3"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap4_sclk_pp7 { - nvidia,pins = "dap4_sclk_pp7"; - nvidia,function = "i2s3"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col0_pq0 { - nvidia,pins = "kb_col0_pq0"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col1_pq1 { - nvidia,pins = "kb_col1_pq1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col2_pq2 { - nvidia,pins = "kb_col2_pq2"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col3_pq3 { - nvidia,pins = "kb_col3_pq3"; - nvidia,function = "kbc"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_col4_pq4 { - nvidia,pins = "kb_col4_pq4"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col5_pq5 { - nvidia,pins = "kb_col5_pq5"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col6_pq6 { - nvidia,pins = "kb_col6_pq6"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_col7_pq7 { - nvidia,pins = "kb_col7_pq7"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row0_pr0 { - nvidia,pins = "kb_row0_pr0"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row1_pr1 { - nvidia,pins = "kb_row1_pr1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row2_pr2 { - nvidia,pins = "kb_row2_pr2"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row3_pr3 { - nvidia,pins = "kb_row3_pr3"; - nvidia,function = "sys"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row4_pr4 { - nvidia,pins = "kb_row4_pr4"; - nvidia,function = "rsvd3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row5_pr5 { - nvidia,pins = "kb_row5_pr5"; - nvidia,function = "rsvd3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row6_pr6 { - nvidia,pins = "kb_row6_pr6"; - nvidia,function = "displaya_alt"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row7_pr7 { - nvidia,pins = "kb_row7_pr7"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row8_ps0 { - nvidia,pins = "kb_row8_ps0"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row9_ps1 { - nvidia,pins = "kb_row9_ps1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row10_ps2 { - nvidia,pins = "kb_row10_ps2"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row11_ps3 { - nvidia,pins = "kb_row11_ps3"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row12_ps4 { - nvidia,pins = "kb_row12_ps4"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row13_ps5 { - nvidia,pins = "kb_row13_ps5"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row14_ps6 { - nvidia,pins = "kb_row14_ps6"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row15_ps7 { - nvidia,pins = "kb_row15_ps7"; - nvidia,function = "soc"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - kb_row16_pt0 { - nvidia,pins = "kb_row16_pt0"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - kb_row17_pt1 { - nvidia,pins = "kb_row17_pt1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - gen2_i2c_scl_pt5 { - nvidia,pins = "gen2_i2c_scl_pt5"; - nvidia,function = "i2c2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - gen2_i2c_sda_pt6 { - nvidia,pins = "gen2_i2c_sda_pt6"; - nvidia,function = "i2c2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_cmd_pt7 { - nvidia,pins = "sdmmc4_cmd_pt7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pu0 { - nvidia,pins = "pu0"; - nvidia,function = "rsvd4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pu1 { - nvidia,pins = "pu1"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pu2 { - nvidia,pins = "pu2"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pu3 { - nvidia,pins = "pu3"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pu4 { - nvidia,pins = "pu4"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pu5 { - nvidia,pins = "pu5"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pu6 { - nvidia,pins = "pu6"; - nvidia,function = "rsvd3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pv0 { - nvidia,pins = "pv0"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pv1 { - nvidia,pins = "pv1"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_cd_n_pv2 { - nvidia,pins = "sdmmc3_cd_n_pv2"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc1_wp_n_pv3 { - nvidia,pins = "sdmmc1_wp_n_pv3"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ddc_scl_pv4 { - nvidia,pins = "ddc_scl_pv4"; - nvidia,function = "i2c4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - ddc_sda_pv5 { - nvidia,pins = "ddc_sda_pv5"; - nvidia,function = "i2c4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - gpio_w2_aud_pw2 { - nvidia,pins = "gpio_w2_aud_pw2"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_w3_aud_pw3 { - nvidia,pins = "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dap_mclk1_pw4 { - nvidia,pins = "dap_mclk1_pw4"; - nvidia,function = "extperiph1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - clk2_out_pw5 { - nvidia,pins = "clk2_out_pw5"; - nvidia,function = "extperiph2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - uart3_txd_pw6 { - nvidia,pins = "uart3_txd_pw6"; - nvidia,function = "uartc"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - uart3_rxd_pw7 { - nvidia,pins = "uart3_rxd_pw7"; - nvidia,function = "uartc"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - gpio_x1_aud_px1 { - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; - nvidia,function = "cldvfs"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - gpio_x3_aud_px3 { - nvidia,pins = "gpio_x3_aud_px3"; - nvidia,function = "rsvd4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_x4_aud_px4 { - nvidia,pins = "gpio_x4_aud_px4"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - gpio_x5_aud_px5 { - nvidia,pins = "gpio_x5_aud_px5"; - nvidia,function = "rsvd4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_x6_aud_px6 { - nvidia,pins = "gpio_x6_aud_px6"; - nvidia,function = "gmi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - gpio_x7_aud_px7 { - nvidia,pins = "gpio_x7_aud_px7"; - nvidia,function = "rsvd1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ulpi_clk_py0 { - nvidia,pins = "ulpi_clk_py0"; - nvidia,function = "spi1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ulpi_dir_py1 { - nvidia,pins = "ulpi_dir_py1"; - nvidia,function = "spi1"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - ulpi_nxt_py2 { - nvidia,pins = "ulpi_nxt_py2"; - nvidia,function = "spi1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - ulpi_stp_py3 { - nvidia,pins = "ulpi_stp_py3"; - nvidia,function = "spi1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - sdmmc1_dat3_py4 { - nvidia,pins = "sdmmc1_dat3_py4"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc1_dat2_py5 { - nvidia,pins = "sdmmc1_dat2_py5"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc1_dat1_py6 { - nvidia,pins = "sdmmc1_dat1_py6"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc1_dat0_py7 { - nvidia,pins = "sdmmc1_dat0_py7"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc1_clk_pz0 { - nvidia,pins = "sdmmc1_clk_pz0"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc1_cmd_pz1 { - nvidia,pins = "sdmmc1_cmd_pz1"; - nvidia,function = "sdmmc1"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pwr_i2c_scl_pz6 { - nvidia,pins = "pwr_i2c_scl_pz6"; - nvidia,function = "i2cpwr"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - pwr_i2c_sda_pz7 { - nvidia,pins = "pwr_i2c_sda_pz7"; - nvidia,function = "i2cpwr"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat1_paa1 { - nvidia,pins = "sdmmc4_dat1_paa1"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat2_paa2 { - nvidia,pins = "sdmmc4_dat2_paa2"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat3_paa3 { - nvidia,pins = "sdmmc4_dat3_paa3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat4_paa4 { - nvidia,pins = "sdmmc4_dat4_paa4"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat5_paa5 { - nvidia,pins = "sdmmc4_dat5_paa5"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat6_paa6 { - nvidia,pins = "sdmmc4_dat6_paa6"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_dat7_paa7 { - nvidia,pins = "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pbb0 { - nvidia,pins = "pbb0"; - nvidia,function = "vimclk2_alt"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - cam_i2c_scl_pbb1 { - nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "i2c3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - cam_i2c_sda_pbb2 { - nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "i2c3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - pbb3 { - nvidia,pins = "pbb3"; - nvidia,function = "vgp3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pbb4 { - nvidia,pins = "pbb4"; - nvidia,function = "vgp4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pbb5 { - nvidia,pins = "pbb5"; - nvidia,function = "rsvd3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pbb6 { - nvidia,pins = "pbb6"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pbb7 { - nvidia,pins = "pbb7"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - cam_mclk_pcc0 { - nvidia,pins = "cam_mclk_pcc0"; - nvidia,function = "vi_alt3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pcc1 { - nvidia,pins = "pcc1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - pcc2 { - nvidia,pins = "pcc2"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4"; - nvidia,function = "sdmmc4"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - clk2_req_pcc5 { - nvidia,pins = "clk2_req_pcc5"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - clk3_out_pee0 { - nvidia,pins = "clk3_out_pee0"; - nvidia,function = "extperiph3"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - clk3_req_pee1 { - nvidia,pins = "clk3_req_pee1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - dap_mclk1_req_pee2 { - nvidia,pins = "dap_mclk1_req_pee2"; - nvidia,function = "sata"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - hdmi_cec_pee3 { - nvidia,pins = "hdmi_cec_pee3"; - nvidia,function = "cec"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_clk_lb_out_pee4 { - nvidia,pins = "sdmmc3_clk_lb_out_pee4"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - sdmmc3_clk_lb_in_pee5 { - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; - nvidia,function = "sdmmc3"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; - nvidia,function = "dp"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - usb_vbus_en2_pff1 { - nvidia,pins = "usb_vbus_en2_pff1"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - pff2 { - nvidia,pins = "pff2"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,open-drain = <TEGRA_PIN_DISABLE>; - }; - core_pwr_req { - nvidia,pins = "core_pwr_req"; - nvidia,function = "pwron"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - cpu_pwr_req { - nvidia,pins = "cpu_pwr_req"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - pwr_int_n { - nvidia,pins = "pwr_int_n"; - nvidia,function = "pmi"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - reset_out_n { - nvidia,pins = "reset_out_n"; - nvidia,function = "reset_out_n"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_DOWN>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; - }; - clk_32k_in { - nvidia,pins = "clk_32k_in"; - nvidia,function = "rsvd2"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - jtag_rtck { - nvidia,pins = "jtag_rtck"; - nvidia,function = "rtck"; - nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - }; - }; - - /* DB9 serial port */ - serial@0,70006300 { - status = "okay"; - }; - - /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ - i2c@0,7000c000 { - status = "okay"; - clock-frequency = <100000>; - - rt5639: audio-codec@1c { - compatible = "realtek,rt5639"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; - realtek,ldo1-en-gpios = - <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; - }; - - eeprom@56 { - compatible = "atmel,24c02"; - reg = <0x56>; - pagesize = <8>; - }; - }; - - /* Expansion GEN2_I2C_* */ - i2c@0,7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion CAM_I2C_* */ - i2c@0,7000c500 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* HDMI DDC */ - hdmi_ddc: i2c@0,7000c700 { - status = "okay"; - clock-frequency = <100000>; - }; - - /* Expansion PWR_I2C_*, on-board components */ - i2c@0,7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@40 { - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - - ams,system-power-controller; - - #interrupt-cells = <2>; - interrupt-controller; - - gpio-controller; - #gpio-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - - as3722_default: pinmux { - gpio0 { - pins = "gpio0"; - function = "gpio"; - bias-pull-down; - }; - - gpio1_2_4_7 { - pins = "gpio1", "gpio2", "gpio4", "gpio7"; - function = "gpio"; - bias-pull-up; - }; - - gpio3_5_6 { - pins = "gpio3", "gpio5", "gpio6"; - bias-high-impedance; - }; - }; - - regulators { - vsup-sd2-supply = <&vdd_5v0_sys>; - vsup-sd3-supply = <&vdd_5v0_sys>; - vsup-sd4-supply = <&vdd_5v0_sys>; - vsup-sd5-supply = <&vdd_5v0_sys>; - vin-ldo0-supply = <&vdd_1v35_lp0>; - vin-ldo1-6-supply = <&vdd_3v3_run>; - vin-ldo2-5-7-supply = <&vddio_1v8>; - vin-ldo3-4-supply = <&vdd_3v3_sys>; - vin-ldo9-10-supply = <&vdd_5v0_sys>; - vin-ldo11-supply = <&vdd_3v3_run>; - - sd0 { - regulator-name = "+VDD_CPU_AP"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-always-on; - regulator-boot-on; - ams,external-control = <2>; - }; - - sd1 { - regulator-name = "+VDD_CORE"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-min-microamp = <2500000>; - regulator-max-microamp = <2500000>; - regulator-always-on; - regulator-boot-on; - ams,external-control = <1>; - }; - - vdd_1v35_lp0: sd2 { - regulator-name = "+1.35V_LP0(sd2)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - sd3 { - regulator-name = "+1.35V_LP0(sd3)"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_1v05_run: sd4 { - regulator-name = "+1.05V_RUN"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - vddio_1v8: sd5 { - regulator-name = "+1.8V_VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sd6 { - regulator-name = "+VDD_GPU_AP"; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3500000>; - regulator-max-microamp = <3500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo0 { - regulator-name = "+1.05V_RUN_AVDD"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; - ams,external-control = <1>; - }; - - ldo1 { - regulator-name = "+1.8V_RUN_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo2 { - regulator-name = "+1.2V_GEN_AVDD"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3 { - regulator-name = "+1.05V_LP0_VDD_RTC"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - ams,enable-tracking; - }; - - ldo4 { - regulator-name = "+2.8V_RUN_CAM"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5 { - regulator-name = "+1.2V_RUN_CAM_FRONT"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vddio_sdmmc3: ldo6 { - regulator-name = "+VDDIO_SDMMC3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "+1.05V_RUN_CAM_REAR"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - ldo9 { - regulator-name = "+3.3V_RUN_TOUCH"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo10 { - regulator-name = "+2.8V_RUN_CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo11 { - regulator-name = "+1.8V_RUN_VPP_FUSE"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - }; - - /* Expansion TS_SPI_* */ - spi@0,7000d400 { - status = "okay"; - }; - - /* Internal SPI */ - spi@0,7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - spi-flash@0 { - compatible = "winbond,w25q32dw"; - reg = <0>; - spi-max-frequency = <20000000>; - }; - }; - - pmc@0,7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <500>; - nvidia,cpu-pwr-off-time = <300>; - nvidia,core-pwr-good-time = <641 3845>; - nvidia,core-pwr-off-time = <61036>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - }; - - /* SD card */ - sdhci@0,700b0400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; - /* eMMC */ emmc: sdhci@0,700b0600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - ahub@0,70300000 { - i2s@0,70301100 { - status = "okay"; - }; - }; - - /* mini-PCIe USB */ - usb@0,7d004000 { - status = "okay"; - }; - - usb-phy@0,7d004000 { - status = "okay"; - }; - - /* USB A connector */ - usb@0,7d008000 { - status = "okay"; - }; - - usb-phy@0,7d008000 { - status = "okay"; - vbus-supply = <&vdd_usb3_vbus>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - gpio-key,wakeup; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_mux: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "+VDD_MUX"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_5v0_sys: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "+5V_SYS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_sys: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "+3.3V_SYS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vdd_mux>; - }; - - vdd_3v3_run: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "+3.3V_RUN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_3v3_hdmi: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_3v3_run>; - }; - - vdd_usb1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "+USB0_VBUS_SW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_usb3_vbus: regulator@8 { - compatible = "regulator-fixed"; - reg = <8>; - regulator-name = "+5V_USB_HS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - gpio-open-drain; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_3v3_lp0: regulator@10 { - compatible = "regulator-fixed"; - reg = <10>; - regulator-name = "+3.3V_LP0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_3v3_sys>; - }; - - vdd_hdmi_pll: regulator@11 { - compatible = "regulator-fixed"; - reg = <11>; - regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; - vin-supply = <&vdd_1v05_run>; - }; - - vdd_5v0_hdmi: regulator@12 { - compatible = "regulator-fixed"; - reg = <12>; - regulator-name = "+5V_HDMI_CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - }; - - sound { - compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", - "nvidia,tegra-audio-rt5640"; - nvidia,model = "NVIDIA Tegra Jetson TK1"; - - nvidia,audio-routing = - "Headphones", "HPOR", - "Headphones", "HPOL", - "Mic Jack", "MICBIAS1", - "IN2P", "Mic Jack"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5639>; - - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; - - clocks = <&tegra_car TEGRA124_CLK_PLL_A>, - <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA124_CLK_EXTERN1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; }; };
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 6/13 clk: tegra: slow down MSELECT to 102MHz
In reply to Lucas StachDon't know where I got the 204MHZ previously, but
102MHz is the official supported maximum.
Signed-off-by Lucas Stach <[email protected]>
---
Overclocking MSELECT by 100% seems to lead to
PCIe failures. Much more on T124 than on T30.
--- drivers/clk/tegra/clk-tegra124.c | 2 +- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
drivers/clk/tegra/clk-tegra124.c +1 -1
@@ -286,7 +286,7 @@ static struct tegra_clk_init_table init_table[] = { {TEGRA124_CLK_PLL_P_OUT2, TEGRA124_CLK_CLK_MAX, 48000000, 1}, {TEGRA124_CLK_PLL_P_OUT3, TEGRA124_CLK_CLK_MAX, 102000000, 1}, {TEGRA124_CLK_PLL_P_OUT4, TEGRA124_CLK_CLK_MAX, 204000000, 1}, - {TEGRA124_CLK_MSELECT, TEGRA124_CLK_PLL_P, 204000000, 1}, + {TEGRA124_CLK_MSELECT, TEGRA124_CLK_PLL_P, 102000000, 1}, {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 0, 1}, {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 0, 1}, {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 0, 1},
drivers/clk/tegra/clk-tegra30.c +1 -1
@@ -351,7 +351,7 @@ static struct tegra_clk_init_table init_table[] = { {TEGRA30_CLK_PLL_P_OUT2, TEGRA30_CLK_CLK_MAX, 48000000, 1}, {TEGRA30_CLK_PLL_P_OUT3, TEGRA30_CLK_CLK_MAX, 102000000, 1}, {TEGRA30_CLK_PLL_P_OUT4, TEGRA30_CLK_CLK_MAX, 204000000, 1}, - {TEGRA30_CLK_MSELECT, TEGRA30_CLK_PLL_P, 204000000, 1}, + {TEGRA30_CLK_MSELECT, TEGRA30_CLK_PLL_P, 102000000, 1}, {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 0, 1}, {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 0, 1}, {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 0, 1},
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 7/13 tegra: pmc: work around power domain failure
In reply to Lucas StachSometimes a power domain didn't properly power up, reading back the command register seems to fix this by flushing the write.
Signed-off-by Lucas Stach <[email protected]>
--- arch/arm/mach-tegra/tegra20-pmc.c | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/mach-tegra/tegra20-pmc.c +2 -0
@@ -55,6 +55,8 @@ static int tegra_powergate_set(int id, bool new_state) }writel (PMC_PWRGATE_TOGGLE_START | id, pmc_base +PMC_PWRGATE_TOGGLE ); +/* I don't know exactly why this is needed, seems to flush the write */ +readl (pmc_base +PMC_PWRGATE_TOGGLE );return 0 ; }
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PATCH 8/13 tegra: jetson-tk1: enable 1.05V_RUN
In reply to Lucas StachNeeded for the PCIe PLL amongst other things.
Signed-off-by Lucas Stach <[email protected]>
--- arch/arm/boards/nvidia-jetson-tk1/Makefile | 2 +- arch/arm/boards/nvidia-jetson-tk1/board.c | 50 ++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boards/nvidia-jetson-tk1/board.c
arch/arm/boards/nvidia-jetson-tk1/Makefile +1 -1
@@ -3,5 +3,5 @@ CFLAGS_pbl-entry.o := \ -fno-tree-switch-conversion -fno-jump-tables soc := tegra124 lwl-y += entry.o -#obj-y += board.o +obj-y += board.o extra-y += jetson-tk1-2gb-emmc.bct
arch/arm/boards/nvidia-jetson-tk1/board.c new file +50 -0
50 lines not on this page · raw message
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PATCH 9/13 clk: tegra124: add PLLE setup functions
In reply to Lucas StachThis adds functions to bring up the new style
Tegra114+ PLL_E.
Signed-off-by Lucas Stach <[email protected]>
--- drivers/clk/tegra/clk-pll.c | 173 +++++++++++++++++++++++++++++++++++++++++++- drivers/clk/tegra/clk.h | 7 ++ 2 files changed, 177 insertions(+), 3 deletions(-)
drivers/clk/tegra/clk-pll.c +170 -3
@@ -63,6 +63,7 @@#define PLLDU_LFCON_SET_DIVN 600#define PLLE_BASE_DIVCML_SHIFT 24 +#define PLLE_BASE_DIVCML_MASK 0xf#define PLLE_BASE_DIVCML_WIDTH 4#define PLLE_BASE_DIVP_SHIFT 16#define PLLE_BASE_DIVP_WIDTH 7
@@ -81,8 +82,45 @@ PLLE_MISC_SETUP_EX_MASK)#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) -#define PLLE_SS_CTRL 0x68 -#define PLLE_SS_DISABLE (7 << 10) +#define XUSBIO_PLL_CFG0 0x51c +#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) +#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) +#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) +#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) +#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25) + +#define PLLE_SS_CTRL 0x68 +#define PLLE_SS_CNTL_BYPASS_SS (7 << 10) +#define PLLE_SS_CNTL_INTERP_RESET (1 << 11) +#define PLLE_SS_CNTL_SSC_BYP (1 << 12) +#define PLLE_SS_CNTL_CENTER (1 << 14) +#define PLLE_SS_CNTL_INVERT (1 << 15) +#define PLLE_SS_MAX_MASK 0x1ff +#define PLLE_SS_MAX_VAL 0x25 +#define PLLE_SS_INC_MASK (0xff << 16) +#define PLLE_SS_INC_VAL (0x1 << 16) +#define PLLE_SS_INCINTRV_MASK (0x3f << 24) +#define PLLE_SS_INCINTRV_VAL (0x20 << 24) +#define PLLE_SS_COEFFICIENTS_MASK \ + (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) +#define PLLE_SS_COEFFICIENTS_VAL \ + (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) + +#define PLLE_MISC_VREG_CTRL_SHIFT 2 +#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) +#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 +#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) +#define PLLE_MISC_PLLE_PTS (1 << 8) +#define PLLE_MISC_IDDQ_SW_VALUE (1 << 13) +#define PLLE_MISC_IDDQ_SW_CTRL (1 << 14) + +#define PLLE_AUX_PLLP_SEL (1 << 2) +#define PLLE_AUX_USE_LOCKDET (1 << 3) +#define PLLE_AUX_ENABLE_SWCTL (1 << 4) +#define PLLE_AUX_SS_SWCTL (1 << 6) +#define PLLE_AUX_SEQ_ENABLE (1 << 24) +#define PLLE_AUX_SEQ_START_STATE (1 << 25) +#define PLLE_AUX_PLLRE_SEL (1 << 28)#define PMC_SATA_PWRGT 0x1ac#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
@@ -102,10 +140,19 @@#define divp_mask (p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \ mask(p->divp_width)) +#define divm_shift (p) (p)->divm_shift +#define divn_shift (p) (p)->divn_shift +#define divp_shift (p) (p)->divp_shift + +#define divm_mask_shifted (p) (divm_mask(p) << divm_shift(p)) +#define divn_mask_shifted (p) (divn_mask(p) << divn_shift(p)) +#define divp_mask_shifted (p) (divp_mask(p) << divp_shift(p)) +#define divm_max (p) (divm_mask(p))#define divn_max (p) (divn_mask(p))#define divp_max (p) (1 << (divp_mask(p))) +#define to_clk_pll (_hw) container_of(_hw, struct tegra_clk_pll, hw)static int clk_pll_is_enabled (struct clk *hw)
@@ -478,7 +525,7 @@ static int clk_plle_enable(struct clk *hw)pll_writel_misc (val, pll); val =readl (pll->clk_base +PLLE_SS_CTRL ); - val |=PLLE_SS_DISABLE ; + val |=PLLE_SS_CNTL_BYPASS_SS ;writel (val, pll->clk_base +PLLE_SS_CTRL ); val =pll_readl_base (pll);
@@ -498,6 +545,115 @@ const struct clk_ops tegra_clk_plle_ops = { .enable = clk_plle_enable, }; +static int clk_plle_tegra114_enable (struct clk *hw) +{ +struct tegra_clk_pll *pll =to_clk_pll (hw); +unsigned long input_rate =clk_get_rate (clk_get_parent (hw)); +struct tegra_clk_pll_freq_table sel; +u32 val; +int ret; + +if (_get_table_rate (hw, &sel, pll->fixed_rate, input_rate)) +return -EINVAL ; + + val =pll_readl_base (pll); + val &= ~BIT (29 );/* Disable lock override */ +pll_writel_base (val, pll); + + val =pll_readl (pll->params->aux_reg, pll); + val |=PLLE_AUX_ENABLE_SWCTL ; + val &= ~PLLE_AUX_SEQ_ENABLE ; +pll_writel (val, pll->params->aux_reg, pll); +udelay (1 ); + + val =pll_readl_misc (pll); + val |=PLLE_MISC_LOCK_ENABLE ; + val |=PLLE_MISC_IDDQ_SW_CTRL ; + val &= ~PLLE_MISC_IDDQ_SW_VALUE ; + val |=PLLE_MISC_PLLE_PTS ; + val |=PLLE_MISC_VREG_BG_CTRL_MASK |PLLE_MISC_VREG_CTRL_MASK ; +pll_writel_misc (val, pll); +udelay (5 ); + + val =pll_readl (PLLE_SS_CTRL , pll); + val |=PLLE_SS_CNTL_BYPASS_SS ; +pll_writel (val,PLLE_SS_CTRL , pll); + + val =pll_readl_base (pll); + val &= ~(divp_mask_shifted (pll) |divn_mask_shifted (pll) | +divm_mask_shifted (pll)); + val &= ~(PLLE_BASE_DIVCML_MASK <<PLLE_BASE_DIVCML_SHIFT ); + val |= sel.m <<divm_shift (pll); + val |= sel.n <<divn_shift (pll); + val |= sel.cpcon <<PLLE_BASE_DIVCML_SHIFT ; +pll_writel_base (val, pll); +udelay (1 ); + +clk_pll_enable (hw); + ret =clk_pll_wait_for_lock (pll, pll->clk_base + pll->params->misc_reg, + pll->params->lock_bit_idx); + +if (ret <0 ) +return ret; + + val =pll_readl (PLLE_SS_CTRL , pll); + val &= ~(PLLE_SS_CNTL_CENTER |PLLE_SS_CNTL_INVERT ); + val &= ~PLLE_SS_COEFFICIENTS_MASK ; + val |=PLLE_SS_COEFFICIENTS_VAL ; +pll_writel (val,PLLE_SS_CTRL , pll); + val &= ~(PLLE_SS_CNTL_SSC_BYP |PLLE_SS_CNTL_BYPASS_SS ); +pll_writel (val,PLLE_SS_CTRL , pll); +udelay (1 ); + val &= ~PLLE_SS_CNTL_INTERP_RESET ; +pll_writel (val,PLLE_SS_CTRL , pll); +udelay (1 ); + +/* Enable hw control of xusb brick pll */ + val =pll_readl_misc (pll); + val &= ~PLLE_MISC_IDDQ_SW_CTRL ; +pll_writel_misc (val, pll); + + val =pll_readl (pll->params->aux_reg, pll); + val |= (PLLE_AUX_USE_LOCKDET |PLLE_AUX_SEQ_START_STATE ); + val &= ~(PLLE_AUX_ENABLE_SWCTL |PLLE_AUX_SS_SWCTL ); +pll_writel (val, pll->params->aux_reg, pll); +udelay (1 ); + val |=PLLE_AUX_SEQ_ENABLE ; +pll_writel (val, pll->params->aux_reg, pll); + + val =pll_readl (XUSBIO_PLL_CFG0 , pll); + val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | +XUSBIO_PLL_CFG0_SEQ_START_STATE ); + val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | +XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL ); +pll_writel (val,XUSBIO_PLL_CFG0 , pll); +udelay (1 ); + val |=XUSBIO_PLL_CFG0_SEQ_ENABLE ; +pll_writel (val,XUSBIO_PLL_CFG0 , pll); + +return ret; +} + +static void clk_plle_tegra114_disable (struct clk *hw) +{ +struct tegra_clk_pll *pll =to_clk_pll (hw); +u32 val; + +clk_pll_disable (hw); + + val =pll_readl_misc (pll); + val |=PLLE_MISC_IDDQ_SW_CTRL |PLLE_MISC_IDDQ_SW_VALUE ; +pll_writel_misc (val, pll); +udelay (1 ); +} + +const struct clk_ops tegra_clk_plle_tegra114_ops = { + .recalc_rate = clk_pll_recalc_rate, + .is_enabled = clk_pll_is_enabled, + .disable = clk_plle_tegra114_disable, + .enable = clk_plle_tegra114_enable, +}; + static struct clk *_tegra_clk_register_pll(const char *name, const char *parent_name, void __iomem *clk_base, unsigned long flags, unsigned long fixed_rate,
@@ -563,3 +719,14 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, flags, fixed_rate, pll_params, pll_flags, freq_table, &tegra_clk_plle_ops); } + +struct clk *tegra_clk_register_plle_tegra114 (const char *name, +const char *parent_name,void __iomem *clk_base, +unsigned long flags,unsigned long fixed_rate, +struct tegra_clk_pll_params *pll_params,u8 pll_flags, +struct tegra_clk_pll_freq_table *freq_table) +{ +return _tegra_clk_register_pll (name, parent_name, clk_base, + flags, fixed_rate, pll_params, pll_flags, freq_table, + &tegra_clk_plle_tegra114_ops); +}
drivers/clk/tegra/clk.h +7 -0
@@ -63,6 +63,7 @@ struct tegra_clk_pll_params {u32 base_reg;u32 misc_reg; +u32 aux_reg;u32 lock_reg;u8 lock_bit_idx;u8 lock_enable_bit_idx;
@@ -107,6 +108,12 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, struct tegra_clk_pll_params *pll_params, u8 pll_flags, struct tegra_clk_pll_freq_table *freq_table); +struct clk *tegra_clk_register_plle_tegra114 (const char *name, +const char *parent_name,void __iomem *clk_base, +unsigned long flags,unsigned long fixed_rate, +struct tegra_clk_pll_params *pll_params,u8 pll_flags, +struct tegra_clk_pll_freq_table *freq_table); +/* struct tegra_clk_pll_out - PLL output divider */ struct tegra_clk_pll_out {struct clk hw;
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 10/13 clk: tegra124: add PCIe clocks
In reply to Lucas StachSigned-off-by Lucas Stach <[email protected]>
--- drivers/clk/tegra/clk-tegra124.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
drivers/clk/tegra/clk-tegra124.c +35 -0
@@ -62,6 +62,15 @@ static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { { 0, 0, 0, 0, 0, 0 }, }; +static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { +/* PLLE special case: use cpcon field to store cml divider value */ + {336000000 ,100000000 ,100 ,21 ,16 ,11 }, + {312000000 ,100000000 ,200 ,26 ,24 ,13 }, + {13000000 ,100000000 ,200 ,1 ,26 ,13 }, + {12000000 ,100000000 ,200 ,1 ,24 ,13 }, + {0 ,0 ,0 ,0 ,0 ,0 }, +}; +static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { {12000000 ,408000000 ,408 ,12 ,0 ,8 }, {13000000, 408000000, 408, 13, 0, 8},
@@ -114,6 +123,21 @@ static struct tegra_clk_pll_params pll_c_params = { .lock_delay = 300, }; +static struct tegra_clk_pll_params pll_e_params = { + .input_min =12000000 , + .input_max =1000000000 , + .cf_min =12000000 , + .cf_max =75000000 , + .vco_min =1600000000 , + .vco_max =2400000000U , + .base_reg =CRC_PLLE_BASE , + .misc_reg =CRC_PLLE_MISC , + .aux_reg =CRC_PLLE_AUX , + .lock_bit_idx =CRC_PLLE_MISC_LOCK , + .lock_enable_bit_idx =CRC_PLLE_MISC_LOCK_ENABLE , + .lock_delay =300 , +}; +static struct tegra_clk_pll_params pll_p_params = { .input_min =2000000 , .input_max =31000000 ,
@@ -220,6 +244,11 @@ static void tegra124_pll_init(void) clks[TEGRA124_CLK_PLL_U ] =tegra_clk_register_pll ("pll_u" ,"pll_ref" , car_base,0 ,0 , &pll_u_params,TEGRA_PLLU |TEGRA_PLL_HAS_CPCON , pll_u_freq_table); + +/* PLLE */ + clks[TEGRA124_CLK_PLL_E ] =tegra_clk_register_plle_tegra114 ("pll_e" , +"pll_ref" , car_base,0 ,100000000 , &pll_e_params, +TEGRA_PLL_FIXED |TEGRA_PLL_USE_LOCK , pll_e_freq_table); }static const char *mux_pllpcm_clkm[] = {"pll_p" ,"pll_c2" ,"pll_c" ,"pll_c3" ,
@@ -244,6 +273,12 @@ static void tegra124_periph_init(void) mux_pllpcm_clkm,ARRAY_SIZE (mux_pllpcm_clkm), car_base,CRC_CLK_SOURCE_UARTD ,TEGRA124_CLK_UARTD , TEGRA_PERIPH_ON_APB); + clks[TEGRA124_CLK_PCIE ] =clk_gate ("pcie" ,"clk_m" , + car_base +CRC_CLK_OUT_ENB_U ,6 ,0 ,0 ); + clks[TEGRA124_CLK_AFI ] =clk_gate ("afi" ,"clk_m" , + car_base +CRC_CLK_OUT_ENB_U ,8 ,0 ,0 ); + clks[TEGRA124_CLK_CML0 ] =clk_gate ("cml0" ,"pll_e" , + car_base +CRC_PLLE_AUX ,0 ,0 ,0 );/* peripheral clocks with a divider */ clks[TEGRA124_CLK_MSELECT] = tegra_clk_register_periph("mselect",
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1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 11/13 add generic PHY framework
In reply to Lucas StachThis brings in the generix PHY framework from Linux. I tried to strip it down as much as possible while keeping it useful.
Signed-off-by Lucas Stach <[email protected]>
--- drivers/Kconfig | 1 + drivers/Makefile | 1 + drivers/phy/Kconfig | 18 +++ drivers/phy/Makefile | 5 + drivers/phy/phy-core.c | 318 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/phy/phy.h | 240 ++++++++++++++++++++++++++++++++++++ 6 files changed, 583 insertions(+) create mode 100644 drivers/phy/Kconfig create mode 100644 drivers/phy/Makefile create mode 100644 drivers/phy/phy-core.c create mode 100644 include/linux/phy/phy.h
drivers/Kconfig +1 -0
@@ -30,5 +30,6 @@ source "drivers/reset/Kconfig" source "drivers/pci/Kconfig" source "drivers/rtc/Kconfig" source "drivers/firmware/Kconfig" +source "drivers/phy/Kconfig" endmenu
drivers/Makefile +1 -0
@@ -29,3 +29,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += reset/ obj-$(CONFIG_PCI) += pci/ obj-y += rtc/ obj-$(CONFIG_FIRMWARE) += firmware/ +obj-$(CONFIG_GENERIC_PHY) += phy/
drivers/phy/Kconfig new file +18 -0
@@ -0,0 +1,18 @@ +# +# PHY +# + +menu "PHY Subsystem" + +config GENERIC_PHY + bool "PHY Core" + help + Generic PHY support. + + This framework is designed to provide a generic interface for PHY + devices present in the kernel. This layer will have the generic + API by which phy drivers can create PHY using the phy framework and + phy users can obtain reference to the PHY. All the users of this + framework should select this config. + +endmenu
drivers/phy/Makefile new file +5 -0
@@ -0,0 +1,5 @@ +# +# Makefile for the phy drivers. +# + +obj-$(CONFIG_GENERIC_PHY) += phy-core.o
drivers/phy/phy-core.c new file +318 -0
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include/linux/phy/phy.h new file +240 -0
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PATCH 12/13 pinctrl: tegra: add XUSB pad controller
In reply to Lucas StachThis is a combined pincontrol/PHY driver for
the SerDes lanes on Tegra K1.
Signed-off-by Lucas Stach <[email protected]>
--- drivers/pinctrl/Kconfig | 8 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-tegra-xusb.c | 519 +++++++++++++++++++++++++++++++++++ 3 files changed, 528 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-tegra-xusb.c
drivers/pinctrl/Kconfig +8 -0
@@ -60,6 +60,14 @@ config PINCTRL_TEGRA30 help The pinmux controller found on the Tegra 30+ line of SoCs. +config PINCTRL_TEGRA_XUSB + bool + default y if ARCH_TEGRA_124_SOC + select GENERIC_PHY + help + The pinmux controller found on the Tegra 124 line of SoCs used for + the SerDes lanes. + source drivers/pinctrl/mvebu/Kconfig endif
drivers/pinctrl/Makefile +1 -0
@@ -7,5 +7,6 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o +obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o obj-$(CONFIG_ARCH_MVEBU) += mvebu/
drivers/pinctrl/pinctrl-tegra-xusb.c new file +519 -0
519 lines not on this page · raw message
Signature · 7 lines
1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
PATCH 13/13 pci: tegra: add tegra124 support
In reply to Lucas StachSigned-off-by Lucas Stach <[email protected]>
--- drivers/pci/pci-tegra.c | 156 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 134 insertions(+), 22 deletions(-)
drivers/pci/pci-tegra.c +134 -22
@@ -30,6 +30,7 @@#include <of_address.h> #include <of_pci.h> #include <linux/pci.h> +#include <linux/phy/phy.h> #include <linux/reset.h> #include <sizes.h> #include <mach/tegra-powergate.h>
@@ -133,8 +134,10 @@#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)#define AFI_FUSE 0x104
@@ -146,12 +149,21 @@#define AFI_PEX_CTRL_RST (1 << 0)#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)#define AFI_PEX_CTRL_REFCLK_EN (1 << 3) +#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) + +#define AFI_PLLE_CONTROL 0x160 +#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) +#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)#define AFI_PEXBIAS_CTRL_0 0x168#define RP_VEND_XP 0x00000F00#define RP_VEND_XP_DL_UP (1 << 30) +#define RP_PRIV_MISC 0x00000FE0 +#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) +#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) +#define RP_LINK_CONTROL_STATUS 0x00000090#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
@@ -209,6 +221,7 @@ struct tegra_pcie_soc_data {bool has_intr_prsnt_sense;bool has_avdd_supply;bool has_cml_clk; +bool has_gen2; };struct tegra_pcie {
@@ -236,6 +249,8 @@ struct tegra_pcie {struct reset_control *afi_rst;struct reset_control *pcie_xrst; +struct phy *phy; +struct list_head ports;unsigned int num_ports;u32 xbar_config;
@@ -424,6 +439,8 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)if (soc->has_pex_clkreq_en) value |=AFI_PEX_CTRL_CLKREQ_EN ; + value |=AFI_PEX_CTRL_OVERRIDE_EN ; +afi_writel (port->pcie, value, ctrl);tegra_pcie_port_reset (port);
@@ -550,29 +567,10 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)afi_writel (pcie,0 ,AFI_MSI_BAR_SZ ); } -static int tegra_pcie_enable_controller (struct tegra_pcie *pcie) +static int tegra_pcie_phy_enable (struct tegra_pcie *pcie) {const struct tegra_pcie_soc_data *soc = pcie->soc_data; -struct tegra_pcie_port *port; -unsigned long value; - -/* power down PCIe slot clock bias pad */ -if (soc->has_pex_bias_ctrl) -afi_writel (pcie,0 ,AFI_PEXBIAS_CTRL_0 ); - -/* configure mode and disable all ports */ - value =afi_readl (pcie,AFI_PCIE_CONFIG ); - value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK ; - value |=AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; - -list_for_each_entry (port, &pcie->ports, list) - value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE (port->index); - -afi_writel (pcie, value,AFI_PCIE_CONFIG ); - - value =afi_readl (pcie,AFI_FUSE ); - value |=AFI_FUSE_PCIE_T0_GEN2_DIS ; -afi_writel (pcie, value,AFI_FUSE ); +u32 value;/* initialize internal PHY, enable up to 16 PCIE lanes */ pads_writel (pcie,0x0 ,PADS_CTL_SEL );
@@ -591,6 +589,13 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |=PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;pads_writel (pcie, value, soc->pads_pll_ctl); +/* reset PLL */ + value =pads_readl (pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM ; +pads_writel (pcie, value, soc->pads_pll_ctl); + +udelay (20 ); +/* take PLL out of reset */ value =pads_readl (pcie, soc->pads_pll_ctl); value |=PADS_PLL_CTL_RST_B4SM ;
@@ -619,6 +624,53 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |=PADS_CTL_TX_DATA_EN_1L |PADS_CTL_RX_DATA_EN_1L ;pads_writel (pcie, value,PADS_CTL ); +return 0 ; +} + +static int tegra_pcie_enable_controller (struct tegra_pcie *pcie) +{ +const struct tegra_pcie_soc_data *soc = pcie->soc_data; +struct tegra_pcie_port *port; +unsigned long value; +int err; + +/* enable PLL power down */ +if (pcie->phy) { + value =afi_readl (pcie,AFI_PLLE_CONTROL ); + value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL ; + value |=AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN ; +afi_writel (pcie, value,AFI_PLLE_CONTROL ); + } + +/* power down PCIe slot clock bias pad */ +if (soc->has_pex_bias_ctrl) +afi_writel (pcie,0 ,AFI_PEXBIAS_CTRL_0 ); + +/* configure mode and disable all ports */ + value =afi_readl (pcie,AFI_PCIE_CONFIG ); + value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK ; + value |=AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config; + +list_for_each_entry (port, &pcie->ports, list) + value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE (port->index); + +afi_writel (pcie, value,AFI_PCIE_CONFIG ); + +if (soc->has_gen2) { + value =afi_readl (pcie,AFI_FUSE ); + value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS ; +afi_writel (pcie, value,AFI_FUSE ); + }else { + value =afi_readl (pcie,AFI_FUSE ); + value |=AFI_FUSE_PCIE_T0_GEN2_DIS ; +afi_writel (pcie, value,AFI_FUSE ); + } + +if (!pcie->phy) + err =tegra_pcie_phy_enable (pcie); +else + err =phy_power_on (pcie->phy); +/* take the PCIe interface module out of reset */ reset_control_deassert (pcie->pcie_xrst);
@@ -653,6 +705,10 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)/* TODO: disable and unprepare clocks? */ + err =phy_power_off (pcie->phy); +if (err <0 ) +dev_warn (pcie->dev,"failed to power off PHY: %d\n" , err); +reset_control_assert (pcie->pcie_xrst);reset_control_assert (pcie->afi_rst);reset_control_assert (pcie->pex_rst);
@@ -806,6 +862,19 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)return err; } + pcie->phy =phy_optional_get (pcie->dev,"pcie" ); +if (IS_ERR (pcie->phy)) { + err =PTR_ERR (pcie->phy); +dev_err (dev,"failed to get PHY: %d\n" , err); +return err; + } + + err =phy_init (pcie->phy); +if (err <0 ) { +dev_err (dev,"failed to initialize PHY: %d\n" , err); +return err; + } + err =tegra_pcie_power_on (pcie);if (err) {dev_err (dev,"failed to power up: %d\n" , err);
@@ -840,7 +909,14 @@ poweroff:static int tegra_pcie_put_resources (struct tegra_pcie *pcie) { +int err; +tegra_pcie_power_off (pcie); + + err =phy_exit (pcie->phy); +if (err <0 ) +dev_err (pcie->dev,"failed to teardown PHY: %d\n" , err); +return 0 ; }
@@ -849,7 +925,19 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, {struct device_node *np = pcie->dev->device_node; -if (of_device_is_compatible (np,"nvidia,tegra30-pcie" )) { +if (of_device_is_compatible (np,"nvidia,tegra124-pcie" )) { +switch (lanes) { +case 0x0000104 : +dev_info (pcie->dev,"4x1, 1x1 configuration\n" ); + *xbar =AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 ; +return 0 ; + +case 0x0000102 : +dev_info (pcie->dev,"2x1, 1x1 configuration\n" ); + *xbar =AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 ; +return 0 ; + } + }else if (of_device_is_compatible (np,"nvidia,tegra30-pcie" )) {switch (lanes) {case 0x00000204 :dev_info (pcie->dev,"4x1, 2x1 configuration\n" );
@@ -1048,6 +1136,13 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port) { unsigned int timeout; unsigned int retries = 2; + u32 value; + + /* override presence detection */ + value = readl(port->base + RP_PRIV_MISC); + value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; + value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; + writel(value, port->base + RP_PRIV_MISC); do { timeout = wait_on_timeout(50 * MSECOND,
@@ -1113,6 +1208,7 @@ static const struct tegra_pcie_soc_data tegra20_pcie_data = { .has_intr_prsnt_sense = false, .has_avdd_supply = false, .has_cml_clk = false, + .has_gen2 = false, };static const struct tegra_pcie_soc_data tegra30_pcie_data = {
@@ -1125,10 +1221,26 @@ static const struct tegra_pcie_soc_data tegra30_pcie_data = { .has_intr_prsnt_sense = true, .has_avdd_supply = true, .has_cml_clk = true, + .has_gen2 = false, +}; + +static const struct tegra_pcie_soc_data tegra124_pcie_data = { + .num_ports =2 , + .msi_base_shift =8 , + .pads_pll_ctl =PADS_PLL_CTL_TEGRA30 , + .tx_ref_sel =PADS_PLL_CTL_TXCLKREF_BUF_EN , + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_intr_prsnt_sense = true, + .has_cml_clk = true, + .has_gen2 = true, };static __maybe_unused struct of_device_id tegra_pcie_of_match[] = { { + .compatible ="nvidia,tegra124-pcie" , + .data = (unsigned long )&tegra124_pcie_data + }, { .compatible ="nvidia,tegra30-pcie" , .data = (unsigned long )&tegra30_pcie_data }, {
Signature · 7 lines
1.9.3 _______________________________________________ barebox mailing list [email protected] http://lists.infradead.org/mailman/listinfo/barebox
Quoted 7 lines · Lucas Stach
This series implements PCIe on Tegra124 aka K1. With this applied the Jetson-TK1 platform is finally useable for proper development, as the network is working now.
The series is spun against -next, as it depends on the previous Tegra PCIe work found there. I hope Sascha can still squeeze this in before the next release.
Just squeezed this in ;)
Sascha
Signature · 9 lines
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