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usb: dwc3: core: enable phy suspend quirk on non-FPGA

PATCH New Felipe Balbi 2 participants 3 messages Nov 6, 2014 – Nov 10, 2014

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Felipe Balbi

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#0 lore raw

PATCH 1/2 usb: dwc3: core: enable phy suspend quirk on non-FPGA

as it turns out, at least AM437x silicon (non-FPGA) needs to enable PHY suspend quirk. So let's allow for PHY suspend quirk to be used with non-FPGA builds too.

Signed-off-by Felipe Balbi <[email protected]>
---
 drivers/usb/dwc3/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/usb/dwc3/core.c +2 -2
index 8ae42b8..25ddc39 100644
@@ -404,7 +404,7 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->tx_de_emphasis_quirk)
 		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 
-	if (dwc->dis_u3_susphy_quirk && dwc->is_fpga)
+	if (dwc->dis_u3_susphy_quirk)
 		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

@@ -422,7 +422,7 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->revision > DWC3_REVISION_194A)
 		reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 
-	if (dwc->dis_u2_susphy_quirk && dwc->is_fpga)
+	if (dwc->dis_u2_susphy_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
Signature · 1 line
2.1.0.GIT
author
#1 lore raw

PATCH 2/2 arm: boot: dts: am4372: enable dwc3 suspend PHY quirk

Whenever Suspend PHY bit is set on AM437x devices, USB will not work due to Set EP Configuration command always failing.

This was only found after a recent commit 2164a47 (usb:
dwc3: set SUSPHY bit for all cores, which will be merged for v3.19) added a missing *required* step to dwc3 initialization. Synopsys Databook requires that we enable Suspend PHY bit after initialization but that, unfortunately, breaks AM437x.

Signed-off-by Felipe Balbi <[email protected]>
---
 arch/arm/boot/dts/am4372.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/am4372.dtsi +4 -0
index 46660ff..e19068d 100644
@@ -817,6 +817,8 @@
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 				status = "disabled";
+				snps,dis_u3_susphy_quirk;
+				snps,dis_u2_susphy_quirk;
 			};
 		};
 

@@ -839,6 +841,8 @@
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 				status = "disabled";
+				snps,dis_u3_susphy_quirk;
+				snps,dis_u2_susphy_quirk;
 			};
 		};
Signature · 1 line
2.1.0.GIT
#2 lore raw

PATCH 2/2 arm: boot: dts: am4372: enable dwc3 suspend PHY quirk

Quoted 4 lines · Felipe Balbi

Whenever Suspend PHY bit is set on AM437x devices, USB will not work due to Set EP Configuration command always failing.

Quoted 8 lines

This was only found after a recent commit 2164a47 (usb:
dwc3: set SUSPHY bit for all cores, which will be merged for v3.19) added a missing *required* step to dwc3 initialization. Synopsys Databook requires that we enable Suspend PHY bit after initialization but that, unfortunately, breaks AM437x.

Signed-off-by Felipe Balbi <[email protected]>

This should be safe to queue along with the related USB changes:

Acked-by Tony Lindgren <[email protected]>
Quoted 35 lines
---
 arch/arm/boot/dts/am4372.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/boot/dts/am4372.dtsi +4 -0
index 46660ff..e19068d 100644
@@ -817,6 +817,8 @@
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 				status = "disabled";
+				snps,dis_u3_susphy_quirk;
+				snps,dis_u2_susphy_quirk;
 			};
 		};
 

@@ -839,6 +841,8 @@
 				maximum-speed = "high-speed";
 				dr_mode = "otg";
 				status = "disabled";
+				snps,dis_u3_susphy_quirk;
+				snps,dis_u2_susphy_quirk;
 			};
 		};
Signature · 7 lines
2.1.0.GIT


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