drm/i915: Add the predicate source registers to the register whitelist
Subsystems (2)
PATCH 1/1 drm/i915: Add the predicate source registers to the register whitelist
The predicate source registers are needed to implement conditional rendering without stalling. The two source registers are used to load the previous values of the PS_DEPTH_COUNT register saved from PIPE_CONTROL commands. These can then be compared and used to set the predicate enable bit via the MI_PREDICATE command.
---
There is a corresponding patch for Mesa which is using these registers on the mailing list here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/070347.html
There are some other registers such as MI_PREDICATE_DATA which can be used for more advanced predicate checking but I haven't added them to the list because they aren't needed to implement GL_NV_conditional_render.
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 4 insertions(+)
drivers/gpu/drm/i915/i915_cmd_parser.c +2 -0
@@ -408,6 +408,8 @@ static const u32 gen7_render_regs[] = {REG64 (PS_INVOCATION_COUNT ),REG64 (PS_DEPTH_COUNT ),OACONTROL ,/* Only allowed for LRI and SRM. See below. */ +REG64 (MI_PREDICATE_SRC0 ), +REG64 (MI_PREDICATE_SRC1 ),GEN7_3DPRIM_END_OFFSET ,GEN7_3DPRIM_START_VERTEX , GEN7_3DPRIM_VERTEX_COUNT,
drivers/gpu/drm/i915/i915_reg.h +2 -0
@@ -314,6 +314,8 @@#define MI_BATCH_GTT (2<<6)/* aliased with (1<<7) on gen4 */ #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) +#define MI_PREDICATE_SRC0 (0x2400) +#define MI_PREDICATE_SRC1 (0x2408)#define MI_PREDICATE_RESULT_2 (0x2214)#define LOWER_SLICE_ENABLED (1<<0)
Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 7 lines · Neil Roberts
The predicate source registers are needed to implement conditional rendering without stalling. The two source registers are used to load the previous values of the
PS_DEPTH_COUNTregister saved fromPIPE_CONTROLcommands. These can then be compared and used to set the predicate enable bit via theMI_PREDICATEcommand.Signed-off-by Neil Roberts <[email protected]>
Quoted 49 lines
---
There is a corresponding patch for Mesa which is using these registers on the mailing list here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/070347.html
There are some other registers such as
MI_PREDICATE_DATAwhich can be used for more advanced predicate checking but I haven't added them to the list because they aren't needed to implementGL_NV_conditional_render.drivers/gpu/drm/i915/i915_cmd_parser.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 4 insertions(+)drivers/gpu/drm/i915/i915_cmd_parser.c +2
-0@@ -408,6 +408,8 @@ static const u32 gen7_render_regs[] = {REG64 (PS_INVOCATION_COUNT ),REG64 (PS_DEPTH_COUNT ),OACONTROL ,/* Only allowed for LRI and SRM. See below. */ +REG64 (MI_PREDICATE_SRC0 ), +REG64 (MI_PREDICATE_SRC1 ),GEN7_3DPRIM_END_OFFSET ,GEN7_3DPRIM_START_VERTEX , GEN7_3DPRIM_VERTEX_COUNT,drivers/gpu/drm/i915/i915_reg.h +2
-0@@ -314,6 +314,8 @@#define MI_BATCH_GTT (2<<6)/* aliased with (1<<7) on gen4 */ #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) +#define MI_PREDICATE_SRC0 (0x2400) +#define MI_PREDICATE_SRC1 (0x2408)#define MI_PREDICATE_RESULT_2 (0x2214)#define LOWER_SLICE_ENABLED (1<<0)Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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PATCH v2 1/1 drm/i915: Add the predicate source registers to the register whitelist
In reply to Neil RobertsThe predicate source registers are needed to implement conditional rendering without stalling. The two source registers are used to load the previous values of the PS_DEPTH_COUNT register saved from PIPE_CONTROL commands. These can then be compared and used to set the predicate enable bit via the MI_PREDICATE command.
The command parser version number is increased to 2 to make it easier to detect the new functionality in user space.
---
Here is a v2 of the patch that also updates the command parser version to make it easier to detect whether we can use the register in Mesa. I have posted a second version of the Mesa patch which uses this here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/070362.html
This was suggested by Glenn Kennard.
drivers/gpu/drm/i915/i915_cmd_parser.c | 6 +++++- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/i915_cmd_parser.c +5 -1
@@ -408,6 +408,8 @@ static const u32 gen7_render_regs[] = {REG64 (PS_INVOCATION_COUNT ),REG64 (PS_DEPTH_COUNT ),OACONTROL ,/* Only allowed for LRI and SRM. See below. */ +REG64 (MI_PREDICATE_SRC0 ), +REG64 (MI_PREDICATE_SRC1 ),GEN7_3DPRIM_END_OFFSET ,GEN7_3DPRIM_START_VERTEX , GEN7_3DPRIM_VERTEX_COUNT,
@@ -1054,6 +1056,8 @@ int i915_cmd_parser_get_version(void)* * 1. Initial version. Checks batches and reports violations, but leaves * hardware parsing enabled (so does not allow new use cases). +* 2. Allow access to the MI_PREDICATE_SRC0 and +* MI_PREDICATE_SRC1 registers. */ -return 1 ; +return 2 ; }
drivers/gpu/drm/i915/i915_reg.h +2 -0
@@ -314,6 +314,8 @@#define MI_BATCH_GTT (2<<6)/* aliased with (1<<7) on gen4 */ #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) +#define MI_PREDICATE_SRC0 (0x2400) +#define MI_PREDICATE_SRC1 (0x2408)#define MI_PREDICATE_RESULT_2 (0x2214)#define LOWER_SLICE_ENABLED (1<<0)
Signature · 6 lines
1.9.3 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 12 lines · Neil Roberts
The predicate source registers are needed to implement conditional rendering without stalling. The two source registers are used to load the previous values of the
PS_DEPTH_COUNTregister saved fromPIPE_CONTROLcommands. These can then be compared and used to set the predicate enable bit via theMI_PREDICATEcommand.The command parser version number is increased to 2 to make it easier to detect the new functionality in user space.
Signed-off-by Neil Roberts <[email protected]>---
Quoted 7 lines
Here is a v2 of the patch that also updates the command parser version to make it easier to detect whether we can use the register in Mesa. I have posted a second version of the Mesa patch which uses this here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/070362.html
This was suggested by Glenn Kennard.
Ok, I've merged this one, since that means you at least won't get an -EINVAL. But you can't yet enable the feature in mesa since it's still no-opped out. Let's hope that v3 actually starts granting rights (but please don't encode that in any merge mesa patch before it's official in the kernel, Dave Airlie _will_ revert it even if it breaks the build) and that this happens soon.
-Daniel
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Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Hi,
Quoted 6 lines · Daniel Vetter
Ok, I've merged this one, since that means you at least won't get an
-EINVAL. But you can't yet enable the feature in mesa since it's still no-opped out. Let's hope that v3 actually starts granting rights (but please don't encode that in any merge mesa patch before it's official in the kernel, Dave Airlie _will_ revert it even if it breaks the build) and that this happens soon.
Thanks for merging the patch.
The current patch proposed for Mesa only enables the feature if the version is >= 2 *and* it can successfully do a pipeline write to some other register. Checking whether it can write to a register is already used to decide whether to enable some transform feedback extensions and indirect draw calls. I think in that case it should be safe to land the Mesa patches even though it would only work on IvyBridge and not Haswell or Gen8+. If we fix the kernel to allow the write for Haswell too then I think it would magically start working without any extra changes. I'm not really sure if I understand what you're saying about it being no-opped. It's effectively not no-opped on IvyBridge so I think we should already be able to enable the feature. Do you agree?
- Neil
Quoted 5 lines
-Daniel
Signature · 3 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Quoted 13 lines · Neil Roberts
Hi,
Quoted 6 lines · Daniel Vetter
Ok, I've merged this one, since that means you at least won't get an
-EINVAL. But you can't yet enable the feature in mesa since it's still no-opped out. Let's hope that v3 actually starts granting rights (but please don't encode that in any merge mesa patch before it's official in the kernel, Dave Airlie _will_ revert it even if it breaks the build) and that this happens soon.Thanks for merging the patch.
Quoted 11 lines
The current patch proposed for Mesa only enables the feature if the version is >= 2 *and* it can successfully do a pipeline write to some other register. Checking whether it can write to a register is already used to decide whether to enable some transform feedback extensions and indirect draw calls. I think in that case it should be safe to land the Mesa patches even though it would only work on IvyBridge and not Haswell or Gen8+. If we fix the kernel to allow the write for Haswell too then I think it would magically start working without any extra changes. I'm not really sure if I understand what you're saying about it being no-opped. It's effectively not no-opped on IvyBridge so I think we should already be able to enable the feature. Do you agree?
Makes sense, thanks for clarifying.
-Daniel
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 19 lines · Neil Roberts
The predicate source registers are needed to implement conditional rendering without stalling. The two source registers are used to load the previous values of the
PS_DEPTH_COUNTregister saved fromPIPE_CONTROLcommands. These can then be compared and used to set the predicate enable bit via theMI_PREDICATEcommand.Signed-off-by Neil Roberts <[email protected]>---
There is a corresponding patch for Mesa which is using these registers on the mailing list here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/070347.html
There are some other registers such as
MI_PREDICATE_DATAwhich can be used for more advanced predicate checking but I haven't added them to the list because they aren't needed to implementGL_NV_conditional_render.
Review
Quoted 5 lines
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 4 insertions(+)(quoted diff) +0
-0
b/drivers/gpu/drm/i915/i915_cmd_parser.c
Review
Quoted 13 lines
index 4c35e2a..9732155 100644
drivers/gpu/drm/i915/i915_cmd_parser.c +2
-0@@ -408,6 +408,8 @@ static const u32 gen7_render_regs[] = {REG64 (PS_INVOCATION_COUNT ),REG64 (PS_DEPTH_COUNT ),OACONTROL ,/* Only allowed for LRI and SRM. See below. */ +REG64 (MI_PREDICATE_SRC0 ), +REG64 (MI_PREDICATE_SRC1 ),GEN7_3DPRIM_END_OFFSET ,GEN7_3DPRIM_START_VERTEX , GEN7_3DPRIM_VERTEX_COUNT,(quoted diff) +0
-0
b/drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_reg.h line 321
Quoted 13 lines
index ea84e1e..9275d41 100644
drivers/gpu/drm/i915/i915_reg.h +2
-0@@ -314,6 +314,8 @@#define MI_BATCH_GTT (2<<6)/* aliased with (1<<7) on gen4 */ #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) +#define MI_PREDICATE_SRC0 (0x2400) +#define MI_PREDICATE_SRC1 (0x2408)#define MI_PREDICATE_RESULT_2 (0x2214)#define LOWER_SLICE_ENABLED (1<<0)
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