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*** iMX6 SabreSD SPL Support ***

PATCH Superseded John Tobias 3 participants 15 messages Nov 8, 2014 – Nov 10, 2014

Subsystems (3)
Arm (32-bit) Arm i.MX and Layerscape MMC, SD and SDIO

v2 of 7 Superseded Latest is v7 →

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John Tobias

author
#0 lore raw

v2 cover *** iMX6 SabreSD SPL Support ***

This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.

After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.

sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69

Changes:
Merged the SPL support into the main board file Remove the compilation warmings

John Tobias (8):
mmc: add spl_board_mmc_init
mmc: imx6: call spl_board_mmc_init
imx6: add spl on board configuration
imx6: add some flexibility for defining macros
imx6: add spl on board configuration
imx6: SPL support for iMX6 SabreSD
imx6: add data configuration file for SPL
kconfig: imx6: add SUPPORT_SPL

 arch/arm/Kconfig                              |   1 +
 board/freescale/mx6sabresd/mx6sabresd.c       | 216 ++++++++++++++++++++++++++
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg |  54 +++++++
 configs/mx6qsabresd_defconfig                 |   7 +-
 drivers/mmc/mmc.c                             |   5 +-
 include/configs/imx6_spl.h                    |   4 +
 include/configs/mx6sabresd.h                  |   7 +
 include/mmc.h                                 |   4 +-
 8 files changed, 293 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH v2 1/8 mmc: add spl_board_mmc_init

To avoid compilation warning it need to define it in the header file.

---
 include/mmc.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
include/mmc.h +3 -1
index d74a190..1d48bba 100644
@@ -388,7 +388,9 @@ int mmc_legacy_init(int verbose);
 int board_mmc_init(bd_t *bis);
 int cpu_mmc_init(bd_t *bis);
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
-
+#ifdef CONFIG_SPL
+int spl_board_mmc_init(bd_t *bis);
+#endif
 /* Set block count limit because of 16 bit register limit on some hardware*/
 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
Signature · 1 line
1.9.1
author
#2 lore raw

PATCH v2 2/8 mmc: imx6: call spl_board_mmc_init

In reply to John Tobias

Add to call spl_board_mmc_init when CONFIG_SPL_MMC_SUPPORT is defined, by default the mmc_initialize function will call board_mmc_init. But, the said function is not link to the spl image.

---
 drivers/mmc/mmc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/mmc/mmc.c +4 -1
index 44a4feb..d641c2a 100644
@@ -1441,10 +1441,13 @@ int mmc_initialize(bd_t *bis)
 	INIT_LIST_HEAD (&mmc_devices);
 	cur_dev_num = 0;
 
+#ifdef CONFIG_SPL_BUILD
+	if (spl_board_mmc_init(bis) < 0)
+		cpu_mmc_init(bis);
+#else
 	if (board_mmc_init(bis) < 0)
 		cpu_mmc_init(bis);
 
-#ifndef CONFIG_SPL_BUILD
 	print_mmc_devices(',');
 #endif
Signature · 1 line
1.9.1
author
#3 lore raw

PATCH v2 3/8 imx6: add spl on board configuration

In reply to John Tobias

add the spl on build configuration of iMX6 SabreSD

---
 include/configs/mx6sabresd.h | 7 +++++++
 1 file changed, 7 insertions(+)
include/configs/mx6sabresd.h +7 -0
index 938030d..4d2e54a 100644
@@ -12,6 +12,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
 
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_STACK 0x0093FFB8
+#include "imx6_spl.h"
+#endif
+
 #define CONFIG_MACH_TYPE	3980
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONFIG_CONSOLE_DEV		"ttymxc0"
Signature · 1 line
1.9.1
reviewer
#4 lore raw

PATCH v2 3/8 imx6: add spl on board configuration

Quoted 10 lines · John Tobias

add the spl on build configuration of iMX6 SabreSD

---
 include/configs/mx6sabresd.h | 7 +++++++
 1 file changed, 7 insertions(+)
include/configs/mx6sabresd.h +0 -0
index 938030d..4d2e54a 100644

include/configs/mx6sabresd.h line 20

Quoted 9 lines
include/configs/mx6sabresd.h +6 -0
@@ -12,6 +12,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
 
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_STACK 0x0093FFB8
+#include "imx6_spl.h"
+#endif

I am wondering if it would be better to create a separate target for the spl version, so that the people could still use the standard DCD approach as they are used to.

Regards,

Fabio Estevam

author
#5 lore raw

PATCH v2 3/8 imx6: add spl on board configuration

That's exactly that I am going to ask you. Because, some people in the community doesn't need the SPL.

I think this will need a separate config files (e.g mx6slevk_spl_defconfig, mx6qsabresd_spl_defconfig)

Regards,

john

Quoted 28 lines · Fabio Estevam
Quoted 10 lines · John Tobias

add the spl on build configuration of iMX6 SabreSD

---
 include/configs/mx6sabresd.h | 7 +++++++
 1 file changed, 7 insertions(+)
include/configs/mx6sabresd.h +0 -0
index 938030d..4d2e54a 100644

include/configs/mx6sabresd.h line 20

Quoted 9 lines
include/configs/mx6sabresd.h +6 -0
@@ -12,6 +12,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
 
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_STACK 0x0093FFB8
+#include "imx6_spl.h"
+#endif

I am wondering if it would be better to create a separate target for the spl version, so that the people could still use the standard DCD approach as they are used to.

Regards,

Fabio Estevam

reviewer
#6 lore raw

PATCH v2 3/8 imx6: add spl on board configuration

Quoted 5 lines · John Tobias

That's exactly that I am going to ask you. Because, some people in the community doesn't need the SPL.

I think this will need a separate config files (e.g mx6slevk_spl_defconfig, mx6qsabresd_spl_defconfig)

Yes, exacly, but I would prefere mx6sabresd_spl (without the 'q'), so that in the future we can support imx6q-sabresd and imx6dl-sabresd with a single binary using SPL.

Thanks,

Fabio Estevam

author
#7 lore raw

PATCH v2 3/8 imx6: add spl on board configuration

Oh okay, I'll do it again.

Regards,

John

Quoted 14 lines · Fabio Estevam
Quoted 5 lines · John Tobias

That's exactly that I am going to ask you. Because, some people in the community doesn't need the SPL.

I think this will need a separate config files (e.g mx6slevk_spl_defconfig, mx6qsabresd_spl_defconfig)

Yes, exacly, but I would prefere mx6sabresd_spl (without the 'q'), so that in the future we can support imx6q-sabresd and imx6dl-sabresd with a single binary using SPL.

Thanks,

Fabio Estevam

author
#8 lore raw

PATCH v2 4/8 imx6: add some flexibility for defining macros

In reply to John Tobias

iMX6 SabreSD has different stack address compare
to the default stack address defined on the file.

The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h which is same address defined on file. At the same time to avoid compilation warnings.

---
 include/configs/imx6_spl.h | 4 ++++
 1 file changed, 4 insertions(+)
include/configs/imx6_spl.h +4 -0
index 5a5f940..4ff37b3 100644
@@ -29,7 +29,9 @@
 #define CONFIG_SPL_TEXT_BASE		0x00908000
 #define CONFIG_SPL_MAX_SIZE		0x10000
 #define CONFIG_SPL_START_S_PATH		"arch/arm/cpu/armv7"
+#ifndef CONFIG_SPL_STACK
 #define CONFIG_SPL_STACK		0x0091FFB8
+#endif
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT

@@ -66,7 +68,9 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START	0x18300000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x3200000	/* 50 MB */
+#ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0x17800000
 #endif
+#endif
 
 #endif
Signature · 1 line
1.9.1
author
#9 lore raw

PATCH v2 5/8 imx6: add spl on board configuration

In reply to John Tobias

add the spl on build configuration of iMX6 SabreSD

---
 configs/mx6qsabresd_defconfig | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
configs/mx6qsabresd_defconfig +4 -3
index 67c1b77..14c80cc 100644
@@ -1,3 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
-CONFIG_ARM=y
-CONFIG_TARGET_MX6SABRESD=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_MX6SABRESD=y
Signature · 1 line
1.9.1
author
#10 lore raw

PATCH v2 6/8 imx6: SPL support for iMX6 SabreSD

In reply to John Tobias

This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port.

---
 board/freescale/mx6sabresd/mx6sabresd.c | 216 ++++++++++++++++++++++++++++++++
 1 file changed, 216 insertions(+)
board/freescale/mx6sabresd/mx6sabresd.c +216 -0
index 3d81fff..d090487 100644
@@ -607,3 +607,219 @@ int checkboard(void)
 	puts("Board: MX6-SabreSD\n");
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+#define BOOT_CFG	0x20D8004
+#define __REG(x)        (*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from mx6q_4x_mt41j128.cfg file
+ */
+void set_mt41j128_ddr(void)
+{
+	__REG(0x020e05a8) = 0x00000028;
+	__REG(0x020e05b0) = 0x00000028;
+	__REG(0x020e0524) = 0x00000028;
+	__REG(0x020e051c) = 0x00000028;
+
+	__REG(0x020e0518) = 0x00000028;
+	__REG(0x020e050c) = 0x00000028;
+	__REG(0x020e05b8) = 0x00000028;
+	__REG(0x020e05c0) = 0x00000028;
+
+	__REG(0x020e05ac) = 0x00000028;
+	__REG(0x020e05b4) = 0x00000028;
+	__REG(0x020e0528) = 0x00000028;
+	__REG(0x020e0520) = 0x00000028;
+
+	__REG(0x020e0514) = 0x00000028;
+	__REG(0x020e0510) = 0x00000028;
+	__REG(0x020e05bc) = 0x00000028;
+	__REG(0x020e05c4) = 0x00000028;
+
+	__REG(0x020e056c) = 0x00000030;
+	__REG(0x020e0578) = 0x00000030;
+	__REG(0x020e0588) = 0x00000030;
+	__REG(0x020e0594) = 0x00000030;
+
+	__REG(0x020e057c) = 0x00000030;
+	__REG(0x020e0590) = 0x00000030;
+	__REG(0x020e0598) = 0x00000030;
+	__REG(0x020e058c) = 0x00000000;
+
+	__REG(0x020e059c) = 0x00003030;
+	__REG(0x020e05a0) = 0x00003030;
+	__REG(0x020e0784) = 0x00000028;
+	__REG(0x020e0788) = 0x00000028;
+
+	__REG(0x020e0794) = 0x00000028;
+	__REG(0x020e079c) = 0x00000028;
+	__REG(0x020e07a0) = 0x00000028;
+	__REG(0x020e07a4) = 0x00000028;
+
+	__REG(0x020e07a8) = 0x00000028;
+	__REG(0x020e0748) = 0x00000028;
+	__REG(0x020e074c) = 0x00000030;
+	__REG(0x020e0750) = 0x00020000;
+
+	__REG(0x020e0758) = 0x00000000;
+	__REG(0x020e0774) = 0x00020000;
+	__REG(0x020e078c) = 0x00000030;
+	__REG(0x020e0798) = 0x000C0000;
+
+	__REG(0x021b081c) = 0x33333333;
+	__REG(0x021b0820) = 0x33333333;
+	__REG(0x021b0824) = 0x33333333;
+	__REG(0x021b0828) = 0x33333333;
+
+	__REG(0x021b481c) = 0x33333333;
+	__REG(0x021b4820) = 0x33333333;
+	__REG(0x021b4824) = 0x33333333;
+	__REG(0x021b4828) = 0x33333333;
+
+	__REG(0x021b0018) = 0x00001740;
+
+	__REG(0x021b001c) = 0x00008000;
+	__REG(0x021b000c) = 0x8A8F7975;
+	__REG(0x021b0010) = 0xFF538E64;
+	__REG(0x021b0014) = 0x01FF00DB;
+	__REG(0x021b002c) = 0x000026D2;
+
+	__REG(0x021b0030) = 0x008F0E21;
+	__REG(0x021b0008) = 0x09444040;
+	__REG(0x021b0004) = 0x00020036;
+	__REG(0x021b0040) = 0x00000047;
+	__REG(0x021b0000) = 0x841A0000;
+
+	__REG(0x021b001c) = 0x04088032;
+	__REG(0x021b001c) = 0x00008033;
+	__REG(0x021b001c) = 0x00428031;
+	__REG(0x021b001c) = 0x09408030;
+
+	__REG(0x021b001c) = 0x04008040;
+	__REG(0x021b0800) = 0xA1380003;
+	__REG(0x021b0020) = 0x00005800;
+	__REG(0x021b0818) = 0x00000007;
+	__REG(0x021b4818) = 0x00000007;
+
+	/* Calibration values based on ARD and 528MHz */
+	__REG(0x021b083c) = 0x434B0358;
+	__REG(0x021b0840) = 0x033D033C;
+	__REG(0x021b483c) = 0x03520362;
+	__REG(0x021b4840) = 0x03480318;
+	__REG(0x021b0848) = 0x41383A3C;
+	__REG(0x021b4848) = 0x3F3C374A;
+	__REG(0x021b0850) = 0x42434444;
+	__REG(0x021b4850) = 0x4932473A;
+
+	__REG(0x021b080c) = 0x001F001F;
+	__REG(0x021b0810) = 0x001F001F;
+
+	__REG(0x021b480c) = 0x001F001F;
+	__REG(0x021b4810) = 0x001F001F;
+
+	__REG(0x021b08b8) = 0x00000800;
+	__REG(0x021b48b8) = 0x00000800;
+
+	__REG(0x021b0404) = 0x00011006;
+	__REG(0x021b0004) = 0x00025576;
+
+	__REG(0x021b001c) = 0x00000000;
+
+	__REG(0x020c4068) = 0x00C03F3F;
+	__REG(0x020c406c) = 0x0030FC00;
+	__REG(0x020c4070) = 0x0FFFC000;
+	__REG(0x020c4074) = 0x3FF00000;
+	__REG(0x020c4078) = 0x00FFF300;
+	__REG(0x020c407c) = 0x0F0000C3;
+	__REG(0x020c4080) = 0x000003FF;
+}
+
+/*
+ * This section require the differentiation
+ * between iMX6 Sabre Families.
+ * But for now, it will configure only for
+ * SabreSD.
+ */
+static u32 spl_dram_init(void)
+{
+	u32 ddr_size;
+
+	set_mt41j128_ddr();
+	ddr_size = 0x40000000;
+	
+	return ddr_size;
+}
+
+int spl_board_mmc_init(bd_t *bis)
+{
+	unsigned reg = readl(BOOT_CFG);
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * 0x840                   SD2
+	 * 0x1040                  SD3
+	 * 0x1840                  eMMC
+	 */
+	switch (reg) {
+	case 0x840:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		spl_usdhc_cfg.esdhc_base = USDHC2_BASE_ADDR;
+		spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+		break;
+	case 0x1040:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		spl_usdhc_cfg.esdhc_base = USDHC3_BASE_ADDR;
+		spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+		break;
+	case 0x1840:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		spl_usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR;
+		spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+		gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+		break;
+	}
+
+	return fsl_esdhc_initialize(bis, &spl_usdhc_cfg);
+}
+
+void board_init_f(ulong dummy)
+{
+	u32 ram_size;
+
+	/* Set the stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	ram_size = spl_dram_init();
+
+	arch_cpu_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+	gd->ram_size = ram_size;
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif
Signature · 1 line
1.9.1
#11 lore raw

PATCH v2 6/8 imx6: SPL support for iMX6 SabreSD

Hello John,

Quoted 3 lines · John Tobias

This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port.
---

<snip>

Quoted 21 lines
  board/freescale/mx6sabresd/mx6sabresd.c | 216 ++++++++++++++++++++++++++++++++
  1 file changed, 216 insertions(+)
board/freescale/mx6sabresd/mx6sabresd.c +9 -0
index 3d81fff..d090487 100644
@@ -607,3 +607,219 @@ int checkboard(void)
  	puts("Board: MX6-SabreSD\n");
  	return 0;
  }
 
+
+void board_init_f(ulong dummy)
+{
+	u32 ram_size;
+
+	/* Set the stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	ram_size = spl_dram_init();

board/freescale/mx6sabresd/mx6sabresd.c int checkboard(void) · line 812

Quoted 10 lines
board/freescale/mx6sabresd/mx6sabresd.c +10 -0
+
+	arch_cpu_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+	gd->ram_size = ram_size;
+

sp and gd should already be valid by the time board_init_f is called. There is no need to set them again.

board/freescale/mx6sabresd/mx6sabresd.c int checkboard(void) · line 821

Quoted 9 lines
board/freescale/mx6sabresd/mx6sabresd.c +9 -0
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	board_init_r(NULL, 0);
+}
+

Regards,
Jeroen

author
#12 lore raw

PATCH v2 6/8 imx6: SPL support for iMX6 SabreSD

Hi Jeroen,

Thanks for the info. and you are correct. I have version 3 already...

Will send the v3 in a moment...

Regards,

john

Quoted 65 lines · Jeroen Hofstee

Hello John,

Quoted 4 lines · John Tobias

This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port.
---

<snip>

Quoted 24 lines
  board/freescale/mx6sabresd/mx6sabresd.c | 216
++++++++++++++++++++++++++++++++
  1 file changed, 216 insertions(+)
board/freescale/mx6sabresd/mx6sabresd.c +9 -0
index 3d81fff..d090487 100644
@@ -607,3 +607,219 @@ int checkboard(void)
        puts("Board: MX6-SabreSD\n");
        return 0;
  }
 
+
+void board_init_f(ulong dummy)
+{
+       u32 ram_size;
+
+       /* Set the stack pointer. */
+       asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+       ram_size = spl_dram_init();

board/freescale/mx6sabresd/mx6sabresd.c int checkboard(void) · line 812

Quoted 10 lines
board/freescale/mx6sabresd/mx6sabresd.c +10 -0
+
+       arch_cpu_init();
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       /* Set global data pointer. */
+       gd = &gdata;
+       gd->ram_size = ram_size;
+

sp and gd should already be valid by the time board_init_f is called. There is no need to set them again.

board/freescale/mx6sabresd/mx6sabresd.c int checkboard(void) · line 821

Quoted 10 lines
board/freescale/mx6sabresd/mx6sabresd.c +9 -0
+       board_early_init_f();
+
+       timer_init();
+
+       preloader_console_init();
+
+       board_init_r(NULL, 0);
+}
+

Regards,
Jeroen

author
#13 lore raw

PATCH v2 7/8 imx6: add data configuration file for SPL

In reply to John Tobias

This file is the default DCD configuration file for SPL

---
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 54 +++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file +54 -0
new file mode 100644
index 0000000..2e2f850
@@ -0,0 +1,54 @@
+/*
+ * Maintainer : Richard Hu <[email protected]>
+ *
+ * Derived from Nitrogen6x code by Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* set the default clock gate to save power */
+DATA 4 0x020C4068 0x00C03F3F /* CCM_CCGR0 */
+DATA 4 0x020C406c 0x0030FC03 /* CCM_CCGR1 */
+DATA 4 0x020C4070 0x0FFFC000 /* CCM_CCGR2 */
+DATA 4 0x020C4074 0x3FF00000 /* CCM_CCGR3 */
+DATA 4 0x020C4078 0xFFF300   /* CCM_CCGR4 */
+DATA 4 0x020C407c 0x0F0000F3 /* CCM_CCGR5 - enable SATA clocks */
+DATA 4 0x020C4080 0x000003FF /* CCM_CCGR6 - enable ushdc and usb clocks */
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF /* IOMUXC_GPR4 */
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F /* IOMUXC_GPR6 */
+DATA 4 0x020e001c 0x007F007F /* IOMUXC_GPR7 */
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb /* CCM_CCOSR */
+
+
Signature · 1 line
1.9.1
author
#14 lore raw

PATCH v2 8/8 kconfig: imx6: add SUPPORT_SPL

In reply to John Tobias

add SUPPORT_SPL for iMX6 SabreSD by default

---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/Kconfig +1 -0
index 22eb2d5..ab0d284 100644
@@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO
 config TARGET_MX6SABRESD
 	bool "Support mx6sabresd"
 	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_MX6SLEVK
 	bool "Support mx6slevk"
Signature · 1 line
1.9.1