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ARM: dts: imx6qdl: Enable CODA960 VPU

PATCH New Fabio Estevam 2 participants 2 messages Nov 11, 2014 – Nov 12, 2014

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Device tree bindings Arm i.MX and Layerscape
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Fabio Estevam

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PATCH 1/1 ARM: dts: imx6qdl: Enable CODA960 VPU

From: Philipp Zabel <[email protected]>

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Signed-off-by Philipp Zabel <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx6dl.dtsi  | 4 ++++
 arch/arm/boot/dts/imx6q.dtsi   | 4 ++++
 arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++
 3 files changed, 16 insertions(+)
arch/arm/boot/dts/imx6dl.dtsi +4 -0
index 44d8876..1ac2fe7 100644
@@ -118,3 +118,7 @@
 		      "di0_sel", "di1_sel",
 		      "di0", "di1";
 };
+
+&vpu {
+	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6q.dtsi +4 -0
index e9f3646..85f72e6 100644
@@ -308,3 +308,7 @@
 		};
 	};
 };
+
+&vpu {
+	compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
arch/arm/boot/dts/imx6qdl.dtsi +8 -0
index 9596ed5..e529308 100644
@@ -333,9 +333,17 @@
 			};
 
 			vpu: vpu at 02040000 {
+				compatible = "cnm,coda960";
 				reg = <0x02040000 0x3c000>;
 				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
 				             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "bit", "jpeg";
+				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
+					 <&clks IMX6QDL_CLK_OCRAM>;
+				clock-names = "per", "ahb", "ocram";
+				resets = <&src 1>;
+				iram = <&ocram>;
 			};
 
 			aipstz at 0207c000 { /* AIPSTZ1 */
Signature · 1 line
1.9.1
Applied
#1 lore raw

PATCH 1/1 ARM: dts: imx6qdl: Enable CODA960 VPU

Quoted 11 lines · Fabio Estevam

From: Philipp Zabel <[email protected]>

This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason.

Signed-off-by Philipp Zabel <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>

Applied, thanks.