mtd: nand: omap_gpmc: Add CONFIG_SYS_NAND_USE_READY to enable ready/busy
Subsystems (2)
PATCH 1/2 mtd: nand: omap_gpmc: Add CONFIG_SYS_NAND_USE_READY to enable ready/busy
By defining CONFIG_SYS_NAND_USE_READY the GPMC NAND driver makes use of the ready pin / signal for busy / ready detection. This function is already available but currently only used in SPL. I don't see a reason to not use it in the main U-Boot as well. As it increases the NAND performance.
I'm making it configurable, so that boards that might now have this pin connected are still supported.
--- README | 5 +++++ drivers/mtd/nand/omap_gpmc.c | 20 +++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-)
README +5 -0
@@ -4731,6 +4731,11 @@ Low Level (hardware related) configuration options: - drivers/mtd/nand/ndfc.c - drivers/mtd/nand/mxc_nand.c +- CONFIG_SYS_NAND_USE_READY + Defined if a ready/busy pin is available on this board + which can be used to determine the state of the NAND + chip. Currently used on the OMAP/AM33xx NAND driver. + - CONFIG_SYS_NDFC_EBC0_CFG Sets the EBC0_CFG register for the NDFC. If not defined a default value will be used.
drivers/mtd/nand/omap_gpmc.c +17 -3
@@ -23,6 +23,16 @@/* 4 bit padding to make byte aligned, 56 = 52 + 4 */ #define BCH4_BIT_PAD 4 +/* +* All OMAP / AM33xx SPL builds already use the ready / busy pin. +* So lets enable this new define to use this signal for SPL. This +* makes the check in the code easier since its reduced to a single +* macro. +*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_NAND_USE_READY +#endif +#ifdef CONFIG_BCH static u8 bch8_polynomial[] = {0xef ,0x51 ,0x2e ,0x09 ,0xed ,0x93 ,0x9a ,0xc2 ,0x97 ,0x79 ,0xe5 ,0x24 ,0xb5 };
@@ -73,9 +83,9 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,writeb (cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_SYS_NAND_USE_READY /* Check wait pin as dev ready indicator */ -static int omap_spl_dev_ready (struct mtd_info *mtd) +static int omap_dev_ready (struct mtd_info *mtd) {return gpmc_cfg->status & (1 <<8 ); }
@@ -887,7 +897,11 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf16; else nand->read_buf = nand_read_buf; - nand->dev_ready = omap_spl_dev_ready;#endif + +#ifdef CONFIG_SYS_NAND_USE_READY + nand->dev_ready = omap_dev_ready; +#endif +return 0 ; }
Signature · 1 line
2.1.3
PATCH 2/2 arm: am335x: Enable CONFIG_SYS_NAND_USE_READY on siemens am33xx
Testing showed a small perfomance gain by using this ready pin to detect the NAND chip state. Here the values tested on Draco with Hynix 4GBit NAND:
Without NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.947 seconds, 2947 ticks
With NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK
time: 2.795 seconds, 2795 ticks
So an increase of approx. 5%.
--- include/configs/siemens-am33x-common.h | 2 ++ 1 file changed, 2 insertions(+)
include/configs/siemens-am33x-common.h +2 -0
@@ -466,6 +466,8 @@/* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1/* Max number of NAND devices */ +#define CONFIG_SYS_NAND_USE_READY +#if !defined(CONFIG_SPI_BOOT )#undef CONFIG_ENV_IS_NOWHERE#define CONFIG_ENV_IS_IN_NAND
Signature · 1 line
2.1.3
PATCH 1/2 mtd: nand: omap_gpmc: Add CONFIG_SYS_NAND_USE_READY to enable ready/busy
In reply to Stefan RoeseQuoted 24 lines · Stefan Roese
By defining
CONFIG_SYS_NAND_USE_READYthe GPMC NAND driver makes use of the ready pin / signal for busy / ready detection. This function is already available but currently only used in SPL. I don't see a reason to not use it in the main U-Boot as well. As it increases the NAND performance.I'm making it configurable, so that boards that might now have this pin connected are still supported.
Signed-off-by Stefan Roese <[email protected]>Cc Tom Rini <[email protected]>Cc Scott Wood <[email protected]>Cc Roger Meier <[email protected]>Cc Samuel Egli <[email protected]>--- README | 5 +++++ drivers/mtd/nand/omap_gpmc.c | 20 +++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-)README +0
-0
README Low Level (hardware related) configuration options: · line 4738
Quoted 8 lines
README +5
-0@@ -4731,6 +4731,11 @@ Low Level (hardware related) configuration options: - drivers/mtd/nand/ndfc.c - drivers/mtd/nand/mxc_nand.c +- CONFIG_SYS_NAND_USE_READY + Defined if a ready/busy pin is available on this board + which can be used to determine the state of the NAND + chip. Currently used on the OMAP/AM33xx NAND driver. +
New symbols should be done in kconfig.
Is this really something that ought to be a generic symbol, rather than OMAP-specific?
-Scott
PATCH 1/2 mtd: nand: omap_gpmc: Add CONFIG_SYS_NAND_USE_READY to enable ready/busy
In reply to Stefan RoeseQuoted 8 lines · Stefan Roese
By defining
CONFIG_SYS_NAND_USE_READYthe GPMC NAND driver makes use of the ready pin / signal for busy / ready detection. This function is already available but currently only used in SPL. I don't see a reason to not use it in the main U-Boot as well. As it increases the NAND performance.I'm making it configurable, so that boards that might now have this pin connected are still supported.
I don't think we need to make this configurable. I think it's always been an oversight since we've always done this in NAND for SPL and I can't think of any boards that do support NAND but don't support booting from NAND in U-Boot.
Signature · 8 lines
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