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pci: correct BAR size calculation

PATCH Applied Lucas Stach 2 participants 4 messages Nov 12, 2014 – Nov 17, 2014

Subsystems (2)
PCI Tegra architecture support
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Lucas Stach

author
#0 lore raw

PATCH 1/3 pci: correct BAR size calculation

The previous math would return negative sizes
for some BARs.

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/pci/pci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/pci/pci.c +3 -3
index ba9d097..87c2fca 100644
@@ -154,7 +154,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 		}
 
 		if (mask & 0x01) { /* IO */
-			size = -(mask & 0xfffffffe);
+			size = ((~(mask & 0xfffffffe)) & 0xffff) + 1;
 			DBG("  PCI: pbar%d: mask=%08x io %d bytes\n", bar, mask, size);
 			if (last_io + size >
 			    dev->bus->resource[PCI_BUS_RESOURCE_IO]->end) {

@@ -167,7 +167,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			last_io += size;
 		} else if ((mask & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
 		           last_mem_pref) /* prefetchable MEM */ {
-			size = -(mask & 0xfffffff0);
+			size = (~(mask & 0xfffffff0)) + 1;
 			DBG("  PCI: pbar%d: mask=%08x P memory %d bytes\n",
 			    bar, mask, size);
 			if (last_mem_pref + size >

@@ -181,7 +181,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			last_addr = last_mem_pref;
 			last_mem_pref += size;
 		} else { /* non-prefetch MEM */
-			size = -(mask & 0xfffffff0);
+			size = (~(mask & 0xfffffff0)) + 1;
 			DBG("  PCI: pbar%d: mask=%08x NP memory %d bytes\n",
 			    bar, mask, size);
 			if (last_mem + size >
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author
#1 lore raw

PATCH 2/3 pci: align bridge windows

The bridge filtering logic needs a minimum alignment of 1MB for mem and 4KB for io resources. Take this into account while assigning resources to devices in oredr to not produce overlapping windows between different bridges.

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/pci/pci.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/pci/pci.c +4 -0
index 87c2fca..7f8ebcf 100644
@@ -1,4 +1,5 @@
 #include <common.h>
+#include <sizes.h>
 #include <linux/pci.h>
 
 #ifdef DEBUG

@@ -259,14 +260,17 @@ static void postscan_setup_bridge(struct pci_dev *dev)
 	pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, bus_index - 1);
 
 	if (last_mem)
+		last_mem = ALIGN(last_mem, SZ_1M);
 		pci_write_config_word(dev, PCI_MEMORY_LIMIT,
 				      ((last_mem - 1) & 0xfff00000) >> 16);
 
 	if (last_mem_pref)
+		last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
 		pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
 				      ((last_mem_pref - 1) & 0xfff00000) >> 16);
 
 	if (last_io) {
+		last_io = ALIGN(last_io, SZ_4K);
 		pci_write_config_byte(dev, PCI_IO_LIMIT,
 				((last_io - 1) & 0x0000f000) >> 8);
 		pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
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author
#2 lore raw

PATCH 3/3 pci: tegra: relax link-up timeout

In reply to Lucas Stach

Some devices need a considerable amount of time from reset deassertion until they are ready to establish a link. Relaxing the link-up timeout helps to detect them more reliable.

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/pci/pci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/pci/pci-tegra.c +1 -1
index f2ade77..1ff3c0d 100644
@@ -1145,7 +1145,7 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
 	writel(value, port->base + RP_PRIV_MISC);
 
 	do {
-		timeout = wait_on_timeout(50 * MSECOND,
+		timeout = wait_on_timeout(150 * MSECOND,
 			readl(port->regs.start + RP_VEND_XP) & RP_VEND_XP_DL_UP);
 
 		if (timeout) {
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Applied
#3 lore raw
In reply to Lucas Stach
Quoted 4 lines · Lucas Stach

The previous math would return negative sizes
for some BARs.

Signed-off-by Lucas Stach <[email protected]>

Applied all, thanks

Sascha

Quoted 44 lines
---
 drivers/pci/pci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/pci/pci.c +3 -3
index ba9d097..87c2fca 100644
@@ -154,7 +154,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 		}
 
 		if (mask & 0x01) { /* IO */
-			size = -(mask & 0xfffffffe);
+			size = ((~(mask & 0xfffffffe)) & 0xffff) + 1;
 			DBG("  PCI: pbar%d: mask=%08x io %d bytes\n", bar, mask, size);
 			if (last_io + size >
 			    dev->bus->resource[PCI_BUS_RESOURCE_IO]->end) {

@@ -167,7 +167,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			last_io += size;
 		} else if ((mask & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
 		           last_mem_pref) /* prefetchable MEM */ {
-			size = -(mask & 0xfffffff0);
+			size = (~(mask & 0xfffffff0)) + 1;
 			DBG("  PCI: pbar%d: mask=%08x P memory %d bytes\n",
 			    bar, mask, size);
 			if (last_mem_pref + size >

@@ -181,7 +181,7 @@ static void setup_device(struct pci_dev *dev, int max_bar)
 			last_addr = last_mem_pref;
 			last_mem_pref += size;
 		} else { /* non-prefetch MEM */
-			size = -(mask & 0xfffffff0);
+			size = (~(mask & 0xfffffff0)) + 1;
 			DBG("  PCI: pbar%d: mask=%08x NP memory %d bytes\n",
 			    bar, mask, size);
 			if (last_mem + size >
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