mx6sabresd: Move the DCD settings to spl code

PATCH New Fabio Estevam 4 participants 12 messages Nov 14, 2014 – Dec 4, 2014

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Arm (32-bit) Arm i.MX and Layerscape

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Fabio Estevam

author reviewer

2014-11-14 11:36 UTC #0 lore raw

PATCH v2 1/4 mx6sabresd: Move the DCD settings to spl code

From: Fabio Estevam <[email protected]>

mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- None. Send it as a series and use a common spl .cfg per Stefano's suggestion

 board/freescale/mx6sabresd/mx6sabresd.c       | 27 +++++++++++++++++++
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 38 ---------------------------
 2 files changed, 27 insertions(+), 38 deletions(-)

board/freescale/mx6sabresd/mx6sabresd.c +27 -0

index 1142e8a..343c3b6 100644
@@ -729,6 +729,30 @@ static struct mx6_ddr3_cfg mem_ddr = {
 	.trasmin = 3500,
 };
 
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
 /*
  * This section require the differentiation
  * between iMX6 Sabre Families.

@@ -768,6 +792,9 @@ void board_init_f(ulong dummy)
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
+	ccgr_init();
+	gpr_init();
+
 	/* iomux and setup of i2c */
 	board_early_init_f();

board/freescale/mx6sabresd/mx6sabresd_spl.cfg +0 ~~-38~~

index 2bf4817..1d031ba 100644
@@ -18,41 +18,3 @@ IMAGE_VERSION 2
  * spi, sd (the board has no nand neither onenand)
  */
 BOOT_FROM      sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb

Signature · 1 line

1.9.1

Fabio Estevam

author reviewer

2014-11-14 11:37 UTC #1 lore raw

PATCH v2 2/4 gw_ventana: Move the DCD settings to spl code

From: Fabio Estevam <[email protected]>

mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced on this series

 board/gateworks/gw_ventana/clocks.cfg       | 42 -----------------------------
 board/gateworks/gw_ventana/gw_ventana.cfg   |  6 -----
 board/gateworks/gw_ventana/gw_ventana_spl.c | 28 +++++++++++++++++++
 3 files changed, 28 insertions(+), 48 deletions(-)
 delete mode 100644 board/gateworks/gw_ventana/clocks.cfg

board/gateworks/gw_ventana/clocks.cfg deleted +0 ~~-42~~

deleted file mode 100644
index a8118a2..0000000
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 Gateworks Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1    --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb

board/gateworks/gw_ventana/gw_ventana.cfg +0 -6

index 9ab95f5..dd8aa61 100644
@@ -21,9 +21,3 @@ BOOT_FROM      spi
 #else
 BOOT_FROM      nand
 #endif
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-#include "clocks.cfg"

board/gateworks/gw_ventana/gw_ventana_spl.c +28 -0

index ca35b3c..d6a5847 100644
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <asm/io.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>

@@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 	mx6_dram_cfg(&sysinfo, calib, mem);
 }
 
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
 /*
  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  * - we have a stack and a place to store GD, both in SRAM

@@ -405,6 +430,9 @@ void board_init_f(ulong dummy)
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
+	ccgr_init();
+	gpr_init();
+
 	/* iomux and setup of i2c */
 	board_early_init_f();
 	i2c_setup_iomux();

Signature · 1 line

1.9.1

Stefano Babic

2014-11-20 09:36 UTC #2 lore raw

PATCH v2 2/4 gw_ventana: Move the DCD settings to spl code

Quoted 11 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.
Signed-off-by Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefan Roese

2014-12-04 11:49 UTC #3 lore raw

PATCH v2 2/4 gw_ventana: Move the DCD settings to spl code

In reply to Fabio Estevam

Hi Fabio, Hi Tim,

Quoted 8 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.

While reworking another mx6 based board (patches will follow soon), I noticed a problem with this patch. Please see below.

Quoted 30 lines

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced on this series

  board/gateworks/gw_ventana/clocks.cfg       | 42 -----------------------------
  board/gateworks/gw_ventana/gw_ventana.cfg   |  6 -----
  board/gateworks/gw_ventana/gw_ventana_spl.c | 28 +++++++++++++++++++
  3 files changed, 28 insertions(+), 48 deletions(-)

delete mode 100644 board/gateworks/gw_ventana/clocks.cfg

board/gateworks/gw_ventana/clocks.cfg deleted +0 ~~-13~~

deleted file mode 100644
index a8118a2..0000000
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 Gateworks Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)

board/gateworks/gw_ventana/clocks.cfg line 23

Quoted 10 lines

board/gateworks/gw_ventana/clocks.cfg deleted +0 ~~-10~~

- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */

Notice here the 0xFFFFF300...

Quoted 48 lines

board/gateworks/gw_ventana/clocks.cfg deleted +0 ~~-19~~

-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1    --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb

board/gateworks/gw_ventana/gw_ventana.cfg +0 -6

index 9ab95f5..dd8aa61 100644
@@ -21,9 +21,3 @@ BOOT_FROM      spi
  #else
  BOOT_FROM      nand
  #endif
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-#include "clocks.cfg"

board/gateworks/gw_ventana/gw_ventana_spl.c +1 -0

index ca35b3c..d6a5847 100644
@@ -8,6 +8,7 @@
  #include <common.h>
  #include <i2c.h>
  #include <asm/io.h>
+#include <asm/arch/crm_regs.h>
  #include <asm/arch/iomux.h>
  #include <asm/arch/mx6-ddr.h>
  #include <asm/arch/mx6-pins.h>

@@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model)
  	mx6_dram_cfg(&sysinfo, calib, mem);
  }

board/gateworks/gw_ventana/gw_ventana_spl.c static void spl_dram_init(int width, int size_mb, int board_model) · line 404

Quoted 10 lines

board/gateworks/gw_ventana/gw_ventana_spl.c +9 -0

 
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);

... and now here the 0x00FFF300! I'm pretty sure that it should be the same value as above. Otherwise NAND booting will not work correctly. At least from my experience.

I'll send a patch to fix this shortly...

Thanks,
Stefan

Fabio Estevam

author reviewer

2014-11-14 11:37 UTC #4 lore raw

PATCH v2 3/4 novena: Move the DCD settings to spl code

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced on this series

 board/kosagi/novena/novena_spl.c | 27 +++++++++++++++++++++++++++
 board/kosagi/novena/setup.cfg    | 31 -------------------------------
 2 files changed, 27 insertions(+), 31 deletions(-)

board/kosagi/novena/novena_spl.c +27 -0

index c4155dd..9cf3979 100644
@@ -533,6 +533,30 @@ static struct mx6_ddr3_cfg elpida_4gib_1600 = {
 	.trasmin	= 3590,
 };
 
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0xFFFFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
 /*
  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  * - we have a stack and a place to store GD, both in SRAM

@@ -543,6 +567,9 @@ void board_init_f(ulong dummy)
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
+	ccgr_init();
+	gpr_init();
+
 	/* setup GP timer */
 	timer_init();

board/kosagi/novena/setup.cfg +0 ~~-31~~

index 18d139c..a79d1f7 100644
@@ -14,34 +14,3 @@ IMAGE_VERSION 2
 
 /* Boot Device : sd */
 BOOT_FROM sd
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1    --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb

Signature · 1 line

1.9.1

Marek Vasut

2014-11-14 20:07 UTC #5 lore raw

PATCH v2 3/4 novena: Move the DCD settings to spl code

Quoted 10 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.
Signed-off-by Fabio Estevam <[email protected]>

Board still works.

Reviewed-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Stefano Babic

2014-11-20 09:29 UTC #6 lore raw

PATCH v2 3/4 novena: Move the DCD settings to spl code

Quoted 5 lines · Marek Vasut

Quoted 4 lines · Fabio Estevam
From: Fabio Estevam <[email protected]>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Quoted 8 lines

Quoted 6 lines
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.
Signed-off-by Fabio Estevam <[email protected]>
Board still works.

I wonder you can compile it, because crm_regs.h is missing in novena_spl.c. I fix it myself, but I am wondering that it worked on your side.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2014-11-20 09:37 UTC #7 lore raw

PATCH v2 3/4 novena: Move the DCD settings to spl code

In reply to Fabio Estevam

Quoted 11 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.
Signed-off-by Fabio Estevam <[email protected]>
---

After a small fix (include crm_regs.h):

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Fabio Estevam

author reviewer

2014-11-14 11:37 UTC #8 lore raw

PATCH v2 4/4 mx6: Use a common SPL configuration file

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Many boards use a minimal .cfg file in the SPL case.

Introduce spl_sd.cfg so that we can reuse it.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced on this series

 arch/arm/imx-common/spl_sd.cfg                |  8 ++++++++
 board/compulab/cm_fx6/imximage.cfg            |  8 --------
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 20 --------------------
 board/kosagi/novena/setup.cfg                 | 16 ----------------
 configs/cm_fx6_defconfig                      |  2 +-
 configs/mx6sabresd_spl_defconfig              |  2 +-
 configs/novena_defconfig                      |  2 +-
 7 files changed, 11 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/imx-common/spl_sd.cfg
 delete mode 100644 board/compulab/cm_fx6/imximage.cfg
 delete mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
 delete mode 100644 board/kosagi/novena/setup.cfg

arch/arm/imx-common/spl_sd.cfg new file +8 -0

new file mode 100644
index 0000000..5fc3e8a
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION	2
+BOOT_FROM	sd

board/compulab/cm_fx6/imximage.cfg deleted +0 -8

deleted file mode 100644
index 420947e..0000000
@@ -1,8 +0,0 @@
-/*
- * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-IMAGE_VERSION 2
-BOOT_FROM	sd

board/freescale/mx6sabresd/mx6sabresd_spl.cfg deleted +0 ~~-20~~

deleted file mode 100644
index 1d031ba..0000000
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd

board/kosagi/novena/setup.cfg deleted +0 ~~-16~~

deleted file mode 100644
index a79d1f7..0000000
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2014 Marek Vasut <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/* Boot Device : sd */
-BOOT_FROM sd

configs/cm_fx6_defconfig +1 -1

index 50c06f7..3c0d64f 100644
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_CM_FX6=y

configs/mx6sabresd_spl_defconfig +1 -1

index b7b26df..12e7844 100644
@@ -1,5 +1,5 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_MX6SABRESD=y

configs/novena_defconfig +1 -1

index a560afb..d28dbd7 100644
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q,SPL"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_KOSAGI_NOVENA=y

Signature · 1 line

1.9.1

Stefano Babic

2014-11-17 13:18 UTC #9 lore raw

PATCH v2 4/4 mx6: Use a common SPL configuration file

Hi Fabio,

Quoted 127 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

Many boards use a minimal .cfg file in the SPL case.

Introduce spl_sd.cfg so that we can reuse it.

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v1:
- Newly introduced on this series

 arch/arm/imx-common/spl_sd.cfg                |  8 ++++++++
 board/compulab/cm_fx6/imximage.cfg            |  8 --------
 board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 20 --------------------
 board/kosagi/novena/setup.cfg                 | 16 ----------------
 configs/cm_fx6_defconfig                      |  2 +-
 configs/mx6sabresd_spl_defconfig              |  2 +-
 configs/novena_defconfig                      |  2 +-
 7 files changed, 11 insertions(+), 47 deletions(-)
 create mode 100644 arch/arm/imx-common/spl_sd.cfg
 delete mode 100644 board/compulab/cm_fx6/imximage.cfg
 delete mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
 delete mode 100644 board/kosagi/novena/setup.cfg

arch/arm/imx-common/spl_sd.cfg new file +8 -0

new file mode 100644
index 0000000..5fc3e8a
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION	2
+BOOT_FROM	sd

board/compulab/cm_fx6/imximage.cfg deleted +0 -8

deleted file mode 100644
index 420947e..0000000
@@ -1,8 +0,0 @@
-/*
- * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-IMAGE_VERSION 2
-BOOT_FROM	sd

board/freescale/mx6sabresd/mx6sabresd_spl.cfg deleted +0 ~~-20~~

deleted file mode 100644
index 1d031ba..0000000
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd

board/kosagi/novena/setup.cfg deleted +0 ~~-16~~

deleted file mode 100644
index a79d1f7..0000000
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2014 Marek Vasut <[email protected]>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/* Boot Device : sd */
-BOOT_FROM sd

configs/cm_fx6_defconfig +1 -1

index 50c06f7..3c0d64f 100644
@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_CM_FX6=y

configs/mx6sabresd_spl_defconfig +1 -1

index b7b26df..12e7844 100644
@@ -1,5 +1,5 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_MX6SABRESD=y

configs/novena_defconfig +0 -0

index a560afb..d28dbd7 100644

configs/novena_defconfig line 4

Quoted 5 lines

configs/novena_defconfig +1 -1

@@ -1,4 +1,4 @@
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q,SPL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q,SPL"
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_KOSAGI_NOVENA=y

Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2014-11-20 09:37 UTC #10 lore raw

PATCH v2 4/4 mx6: Use a common SPL configuration file

In reply to Fabio Estevam

Quoted 8 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
Many boards use a minimal .cfg file in the SPL case.
Introduce spl_sd.cfg so that we can reuse it.
Signed-off-by Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2014-11-20 09:36 UTC #11 lore raw

PATCH v2 1/4 mx6sabresd: Move the DCD settings to spl code

In reply to Fabio Estevam

Quoted 11 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in the kernel, so remove such setting.
Signed-off-by Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================