ARM: atmel: add sama5d4ek board support

index 9114a86..20fcecb 100644
@@ -762,6 +762,62 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host,
 }
 #endif
 
+#if defined(NO_GALOIS_TABLE_IN_ROM)
+static uint16_t *pmecc_galois_table;
+static inline int deg(unsigned int poly)
+{
+	/* polynomial degree is the most-significant bit index */
+	return fls(poly) - 1;
+}
+
+static int build_gf_tables(int mm, unsigned int poly,
+			   int16_t *index_of, int16_t *alpha_to)
+{
+	unsigned int i, x = 1;
+	const unsigned int k = 1 << deg(poly);
+	unsigned int nn = (1 << mm) - 1;
+
+	/* primitive polynomial must be of degree m */
+	if (k != (1u << mm))
+		return -EINVAL;
+
+	for (i = 0; i < nn; i++) {
+		alpha_to[i] = x;
+		index_of[x] = i;
+		if (i && (x == 1))
+			/* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
+			return -EINVAL;
+		x <<= 1;
+		if (x & k)
+			x ^= poly;
+	}
+
+	alpha_to[nn] = 1;
+	index_of[0] = 0;
+
+	return 0;
+}
+
+static uint16_t *create_lookup_table(int sector_size)
+{
+	int degree = (sector_size == 512) ?
+			PMECC_GF_DIMENSION_13 :
+			PMECC_GF_DIMENSION_14;
+	unsigned int poly = (sector_size == 512) ?
+			PMECC_GF_13_PRIMITIVE_POLY :
+			PMECC_GF_14_PRIMITIVE_POLY;
+	int table_size = (sector_size == 512) ?
+			PMECC_INDEX_TABLE_SIZE_512 :
+			PMECC_INDEX_TABLE_SIZE_1024;
+
+	int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
+	if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
+		return NULL;
+
+	return (uint16_t *)addr;
+}
+#endif
+
 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 		struct mtd_info *mtd)
 {

@@ -809,11 +865,18 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 	sector_size = host->pmecc_sector_size;
 
 	/* TODO: need check whether cap & sector_size is validate */
-
+#if defined(NO_GALOIS_TABLE_IN_ROM)
+	/*
+	 * As pmecc_rom_base is the begin of the gallois field table, So the
+	 * index offset just set as 0.
+	 */
+	host->pmecc_index_table_offset = 0;
+#else
 	if (host->pmecc_sector_size == 512)
 		host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
 	else
 		host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
+#endif
 
 	MTDDEBUG(MTD_DEBUG_LEVEL1,
 		"Initialize PMECC params, cap: %d, sector: %d\n",

@@ -822,7 +885,17 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 	host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
 	host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
 			ATMEL_BASE_PMERRLOC;
+#if defined(NO_GALOIS_TABLE_IN_ROM)
+	pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
+	if (!pmecc_galois_table) {
+		dev_err(host->dev, "out of memory\n");
+		return -ENOMEM;
+	}
+
+	host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
+#else
 	host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
+#endif
 
 	/* ECC is calculated for the whole page (1 step) */
 	nand->ecc.size = mtd->writesize;

index 92d4ec5..eac860d 100644
@@ -141,6 +141,10 @@ struct pmecc_errloc_regs {
 #define PMECC_GF_DIMENSION_13			13
 #define PMECC_GF_DIMENSION_14			14
 
+/* Primitive Polynomial used by PMECC */
+#define PMECC_GF_13_PRIMITIVE_POLY		0x201b
+#define PMECC_GF_14_PRIMITIVE_POLY		0x4443
+
 #define PMECC_INDEX_TABLE_SIZE_512		0x2000
 #define PMECC_INDEX_TABLE_SIZE_1024		0x4000
 

index 375c8a4..6d48252 100644
@@ -565,7 +565,13 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 	macb_writel(macb, TBQP, macb->tx_ring_dma);
 
 	if (macb_is_gem(macb)) {
-#ifdef CONFIG_RGMII
+		/*
+		 * When the GMAC IP with GE feature, this bit is used to
+		 * select interface between RGMII and GMII.
+		 * When the GMAC IP without GE feature, this bit is used
+		 * to select interface between RMII and MII.
+		 */
+#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
 		gem_writel(macb, UR, GEM_BIT(RGMII));
 #else
 		gem_writel(macb, UR, 0);

new file mode 100644
index 0000000..2708097
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d4.h>
+
+char *get_cpu_name()
+{
+	unsigned int extension_id = get_extension_chip_id();
+
+	if (cpu_is_sama5d4())
+		switch (extension_id) {
+		case ARCH_EXID_SAMA5D41:
+			return "SAMA5D41";
+		case ARCH_EXID_SAMA5D42:
+			return "SAMA5D42";
+		case ARCH_EXID_SAMA5D43:
+			return "SAMA5D43";
+		case ARCH_EXID_SAMA5D44:
+			return "SAMA5D44";
+		default:
+			return "Unknown CPU type";
+		}
+	else
+		return "Unknown CPU type";
+}

index e3ebfe0..19bf80b 100644
@@ -65,7 +65,8 @@ int timer_init(void)
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+	gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
+
 	gd->arch.tbu = 0;
 	gd->arch.tbl = 0;
 

index 27331ff..7c1578c 100644
@@ -78,7 +78,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
 #define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
-#ifdef CONFIG_SAMA5D3
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 #define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
 #else
 #define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)

@@ -97,7 +97,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
 #define AT91_PMC_MCKR_CSS_MASK		0x00000003
 
-#ifdef CONFIG_SAMA5D3
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 #define AT91_PMC_MCKR_PRES_1		0x00000000
 #define AT91_PMC_MCKR_PRES_2		0x00000010
 #define AT91_PMC_MCKR_PRES_4		0x00000020

@@ -126,7 +126,7 @@ typedef struct at91_pmc {
 #else
 #define AT91_PMC_MCKR_MDIV_1		0x00000000
 #define AT91_PMC_MCKR_MDIV_2		0x00000100
-#ifdef CONFIG_SAMA5D3
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 #define AT91_PMC_MCKR_MDIV_3		0x00000300
 #endif
 #define AT91_PMC_MCKR_MDIV_4		0x00000200

@@ -136,6 +136,8 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_PLLADIV_1		0x00000000
 #define AT91_PMC_MCKR_PLLADIV_2		0x00001000
 
+#define AT91_PMC_MCKR_H32MXDIV		0x01000000
+
 #define AT91_PMC_IXR_MOSCS		0x00000001
 #define AT91_PMC_IXR_LOCKA		0x00000002
 #define AT91_PMC_IXR_LOCKB		0x00000004

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index d712a0d..bf0a1bd 100644
@@ -27,6 +27,8 @@
 # include <asm/arch/at91cap9.h>
 #elif defined(CONFIG_SAMA5D3)
 # include <asm/arch/sama5d3.h>
+#elif defined(CONFIG_SAMA5D4)
+# include <asm/arch/sama5d4.h>
 #else
 # error "Unsupported AT91 processor"
 #endif

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