ARM: clk-imx6q: fix video divider for rev T0 1.0

The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed to 1. As the table index was wrong, a divider a of 4 could still be requested which implied the clock not to be set properly. This is the root cause of the HDMI not working at high resolution on rev T0 1.0 of the SoC, giving the following error:
mxc_sdc_fb fb.27: timeout when waiting for flip irq

See this thread for details:
https://lists.yoctoproject.org/pipermail/meta-freescale/2014-December/thread.html#11776

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Hi,

This patch has been tested with a Sabrelite rev D (5-9-12).

However I've realized this patch doesn't fix the HDMI at 1080p60 but only resolutions up to 1080p30. As mainline kernel is forcing the highest resolution supported by the monitor it might not work on 1080p60-enable displays. This latter issue is being investigated.

This patch is being integrated into meta-fsl-arm. Fabio suggested to submit this patch already as clearly the array index is currently wrong and "Better to have some HDMI then no HDMI at all":
https://lists.yoctoproject.org/pipermail/meta-freescale/2014-December/011796.html

Thanks,
Gary

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 arch/arm/mach-imx/clk-imx6q.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 4e79da7..2aa1b67 100644
@@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 		post_div_table[1].div = 1;
 		post_div_table[2].div = 1;
 		video_div_table[1].div = 1;
-		video_div_table[2].div = 1;
+		video_div_table[3].div = 1;
 	};
 
 	clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

2.1.3

Hi Gary,

Patch looks good, but just a minot comment: I would suggest removing this line:

as it is not part of mainline.

Hi Fabio,

You are right, this is a good point, let me send a v2.

Thanks,
Gary