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bcm281xx: add support for "USB OTG clock"

PATCH Superseded Steve Rae 3 participants 4 messages Dec 6, 2014 – Dec 9, 2014

Subsystems (3)
Arm (32-bit) Broadcom BCM2711/BCM2835 Arm architecture Broadcom BCM281XX/BCM11XXX/BCM216XX Arm architecture

v2 of 3 Superseded Latest is v3 →

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Steve Rae

author
#0 lore raw

PATCH v2 1/1 bcm281xx: add support for "USB OTG clock"

enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by Steve Rae <[email protected]>

---

Changes in v2:
removed unrelated changes as per Felipe Balbi <[email protected]>

 arch/arm/cpu/armv7/bcm281xx/Makefile        |  1 +
 arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c  | 16 +++++++++++++++
 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c   | 32 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/kona-common/clk-stubs.c  |  5 +++++
 arch/arm/include/asm/arch-bcm281xx/sysmap.h |  2 ++
 arch/arm/include/asm/kona-common/clk.h      |  1 +
 6 files changed, 57 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
arch/arm/cpu/armv7/bcm281xx/Makefile +1 -0
index bd867a2..f24aeb3 100644
@@ -10,3 +10,4 @@ obj-y	+= clk-bcm281xx.o
 obj-y	+= clk-sdio.o
 obj-y	+= clk-bsc.o
 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +16 -0
index d16b99f..7e25255 100644
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
 	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
 	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };

@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
  */
 
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
 	.clk = {
 		.name = "sdio1_ahb_clk",

@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
 	CLK_LK(bsc2),
 	CLK_LK(bsc3),
 	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
 	CLK_LK(sdio1_ahb),
 	CLK_LK(sdio2_ahb),
 	CLK_LK(sdio3_ahb),
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +32 -0
new file mode 100644
index 0000000..b7efd8e
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	int ret;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
arch/arm/cpu/armv7/kona-common/clk-stubs.c +5 -0
index 338e0e4..fa10802 100644
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
 {
 	return 0;
 }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+	return 0;
+}
arch/arm/include/asm/arch-bcm281xx/sysmap.h +2 -0
index 350e7f6..93ebf34 100644
@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR	0x38000000
 #define ESW_CONTRL_BASE_ADDR	0x38200000
 #define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
 #define KONA_MST_CLK_BASE_ADDR	0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR	0x3e011000
 #define PMU_BSC_BASE_ADDR	0x3500d000
arch/arm/include/asm/kona-common/clk.h +1 -0
index 2c7e829..a5e2fd9 100644
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
 #endif
Signature · 1 line
1.8.5
#1 lore raw

PATCH v2 1/1 bcm281xx: add support for "USB OTG clock"

Quoted 4 lines · Steve Rae

enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by Steve Rae <[email protected]>
Reviewed-by Felipe Balbi <[email protected]>
Quoted 146 lines

---

Changes in v2:
removed unrelated changes as per Felipe Balbi <[email protected]>

 arch/arm/cpu/armv7/bcm281xx/Makefile        |  1 +
 arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c  | 16 +++++++++++++++
 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c   | 32 +++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/kona-common/clk-stubs.c  |  5 +++++
 arch/arm/include/asm/arch-bcm281xx/sysmap.h |  2 ++
 arch/arm/include/asm/kona-common/clk.h      |  1 +
 6 files changed, 57 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
arch/arm/cpu/armv7/bcm281xx/Makefile +1 -0
index bd867a2..f24aeb3 100644
@@ -10,3 +10,4 @@ obj-y	+= clk-bcm281xx.o
 obj-y	+= clk-sdio.o
 obj-y	+= clk-bsc.o
 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +16 -0
index d16b99f..7e25255 100644
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
 	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
 	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };

@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
  */
 
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
 	.clk = {
 		.name = "sdio1_ahb_clk",

@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
 	CLK_LK(bsc2),
 	CLK_LK(bsc3),
 	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
 	CLK_LK(sdio1_ahb),
 	CLK_LK(sdio2_ahb),
 	CLK_LK(sdio3_ahb),
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +32 -0
new file mode 100644
index 0000000..b7efd8e
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	int ret;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
arch/arm/cpu/armv7/kona-common/clk-stubs.c +5 -0
index 338e0e4..fa10802 100644
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
 {
 	return 0;
 }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+	return 0;
+}
arch/arm/include/asm/arch-bcm281xx/sysmap.h +2 -0
index 350e7f6..93ebf34 100644
@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR	0x38000000
 #define ESW_CONTRL_BASE_ADDR	0x38200000
 #define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
 #define KONA_MST_CLK_BASE_ADDR	0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR	0x3e011000
 #define PMU_BSC_BASE_ADDR	0x3500d000
arch/arm/include/asm/kona-common/clk.h +1 -0
index 2c7e829..a5e2fd9 100644
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
 #endif
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#2 lore raw

PATCH v2 1/1 bcm281xx: add support for "USB OTG clock"

In reply to Steve Rae

Hi

Il 07/dic/2014 02:24 "Steve Rae" <[email protected]> ha scritto:

Quoted 5 lines

enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by Steve Rae <[email protected]>
Quoted 8 lines

---

Changes in v2:
removed unrelated changes as per Felipe Balbi <[email protected]>

 arch/arm/cpu/armv7/bcm281xx/Makefile        |  1 +
 arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c  | 16 +++++++++++++++
 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c   | 32

+++++++++++++++++++++++++++++

Review

Quoted 7 lines
 arch/arm/cpu/armv7/kona-common/clk-stubs.c  |  5 +++++
 arch/arm/include/asm/arch-bcm281xx/sysmap.h |  2 ++
 arch/arm/include/asm/kona-common/clk.h      |  1 +
 6 files changed, 57 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/bcm281xx/Makefile

Review

Quoted 9 lines

index bd867a2..f24aeb3 100644

arch/arm/cpu/armv7/bcm281xx/Makefile +1 -0
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
 obj-y  += clk-sdio.o
 obj-y  += clk-bsc.o
 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y  += clk-usb-otg.o
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

Review

Quoted 41 lines

index d16b99f..7e25255 100644

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +16 -0
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
        .gate           = SW_ONLY_GATE(0x0360, 20, 4),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
        .gate           = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };

@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
  */
 
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+       .clk = {
+               .name = "usb_otg_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
        .clk = {
                .name = "sdio1_ahb_clk",

@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
        CLK_LK(bsc2),
        CLK_LK(bsc3),
        /* Bus clocks */
+       CLK_LK(usb_otg_ahb),
        CLK_LK(sdio1_ahb),
        CLK_LK(sdio2_ahb),
        CLK_LK(sdio3_ahb),
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

Quoted 22 lines

new file mode 100644
index 0000000..b7efd8e

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +17 -0
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+       int ret;
+       char *ahbstr;
+

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c line 27

Quoted 10 lines
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +10 -0
+       switch ((u32) base) {
+       case HSOTG_BASE_ADDR:
+               ahbstr = "usb_otg_ahb_clk";
+               break;
+       default:
+               printf("%s: base 0x%p not found\n", __func__, base);
+               return -EINVAL;
+       }
+
+       ret = clk_get_and_enable(ahbstr);

return clk_get..... ?

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c line 32

Quoted 5 lines
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +5 -0
+       if (ret)
+               return ret;
+
+       return 0;
+}

What is usage of this file?

Why don't enable with the string?

Michael

Review

Quoted 1 line
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/kona-common/clk-stubs.c

arch/arm/cpu/armv7/kona-common/clk-stubs.c int __weak clk_bsc_enable(void *base, u32 rate, u32

Quoted 4 lines

index 338e0e4..fa10802 100644

arch/arm/cpu/armv7/kona-common/clk-stubs.c +0 -0
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32

*actual_ratep)

Review

Quoted 9 lines
arch/arm/cpu/armv7/kona-common/clk-stubs.c +5 -0
 {
        return 0;
 }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+       return 0;
+}
(quoted diff) +0 -0

b/arch/arm/include/asm/arch-bcm281xx/sysmap.h

Review

Quoted 13 lines

index 350e7f6..93ebf34 100644

arch/arm/include/asm/arch-bcm281xx/sysmap.h +2 -0
@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR     0x38000000
 #define ESW_CONTRL_BASE_ADDR   0x38200000
 #define GPIO2_BASE_ADDR                0x35003000
+#define HSOTG_BASE_ADDR                0x3f120000
+#define HSOTG_CTRL_BASE_ADDR   0x3f130000
 #define KONA_MST_CLK_BASE_ADDR 0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
 #define PMU_BSC_BASE_ADDR      0x3500d000
(quoted diff) +0 -0

b/arch/arm/include/asm/kona-common/clk.h

Quoted 17 lines

index 2c7e829..a5e2fd9 100644

arch/arm/include/asm/kona-common/clk.h +1 -1
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
 #endif
--

1.8.5

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author
#3 lore raw

PATCH v2 1/1 bcm281xx: add support for "USB OTG clock"

Quoted 103 lines · Michael Trimarchi

Hi

Il 07/dic/2014 02:24 "Steve Rae" <[email protected]> ha scritto:

Quoted 5 lines

enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by Steve Rae <[email protected]>
Quoted 8 lines

---

Changes in v2:
removed unrelated changes as per Felipe Balbi <[email protected]>

  arch/arm/cpu/armv7/bcm281xx/Makefile        |  1 +
  arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c  | 16 +++++++++++++++
  arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c   | 32

+++++++++++++++++++++++++++++

Review

Quoted 7 lines
  arch/arm/cpu/armv7/kona-common/clk-stubs.c  |  5 +++++
  arch/arm/include/asm/arch-bcm281xx/sysmap.h |  2 ++
  arch/arm/include/asm/kona-common/clk.h      |  1 +
  6 files changed, 57 insertions(+)

create mode 100644 arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

(quoted diff) +0 -0

b/arch/arm/cpu/armv7/bcm281xx/Makefile

Review

Quoted 9 lines

index bd867a2..f24aeb3 100644

arch/arm/cpu/armv7/bcm281xx/Makefile +1 -0
@@ -10,3 +10,4 @@ obj-y += clk-bcm281xx.o
  obj-y  += clk-sdio.o
  obj-y  += clk-bsc.o
  obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y  += clk-usb-otg.o
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c

Review

Quoted 41 lines

index d16b99f..7e25255 100644

arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +16 -0
@@ -209,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
         .gate           = SW_ONLY_GATE(0x0360, 20, 4),
  };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
  static struct bus_clk_data sdio1_ahb_data = {
         .gate           = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
  };

@@ -331,6 +335,17 @@ static struct ccu_clock esub_ccu_clk = {
   */
 
  /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+       .clk = {
+               .name = "usb_otg_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &usb_otg_ahb_data,
+};
+
  static struct bus_clock sdio1_ahb_clk = {
         .clk = {
                 .name = "sdio1_ahb_clk",

@@ -541,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
         CLK_LK(bsc2),
         CLK_LK(bsc3),
         /* Bus clocks */
+       CLK_LK(usb_otg_ahb),
         CLK_LK(sdio1_ahb),
         CLK_LK(sdio2_ahb),
         CLK_LK(sdio3_ahb),
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c

Quoted 26 lines

new file mode 100644
index 0000000..b7efd8e

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +21 -0
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+       int ret;
+       char *ahbstr;
+
+       switch ((u32) base) {
+       case HSOTG_BASE_ADDR:
+               ahbstr = "usb_otg_ahb_clk";
+               break;
Quoted 9 lines

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c line 27

Quoted 6 lines
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +6 -0
+       default:
+               printf("%s: base 0x%p not found\n", __func__, base);
+               return -EINVAL;
+       }
+
+       ret = clk_get_and_enable(ahbstr);

return clk_get..... ?

Thanks - see [v3]

Quoted 9 lines

arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c line 32

Quoted 5 lines
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c new file +5 -0
+       if (ret)
+               return ret;
+
+       return 0;
+}

What is usage of this file?

Why don't enable with the string?

this "USB OTG clk" is enabled by the "fastboot initialization code" - which is in a parallel set of patches.....
(I'm trying to not submit an overwhelming set of changes....) Thanks, Steve

Quoted 52 lines

Michael

Review

Quoted 1 line
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/kona-common/clk-stubs.c

arch/arm/cpu/armv7/kona-common/clk-stubs.c int __weak clk_bsc_enable(void *base, u32 rate, u32

Quoted 4 lines

index 338e0e4..fa10802 100644

arch/arm/cpu/armv7/kona-common/clk-stubs.c +0 -0
@@ -19,3 +19,8 @@ int __weak clk_bsc_enable(void *base, u32 rate, u32

*actual_ratep)

Review

Quoted 9 lines
arch/arm/cpu/armv7/kona-common/clk-stubs.c +5 -0
  {
         return 0;
  }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+       return 0;
+}
(quoted diff) +0 -0

b/arch/arm/include/asm/arch-bcm281xx/sysmap.h

Review

Quoted 13 lines

index 350e7f6..93ebf34 100644

arch/arm/include/asm/arch-bcm281xx/sysmap.h +2 -0
@@ -13,6 +13,8 @@
  #define ESUB_CLK_BASE_ADDR     0x38000000
  #define ESW_CONTRL_BASE_ADDR   0x38200000
  #define GPIO2_BASE_ADDR                0x35003000
+#define HSOTG_BASE_ADDR                0x3f120000
+#define HSOTG_CTRL_BASE_ADDR   0x3f130000
  #define KONA_MST_CLK_BASE_ADDR 0x3f001000
  #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
  #define PMU_BSC_BASE_ADDR      0x3500d000
(quoted diff) +0 -0

b/arch/arm/include/asm/kona-common/clk.h

Quoted 17 lines

index 2c7e829..a5e2fd9 100644

arch/arm/include/asm/kona-common/clk.h +1 -1
@@ -25,5 +25,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
  struct clk *clk_get_parent(struct clk *clk);
  int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
  int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
 
  #endif
--

1.8.5

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