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arm: ls102xa: Add NAND boot support for LS1021AQDS board

PATCH Superseded Alison Wang 3 participants 3 messages Dec 6, 2014 – Dec 9, 2014

Subsystems (3)
Arm (32-bit) Memory technology devices (MTD) NAND flash

v4 of 5 Superseded Latest is v5 →

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Alison Wang

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#0 lore raw

PATCH v4 9/9 arm: ls102xa: Add NAND boot support for LS1021AQDS board

This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by Prabhakar Kushwaha <[email protected]>
Signed-off-by Alison Wang <[email protected]>

---
Change log:
v4: Use some defines instead of the magic numbers.
v3: New file.

 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 ++
 board/freescale/ls1021aqds/MAINTAINERS            |  1 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 16 +++++
 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg   |  7 +++
 configs/ls1021aqds_nand_defconfig                 |  4 ++
 drivers/mtd/nand/fsl_ifc_spl.c                    | 10 ++++
 include/configs/ls1021aqds.h                      | 72 +++++++++++++++++++++++
 8 files changed, 116 insertions(+)
 create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
 create mode 100644 configs/ls1021aqds_nand_defconfig
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
index ba86eea..8318c91 100644
@@ -13,6 +13,7 @@
 #define OCRAM_SIZE				0x00020000
 
 #define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20200000
 
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +5 -0
index b0c267c..3af63f8 100644
@@ -29,6 +29,11 @@
 #define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
 #define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
 
+#define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000
+
+#define DCFG_DCSR_PORCR1		0x20000
+
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	unsigned long freq_systembus;
board/freescale/ls1021aqds/MAINTAINERS +1 -0
index 962176b..b7d85dc 100644
@@ -7,3 +7,4 @@ F:	configs/ls1021aqds_nor_defconfig
 F:	configs/ls1021aqds_ddr4_nor_defconfig
 F:	configs/ls1021aqds_nor_SECURE_BOOT_defconfig
 F:	configs/ls1021aqds_sdcard_defconfig
+F:	configs/ls1021aqds_nand_defconfig
board/freescale/ls1021aqds/ls1021aqds.c +16 -0
index bb1ec72..a8e6276 100644
@@ -172,6 +172,22 @@ void board_init_f(ulong dummy)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
+#ifdef CONFIG_NAND_BOOT
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 porsr1, pinctl;
+
+	/*
+	 * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
+	 * This workaround changes RCW source to make all signals enabled.
+	 */
+	porsr1 = in_be32(&gur->porsr1);
+	pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+		 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+	out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + DCFG_DCSR_PORCR1),
+		 pinctl);
+#endif
+
 	/* Set global data pointer */
 	gd = &gdata;
board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg new file +7 -0
new file mode 100644
index 0000000..222c71d
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
configs/ls1021aqds_nand_defconfig new file +4 -0
new file mode 100644
index 0000000..dad5274
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
drivers/mtd/nand/fsl_ifc_spl.c +10 -0
index e336cb1..fb827c5 100644
@@ -254,3 +254,13 @@ void nand_boot(void)
 	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 	uboot();
 }
+
+#ifndef CONFIG_SPL_NAND_INIT
+void nand_init(void)
+{
+}
+
+void nand_deselect(void)
+{
+}
+#endif
include/configs/ls1021aqds.h +72 -0

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Signature · 1 line
2.1.0.27.g96db324
#1 lore raw

PATCH v4 9/9 arm: ls102xa: Add NAND boot support for LS1021AQDS board

Quoted 29 lines · Alison Wang

This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by Prabhakar Kushwaha <[email protected]>
Signed-off-by Alison Wang <[email protected]>

---
Change log:
v4: Use some defines instead of the magic numbers.
v3: New file.

 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 ++
 board/freescale/ls1021aqds/MAINTAINERS            |  1 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 16 +++++
 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg   |  7 +++
 configs/ls1021aqds_nand_defconfig                 |  4 ++
 drivers/mtd/nand/fsl_ifc_spl.c                    | 10 ++++
 include/configs/ls1021aqds.h                      | 72 +++++++++++++++++++++++
 8 files changed, 116 insertions(+)
 create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
 create mode 100644 configs/ls1021aqds_nand_defconfig
arch/arm/include/asm/arch-ls102xa/config.h +0 -0
index ba86eea..8318c91 100644

arch/arm/include/asm/arch-ls102xa/config.h line 16

Quoted 4 lines
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
@@ -13,6 +13,7 @@
 #define OCRAM_SIZE				0x00020000
 
 #define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20200000

This line is conflict with this patch http://patchwork.ozlabs.org/patch/402218/.
Which one is correct?

York

#2 lore raw

PATCH v4 9/9 arm: ls102xa: Add NAND boot support for LS1021AQDS board

Refer to "Table 5-1. LS1 memory map" in "LS1 SoC Architecture Specification". It shows that:
Start Address: 0x200000000 Size: 16MB DCSR

Or, see the dcsr node in arch/arm/boot/dts/ls1021a.dtsi in Linux.

Thanks,
Chenhui
________________________________________
From: York Sun <[email protected]>
Sent: Tuesday, December 9, 2014 4:53
To: Wang Huan-B18965; u-boot at lists.denx.de; Jin Zhengxiong-R64188; Zhao Chenhui-B35336
Subject: Re: [PATCH v4 9/9] arm: ls102xa: Add NAND boot support for LS1021AQDS board

Quoted 29 lines · Alison Wang

This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by Prabhakar Kushwaha <[email protected]>
Signed-off-by Alison Wang <[email protected]>

---
Change log:
v4: Use some defines instead of the magic numbers.
v3: New file.

 arch/arm/include/asm/arch-ls102xa/config.h        |  1 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 ++
 board/freescale/ls1021aqds/MAINTAINERS            |  1 +
 board/freescale/ls1021aqds/ls1021aqds.c           | 16 +++++
 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg   |  7 +++
 configs/ls1021aqds_nand_defconfig                 |  4 ++
 drivers/mtd/nand/fsl_ifc_spl.c                    | 10 ++++
 include/configs/ls1021aqds.h                      | 72 +++++++++++++++++++++++
 8 files changed, 116 insertions(+)
 create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
 create mode 100644 configs/ls1021aqds_nand_defconfig
arch/arm/include/asm/arch-ls102xa/config.h +0 -0
index ba86eea..8318c91 100644

arch/arm/include/asm/arch-ls102xa/config.h line 16

Quoted 4 lines
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
@@ -13,6 +13,7 @@
 #define OCRAM_SIZE                           0x00020000
 
 #define CONFIG_SYS_IMMR                              0x01000000
+#define CONFIG_SYS_DCSRBAR                   0x20200000

This line is conflict with this patch http://patchwork.ozlabs.org/patch/402218/.
Which one is correct?

York