clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

PATCH In review Krzysztof Kozlowski 6 participants 13 messages Dec 5, 2014 – Jan 2, 2015

Subsystems (3)

Common clk Arm Samsung Exynos Samsung SoC clock drivers

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Krzysztof Kozlowski

author

2014-12-05 14:15 UTC #0 lore raw

PATCH 1/1 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.

This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.

The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.

Add a workaround for this by enabling the 'mau_epll' clock in probe.

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

drivers/clk/samsung/clk-exynos-audss.c +28 -1

index acce708ace18..0916a81fa932 100644
@@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock);
 static struct clk **clk_table;
 static void __iomem *reg_base;
 static struct clk_onecell_data clk_data;
+/*
+ * On Exynos5420 this will be a clock which has to be enabled before any
+ * access to audss registers. Typically a child of EPLL.
+ *
+ * On other platforms this will be -ENODEV.
+ */
+static struct clk *epll;
 
 #define ASS_CLK_SRC 0x0
 #define ASS_CLK_DIV 0x4

@@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failed to map audss registers\n");
 		return PTR_ERR(reg_base);
 	}
+	/* EPLL don't have to be enabled for boards other than Exynos5420 */
+	epll = ERR_PTR(-ENODEV);
 
 	clk_table = devm_kzalloc(&pdev->dev,
 				sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,

@@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
 	pll_in = devm_clk_get(&pdev->dev, "pll_in");
 	if (!IS_ERR(pll_ref))
 		mout_audss_p[0] = __clk_get_name(pll_ref);
-	if (!IS_ERR(pll_in))
+	if (!IS_ERR(pll_in)) {
 		mout_audss_p[1] = __clk_get_name(pll_in);
+
+		if (variant == TYPE_EXYNOS5420) {
+			epll = pll_in;
+
+			ret = clk_prepare_enable(epll);
+			if (ret) {
+				dev_err(&pdev->dev,
+						"failed to prepare the epll clock\n");
+				return ret;
+			}
+		}
+	}
 	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
 				mout_audss_p, ARRAY_SIZE(mout_audss_p),
 				CLK_SET_RATE_NO_REPARENT,

@@ -203,6 +224,9 @@ unregister:
 			clk_unregister(clk_table[i]);
 	}
 
+	if (!IS_ERR(epll))
+		clk_disable_unprepare(epll);
+
 	return ret;
 }

@@ -217,6 +241,9 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
 			clk_unregister(clk_table[i]);
 	}
 
+	if (!IS_ERR(epll))
+		clk_disable_unprepare(epll);
+
 	return 0;
 }

Signature · 1 line

1.9.1

Krzysztof Kozlowski

author

2014-12-09 12:59 UTC #1 lore raw

Quoted 15 lines · Krzysztof Kozlowski

Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.

Quoted 6 lines

Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).

This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223

Any comments on this?

Best regards,
Krzysztof

Quoted 69 lines

drivers/clk/samsung/clk-exynos-audss.c +28 -1

index acce708ace18..0916a81fa932 100644
@@ -29,6 +29,13 @@ static DEFINE_SPINLOCK(lock);
 static struct clk **clk_table;
 static void __iomem *reg_base;
 static struct clk_onecell_data clk_data;
+/*
+ * On Exynos5420 this will be a clock which has to be enabled before any
+ * access to audss registers. Typically a child of EPLL.
+ *
+ * On other platforms this will be -ENODEV.
+ */
+static struct clk *epll;
 
 #define ASS_CLK_SRC 0x0
 #define ASS_CLK_DIV 0x4

@@ -98,6 +105,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "failed to map audss registers\n");
 		return PTR_ERR(reg_base);
 	}
+	/* EPLL don't have to be enabled for boards other than Exynos5420 */
+	epll = ERR_PTR(-ENODEV);
 
 	clk_table = devm_kzalloc(&pdev->dev,
 				sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,

@@ -115,8 +124,20 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
 	pll_in = devm_clk_get(&pdev->dev, "pll_in");
 	if (!IS_ERR(pll_ref))
 		mout_audss_p[0] = __clk_get_name(pll_ref);
-	if (!IS_ERR(pll_in))
+	if (!IS_ERR(pll_in)) {
 		mout_audss_p[1] = __clk_get_name(pll_in);
+
+		if (variant == TYPE_EXYNOS5420) {
+			epll = pll_in;
+
+			ret = clk_prepare_enable(epll);
+			if (ret) {
+				dev_err(&pdev->dev,
+						"failed to prepare the epll clock\n");
+				return ret;
+			}
+		}
+	}
 	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
 				mout_audss_p, ARRAY_SIZE(mout_audss_p),
 				CLK_SET_RATE_NO_REPARENT,

@@ -203,6 +224,9 @@ unregister:
 			clk_unregister(clk_table[i]);
 	}
 
+	if (!IS_ERR(epll))
+		clk_disable_unprepare(epll);
+
 	return ret;
 }

@@ -217,6 +241,9 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
 			clk_unregister(clk_table[i]);
 	}
 
+	if (!IS_ERR(epll))
+		clk_disable_unprepare(epll);
+
 	return 0;
 }

Sylwester Nawrocki

maintainer Acked-by

2014-12-09 13:18 UTC #2 lore raw

Quoted 27 lines · Krzysztof Kozlowski

Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).

Quoted 5 lines

This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?

The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?

Quoted 1 line

From my side:

Acked-by Sylwester Nawrocki <[email protected]>

Signature · 2 lines

Thanks,
Sylwester

Javier Martinez Canillas

Tested-by

2014-12-09 14:05 UTC #3 lore raw

Hello,

Quoted 11 lines · Sylwester Nawrocki

Quoted 6 lines
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?

This patch fixes the boot failure bug on my Exynos5420 Peach Pit Chromebook and I've audio working as well.

Quoted 4 lines

From my side:
Acked-by Sylwester Nawrocki <[email protected]>

Tested-by Javier Martinez Canillas <[email protected]>

Best regards,
Javier

Kevin Hilman

Tested-by

2014-12-10 17:35 UTC #4 lore raw

In reply to Sylwester Nawrocki

Quoted 32 lines · Sylwester Nawrocki

Quoted 31 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223

Quoted 5 lines

Quoted 1 line
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?

I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.

Tested-by Kevin Hilman <[email protected]>

Kevin

Kevin Hilman

2014-12-15 22:26 UTC #5 lore raw

Quoted 40 lines · Kevin Hilman

Quoted 32 lines · Sylwester Nawrocki
Quoted 31 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Quoted 5 lines
Quoted 1 line
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?

Quoted 5 lines

I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>

What's the status of this patch? linux-next is still broken for several Exynos5 platforms without this fix.

Kevin

Krzysztof Kozlowski

author

2014-12-16 08:20 UTC #6 lore raw

Quoted 42 lines · Kevin Hilman

Quoted 40 lines · Kevin Hilman
Quoted 37 lines · Sylwester Nawrocki
Quoted 27 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
Quoted 5 lines
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?

Quoted 8 lines

Quoted 5 lines
I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>
What's the status of this patch? linux-next is still broken for several Exynos5 platforms without this fix.

I believe not only next is broken but also current mainline because runtime PM for pl330 was merged yesterday...

The patch received two tested-bys (Kevin's and Javier's) and Sylwester's ack.

Mike, could you pick the patch and send it to Linus after rc1?

Best regards,
Krzysztof

Mike Turquette

2014-12-17 15:23 UTC #7 lore raw

Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)

Quoted 52 lines · Kevin Hilman

Quoted 42 lines
Quoted 40 lines · Kevin Hilman
Quoted 37 lines · Sylwester Nawrocki
Quoted 27 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
Quoted 5 lines
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?
Quoted 8 lines
Quoted 5 lines
I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>
What's the status of this patch? linux-next is still broken for several Exynos5 platforms without this fix.

Quoted 7 lines

I believe not only next is broken but also current mainline because runtime PM for pl330 was merged yesterday...
The patch received two tested-bys (Kevin's and Javier's) and Sylwester's ack.
Mike, could you pick the patch and send it to Linus after rc1?

Will do.

Regards,
Mike

Quoted 4 lines

Best regards,
Krzysztof

Mike Turquette

2014-12-18 06:58 UTC #8 lore raw

Quoting Mike Turquette (2014-12-17 07:23:22)

Quoted 56 lines

Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
Quoted 55 lines · Kevin Hilman
Quoted 42 lines
Quoted 40 lines · Kevin Hilman
Quoted 37 lines · Sylwester Nawrocki
Quoted 27 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
Quoted 5 lines
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?
Quoted 8 lines
Quoted 5 lines
I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>
What's the status of this patch? linux-next is still broken for several Exynos5 platforms without this fix.
I believe not only next is broken but also current mainline because runtime PM for pl330 was merged yesterday...

Quoted 6 lines

Quoted 4 lines
The patch received two tested-bys (Kevin's and Javier's) and Sylwester's ack.
Mike, could you pick the patch and send it to Linus after rc1?
Will do.

To be clear, I pulled this into clk-next towards -rc1, so it won't need to go through as an -rc fix.

Regards,
Mike

Quoted 8 lines

Regards,
Mike
Quoted 4 lines
Best regards,
Krzysztof

Kevin Hilman

2014-12-18 22:10 UTC #9 lore raw

Quoted 60 lines · Mike Turquette

Quoting Mike Turquette (2014-12-17 07:23:22)
Quoted 59 lines
Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
Quoted 58 lines · Kevin Hilman
Quoted 42 lines
Quoted 40 lines · Kevin Hilman
Quoted 37 lines · Sylwester Nawrocki
Quoted 27 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
Quoted 6 lines
Quoted 6 lines
Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
Quoted 5 lines
This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?
Quoted 8 lines
Quoted 5 lines
I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>
What's the status of this patch? linux-next is still broken for several Exynos5 platforms without this fix.
I believe not only next is broken but also current mainline because runtime PM for pl330 was merged yesterday...
The patch received two tested-bys (Kevin's and Javier's) and Sylwester's ack.

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Mike, could you pick the patch and send it to Linus after rc1?
Will do.
To be clear, I pulled this into clk-next towards -rc1, so it won't need to go through as an -rc fix.

This hit today's linux-next, and exynos5 platforms are happily booting again. Thanks!

Kevin

Mike Turquette

2014-12-18 22:32 UTC #10 lore raw

PATCH 1/1 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated

Quoting Kevin Hilman (2014-12-18 14:10:34)

Quoted 63 lines · Mike Turquette

Quoted 62 lines
Quoting Mike Turquette (2014-12-17 07:23:22)
Quoted 61 lines
Quoting Krzysztof Kozlowski (2014-12-16 00:20:15)
Quoted 59 lines · Kevin Hilman
Quoted 42 lines
Quoted 40 lines · Kevin Hilman
Quoted 37 lines · Sylwester Nawrocki
Quoted 27 lines · Krzysztof Kozlowski
Quoted 15 lines · Krzysztof Kozlowski
Quoted 15 lines
Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block.
This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll.
The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated.
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Add a workaround for this by enabling the 'mau_epll' clock in probe.
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 drivers/clk/samsung/clk-exynos-audss.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)
Sorry for pinging so quick but merge window is open and it looks like booting Exynos542x boards will be broken (because pl330 will no longer hold adma clock enabled so whole audss domain will be gated).
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This is a non-intrusive workaround for that issue, as wanted by Sylwester:
https://lkml.org/lkml/2014/12/5/223
Any comments on this?
The patch looks OK to me, it would be good though if someone else has confirmed it fixes the bug. I don't have any clock patches queued at the moment. Perhaps you could apply it directly, Mike ?
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I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>
What's the status of this patch? linux-next is still broken for several Exynos5 platforms without this fix.
I believe not only next is broken but also current mainline because runtime PM for pl330 was merged yesterday...
The patch received two tested-bys (Kevin's and Javier's) and Sylwester's ack.
Mike, could you pick the patch and send it to Linus after rc1?

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Will do.
To be clear, I pulled this into clk-next towards -rc1, so it won't need to go through as an -rc fix.
This hit today's linux-next, and exynos5 platforms are happily booting again. Thanks!

Thanks for testing it Kevin.

Regards,
Mike

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Kevin

Paolo Pisati

2014-12-24 16:36 UTC #11 lore raw

In reply to Kevin Hilman

Quoted 6 lines · Kevin Hilman

I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>

does audio work on your peach pi? because kernel boots fine, but i can't get any audio out of it

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bye,
p.

Javier Martinez Canillas

2015-01-02 09:49 UTC #12 lore raw

Hello Paolo,

Quoted 11 lines · Paolo Pisati

Quoted 6 lines · Kevin Hilman
I confirm it fixes the boot hang in linux-next (next-20141210) on my exynos5800-peach-pi and exynos5420-arndale-octa. Tested both exynos_defconfig and multi_v7_defconfig.
Tested-by Kevin Hilman <[email protected]>
does audio work on your peach pi? because kernel boots fine, but i can't get any audio out of it

Audio is not working for me as well. I said before that audio was working because I tested with the headphone audio jack but I forgot that I had re-introduced the clk_ignore_unused parameter to my kernel command line to test the mmc/sdio wifi. Without clk_ignore_unused, I have no audio.

I see that the downstream daisy_max98095 ASoC driver in the ChromeOS tree grabs some clocks that the mainline sound/soc/samsung/snow.c driver so it it seems that at least that is missing and may explain why it is working with clk_ignore_unused.

Best regards,
Javier