sun8i: Remaining sun8i SPL support patches

PATCH New Hans de Goede 4 participants 10 messages Dec 20, 2014 – Dec 22, 2014

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Arm (32-bit) Arm/Allwinner sunXi SoC support

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Hans de Goede

author

2014-12-20 11:29 UTC #0 lore raw

v2 cover sun8i: Remaining sun8i SPL support patches

Hi Ian, et al,

Here is a v2 of the A23 patches which did not pass review in v1 (so not a resend of the whole set).

Changes:
-"sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/"
-Not only change the prefix of the P2WI gpio mux defines from SUNXI to
SUN6I, but also the prefix of the SUN6I_P2WI_BASE address define
-"sunxi: Add support for the rsb (Reduced Serial Bus)"
-Drop sun6i / sun8i comments from SUN6I_P2WI_BASE / SUNXI_RSB_BASE defines,
use the prefix instead to make clear for which SoC family they are valid
-"sun8i: Add dram initialization support"
-white space fixes
-Add a comment that the ddr phy bits look a lot like the ddr phy found
in the TI Keystone2 and add a link to the TI Keystone2 documentation for future reference / cleanup work
-Split out the Ippo_q8h_v5_defconfig patches into their own patch

Regards,

Hans

p.s.

I also still need an ack for "sunxi: Fill memory before comparing it when doing dram init on sun6i", as you had some questions on that when reviewing v1 of the set.

Hans de Goede

author

2014-12-20 11:29 UTC #1 lore raw

PATCH v2 1/4 sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/

The p2wi interface is only available on sun6i, adjust the gpio pinmux and base address defines for it to reflect this.

Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/p2wi.c        | 14 +++++++-------
 arch/arm/include/asm/arch-sunxi/cpu.h  |  2 +-
 arch/arm/include/asm/arch-sunxi/gpio.h |  4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

arch/arm/cpu/armv7/sunxi/p2wi.c +7 -7

index 48613bd..26a9cfc 100644
@@ -26,13 +26,13 @@
 
 void p2wi_init(void)
 {
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 
 	/* Enable p2wi and PIO clk, and de-assert their resets */
 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
 
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
 
 	/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
 	writel(P2WI_CTRL_RESET, &p2wi->ctrl);

@@ -43,7 +43,7 @@ void p2wi_init(void)
 
 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
 {
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 	unsigned long tmo = timer_get_us() + 1000000;
 
 	writel(P2WI_PM_DEV_ADDR(slave_addr) |

@@ -62,7 +62,7 @@ int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
 
 static int p2wi_await_trans(void)
 {
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 	unsigned long tmo = timer_get_us() + 1000000;
 	int ret;
 	u8 reg;

@@ -88,7 +88,7 @@ static int p2wi_await_trans(void)
 
 int p2wi_read(const u8 addr, u8 *data)
 {
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 	int ret;
 
 	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);

@@ -105,7 +105,7 @@ int p2wi_read(const u8 addr, u8 *data)
 
 int p2wi_write(const u8 addr, u8 data)
 {
-	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+	struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 
 	writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
 	writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);

arch/arm/include/asm/arch-sunxi/cpu.h +1 -1

index 9500262..adf203a 100644
@@ -128,7 +128,7 @@
 #define SUN6I_CPUCFG_BASE		0x01f01c00
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
-#define SUNXI_P2WI_BASE			0x01f03400
+#define SUN6I_P2WI_BASE			0x01f03400
 
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE			0x3f500000

arch/arm/include/asm/arch-sunxi/gpio.h +2 -2

index 366c0dc..9f972ce 100644
@@ -173,8 +173,8 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPI4_SDC3		2
 
-#define SUNXI_GPL0_R_P2WI_SCK	3
-#define SUNXI_GPL1_R_P2WI_SDA	3
+#define SUN6I_GPL0_R_P2WI_SCK	3
+#define SUN6I_GPL1_R_P2WI_SDA	3
 
 #define SUN8I_GPL2_R_UART_TX	2
 #define SUN8I_GPL3_R_UART_RX	2

Signature · 1 line

2.1.0

Hans de Goede

author

2014-12-20 11:29 UTC #2 lore raw

PATCH v2 2/4 sunxi: Add support for the rsb (Reduced Serial Bus)

In reply to Hans de Goede

sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual.

This commit adds support for this based on the rsb driver from the allwinner u-boot sources.

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/Makefile      |   1 +
 arch/arm/cpu/armv7/sunxi/rsb.c         | 158 +++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/cpu.h  |   1 +
 arch/arm/include/asm/arch-sunxi/gpio.h |   2 +
 arch/arm/include/asm/arch-sunxi/prcm.h |   3 +-
 arch/arm/include/asm/arch-sunxi/rsb.h  |  55 ++++++++++++
 6 files changed, 219 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h

arch/arm/cpu/armv7/sunxi/Makefile +1 -0

index 1337b60..3e8975a 100644
@@ -15,6 +15,7 @@ obj-y	+= pinmux.o
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN8I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN6I)	+= p2wi.o
+obj-$(CONFIG_MACH_SUN8I)	+= rsb.o
 obj-$(CONFIG_MACH_SUN4I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o

arch/arm/cpu/armv7/sunxi/rsb.c new file +158 -0

158 lines not on this page · raw message

arch/arm/include/asm/arch-sunxi/cpu.h +1 -0

index adf203a..bcfa00d 100644
@@ -129,6 +129,7 @@
 #define SUNXI_R_UART_BASE		0x01f02800
 #define SUNXI_R_PIO_BASE		0x01f02c00
 #define SUN6I_P2WI_BASE			0x01f03400
+#define SUNXI_RSB_BASE			0x01f03400
 
 /* CoreSight Debug Module */
 #define SUNXI_CSDM_BASE			0x3f500000

arch/arm/include/asm/arch-sunxi/gpio.h +2 -0

index 9f972ce..6623f15 100644
@@ -176,6 +176,8 @@ enum sunxi_gpio_number {
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
 
+#define SUN8I_GPL0_R_RSB_SCK	2
+#define SUN8I_GPL1_R_RSB_SDA	2
 #define SUN8I_GPL2_R_UART_TX	2
 #define SUN8I_GPL3_R_UART_RX	2

arch/arm/include/asm/arch-sunxi/prcm.h +2 -1

index 88de1ff..82ed541 100644
@@ -50,7 +50,8 @@
 #define PRCM_APB0_GATE_PIO (0x1 << 0)
 #define PRCM_APB0_GATE_IR (0x1 << 1)
 #define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
-#define PRCM_APB0_GATE_P2WI (0x1 << 3)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)		/* sun6i */
+#define PRCM_APB0_GATE_RSB (0x1 << 3)		/* sun8i */
 #define PRCM_APB0_GATE_UART (0x1 << 4)
 #define PRCM_APB0_GATE_1WIRE (0x1 << 5)
 #define PRCM_APB0_GATE_I2C (0x1 << 6)

arch/arm/include/asm/arch-sunxi/rsb.h new file +55 -0

55 lines not on this page · raw message

Signature · 1 line

2.1.0

Ian Campbell

2014-12-22 13:10 UTC #3 lore raw

PATCH v2 2/4 sunxi: Add support for the rsb (Reduced Serial Bus)

Quoted 8 lines · Hans de Goede

sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner u-boot sources.
Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Hans de Goede

author

2014-12-20 11:29 UTC #4 lore raw

PATCH v2 3/4 sun8i: Add dram initialization support

In reply to Hans de Goede

Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0.

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/cpu/armv7/sunxi/Makefile             |   1 +
 arch/arm/cpu/armv7/sunxi/board.c              |   3 +-
 arch/arm/cpu/armv7/sunxi/dram_sun8i.c         | 346 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |   4 +
 arch/arm/include/asm/arch-sunxi/dram.h        |   2 +
 arch/arm/include/asm/arch-sunxi/dram_sun8i.h  | 266 ++++++++++++++++++++
 board/sunxi/Kconfig                           |   3 +-
 include/configs/sun8i.h                       |   2 +
 8 files changed, 625 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun8i.c
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun8i.h

arch/arm/cpu/armv7/sunxi/Makefile +1 -0

index 3e8975a..1e89937 100644
@@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
+obj-$(CONFIG_MACH_SUN8I)	+= dram_sun8i.o
 ifdef CONFIG_SPL_FEL
 obj-y	+= start.o
 endif

arch/arm/cpu/armv7/sunxi/board.c +2 -1

index 9b3e80c..bc98c56 100644
@@ -114,7 +114,8 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
-#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+#if defined CONFIG_SPL_BUILD && \
+		(defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
 	/* Magic (undocmented) value taken from boot0, without this DRAM
 	 * access gets messed up (seems cache related) */
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);

arch/arm/cpu/armv7/sunxi/dram_sun8i.c new file +346 -0

346 lines not on this page · raw message

arch/arm/include/asm/arch-sunxi/clock_sun6i.h +4 -0

index 7d61216..45a199c 100644
@@ -273,7 +273,11 @@ struct sunxi_ccm_reg {
 #define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
 #define CCM_HDMI_CTRL_GATE		(0x1 << 31)
 
+#ifndef CONFIG_MACH_SUN8I
 #define MBUS_CLK_DEFAULT		0x81000001 /* PLL6 / 2 */
+#else
+#define MBUS_CLK_DEFAULT		0x81000003 /* PLL6 / 4 */
+#endif
 
 #define CCM_PLL5_PATTERN		0xd1303333

arch/arm/include/asm/arch-sunxi/dram.h +2 -0

index a8a37d5..8d78029 100644
@@ -18,6 +18,8 @@
 /* dram regs definition */
 #if defined(CONFIG_MACH_SUN6I)
 #include <asm/arch/dram_sun6i.h>
+#elif defined(CONFIG_MACH_SUN8I)
+#include <asm/arch/dram_sun8i.h>
 #else
 #include <asm/arch/dram_sun4i.h>
 #endif

arch/arm/include/asm/arch-sunxi/dram_sun8i.h new file +266 -0

266 lines not on this page · raw message

board/sunxi/Kconfig +2 -1

index 5bb2f58..5a88ba0 100644
@@ -29,10 +29,11 @@ config MACH_SUN7I
 config MACH_SUN8I
 	bool "sun8i (Allwinner A23)"
 	select CPU_V7
+	select SUPPORT_SPL
 
 endchoice
 
-if MACH_SUN6I
+if MACH_SUN6I || MACH_SUN8I
 
 config DRAM_CLK
 	int "sun6i dram clock speed"

include/configs/sun8i.h +2 -0

index 6f1fc48..792422d 100644
@@ -12,6 +12,8 @@
 /*
  * A23 specific configuration
  */
+#define CONFIG_CLK_FULL_SPEED	1008000000
+
 #define CONFIG_SYS_PROMPT	"sun8i# "
 
 /*

Signature · 1 line

2.1.0

Ian Campbell

2014-12-22 13:13 UTC #5 lore raw

PATCH v2 3/4 sun8i: Add dram initialization support

Quoted 4 lines · Hans de Goede

Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0.
Signed-off-by Hans de Goede <[email protected]>

All my queries last time were on the defconfig, which is now split out,
so: Acked-by: Ian Campbell <[email protected]>

Hans de Goede

author

2014-12-20 11:29 UTC #6 lore raw

PATCH v2 4/4 sun8i: Ippo_q8h_v5_defconfig: Enable SPL support

In reply to Hans de Goede

Now that we've sun8i dram-init support we can enable the SPL for sun8i boards.

While at it also replace CONFIG_DEFAULT_DEVICE_TREE with CONFIG_FDTFILE, the former is for u-boot's own fdt usage, which we do not use (yet), the later specifies the fdt to pass to the kernel, which is the one we want.

Signed-off-by Hans de Goede <[email protected]>

---
 configs/Ippo_q8h_v5_defconfig | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

configs/Ippo_q8h_v5_defconfig +13 -5

index 50c2f93..b8d3afe 100644
@@ -1,8 +1,16 @@
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_ARM=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN8I=y
-CONFIG_TARGET_IPPO_Q8H_V5=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
+CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
 CONFIG_VIDEO=n
 CONFIG_USB_KEYBOARD=n
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN8I=y
++S:CONFIG_TARGET_IPPO_Q8H_V5=y
++S:CONFIG_DRAM_CLK=480
+# zq = 0xf777
++S:CONFIG_DRAM_ZQ=63351
+# Wifi power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
++S:CONFIG_AXP221_ALDO1_VOLT=3000

Signature · 1 line

2.1.0

Ian Campbell

2014-12-22 13:14 UTC #7 lore raw

PATCH v2 4/4 sun8i: Ippo_q8h_v5_defconfig: Enable SPL support

Quoted 7 lines · Hans de Goede

Now that we've sun8i dram-init support we can enable the SPL for sun8i boards.
While at it also replace CONFIG_DEFAULT_DEVICE_TREE with CONFIG_FDTFILE, the former is for u-boot's own fdt usage, which we do not use (yet), the later specifies the fdt to pass to the kernel, which is the one we want.
Signed-off-by Hans de Goede <[email protected]>

Acked-by Ian Campbell <[email protected]>

Chen-Yu Tsai

2014-12-22 09:35 UTC #8 lore raw

v2 cover sun8i: Remaining sun8i SPL support patches

In reply to Hans de Goede

Hi Hans,

Quoted 5 lines · Hans de Goede

Hi Ian, et al,
Here is a v2 of the A23 patches which did not pass review in v1 (so not a resend of the whole set).

I just built a new u-boot for my Q8H tablet this morning against

289dcd4 sunxi: video: Set input sync enable

and it works nicely. One thing that's not correct, but isn't an immediate issue is that PLL1 is different between sun6i and sun8i. See:

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/diff/drivers/clk/sunxi/clk-sunxi.c?id=515c1a4

This results in the CPU clock speed being only 504 MHz instead of the configured 1008 MHz full speed. As I said, it's not an immediate issue. In the future with cpufreq, it shouldn't matter either.

Also if you're building linux-next or v3.19-rc1 and using R_UART, be sure to use ttyS5 as the new console, due to the commit:

f77d55a3b56a serial: 8250_dw: get index of serial line from DT aliases

Cheers
ChenYu

Quoted 27 lines

Changes:
-"sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/"
-Not only change the prefix of the P2WI gpio mux defines from SUNXI to
SUN6I, but also the prefix of the SUN6I_P2WI_BASE address define
-"sunxi: Add support for the rsb (Reduced Serial Bus)"
-Drop sun6i / sun8i comments from SUN6I_P2WI_BASE / SUNXI_RSB_BASE defines,
use the prefix instead to make clear for which SoC family they are valid
-"sun8i: Add dram initialization support"
-white space fixes
-Add a comment that the ddr phy bits look a lot like the ddr phy found
in the TI Keystone2 and add a link to the TI Keystone2 documentation for future reference / cleanup work
-Split out the Ippo_q8h_v5_defconfig patches into their own patch
Regards,
Hans
p.s.
I also still need an ack for "sunxi: Fill memory before comparing it when doing dram init on sun6i", as you had some questions on that when reviewing v1 of the set.
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U-Boot at lists.denx.de
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Siarhei Siamashka

2014-12-22 14:39 UTC #9 lore raw

v2 cover sun8i: Remaining sun8i SPL support patches

Quoted 13 lines · On Mon, 22 Dec 2014 17:35:02 +0800 Chen-Yu Tsai <[email protected]> wrote:

Hi Hans,
Quoted 5 lines · Hans de Goede
Hi Ian, et al,
Here is a v2 of the A23 patches which did not pass review in v1 (so not a resend of the whole set).
I just built a new u-boot for my Q8H tablet this morning against
289dcd4 sunxi: video: Set input sync enable

Quoted 8 lines

and it works nicely. One thing that's not correct, but isn't an immediate issue is that PLL1 is different between sun6i and sun8i. See:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/diff/drivers/clk/sunxi/clk-sunxi.c?id=515c1a4
This results in the CPU clock speed being only 504 MHz instead of the configured 1008 MHz full speed. As I said, it's not an immediate issue. In the future with cpufreq, it shouldn't matter either.

Thanks, that's a good catch. Do you happen to know if PLL5 is the same or different between sun6i and sun8i?

The circumstances around the "sun6i: Add k and m parameters to clock_set_pll5()" patch seem to be a little bit fishy to me:

    http://lists.denx.de/pipermail/u-boot/2014-December/199279.html

Signature · 2 lines

Best regards,
Siarhei Siamashka