phy: fixes for 3.19 -rc cycle

Hi Greg,

Please find the pull request for 3.19 -rc cycle. This contains misc fixes in PHY drivers.

Let me know if I have to change something.

Thanks
Kishon

The following changes since commit aa39477b5692611b91ac9455ae588738852b3f60:

Merge tag 'dm-3.19-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm (2014-12-22 14:47:17 -0800)

are available in the git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git tags/for-3.19-rc

for you to fetch changes up to 0bc09f9cdc589e0b54724096138996a00b19babb:

phy: phy-ti-pipe3: fix inconsistent enumeration of PCIe gen2 cards (2014-12-23 15:44:32 +0530)

----------------------------------------------------------------
misc fixes in PHY drivers

----------------------------------------------------------------
Dan Carpenter (1):
phy: miphy28lp: unlock on error in miphy28lp_init()

Hans de Goede (1):
phy-sun4i-usb: Change disconnect threshold value for sun6i

Vignesh R (1):
phy: phy-ti-pipe3: fix inconsistent enumeration of PCIe gen2 cards

 drivers/phy/phy-miphy28lp.c          |    3 ++-
 drivers/phy/phy-omap-control.c       |    7 +++----
 drivers/phy/phy-sun4i-usb.c          |    3 ++-
 drivers/phy/phy-ti-pipe3.c           |   10 ++++++----
 include/linux/phy/omap_control_phy.h |    6 +++---
 5 files changed, 16 insertions(+), 13 deletions(-)

1.7.9.5

From: Dan Carpenter <[email protected]>

We need to unlock before returning the -EINVAL here.

---
 drivers/phy/phy-miphy28lp.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index e34da13..27fa62c 100644
@@ -1050,7 +1050,8 @@ static int miphy28lp_init(struct phy *phy)
 		ret = miphy28lp_init_usb3(miphy_phy);
 		break;
 	default:
-		return -EINVAL;
+		ret = -EINVAL;
+		break;
 	}
 
 	mutex_unlock(&miphy_dev->miphy_mutex);

1.7.9.5

From: Hans de Goede <[email protected]>

The allwinner SDK uses a value of 3 for the disconnect threshold setting on sun6i, do the same in the kernel.

In my previous experience with sun5i problems getting the threshold right is important to avoid usb2 devices being unplugged sometimes going unnoticed.

---
 drivers/phy/phy-sun4i-usb.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index fb02a67..a2b08f3c 100644
@@ -244,7 +244,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 	else
 		data->num_phys = 3;
 
-	if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
+	if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy") ||
+	    of_device_is_compatible(np, "allwinner,sun6i-a31-usb-phy"))
 		data->disc_thresh = 3;
 	else
 		data->disc_thresh = 2;

1.7.9.5

From: Vignesh R <[email protected]>

Prior to DRA74x silicon rev 1.1, pcie_pcs register bits 8-15 and bits 16-23 were used to configure RC delay count for phy1 and phy2 respectively. phyid was used as index to distinguish the phys and to configure the delay values appropriately.

As of DRA74x silicon rev 1.1, pcie_pcs register definition has changed. Bits 16-23 are used to configure delay values for *both* phy1 and phy2.

Hence phyid is no longer required.

So, drop id field from ti_pipe3 structure and its subsequent references for configuring pcie_pcs register.

Also, pcie_pcs register now needs to be configured with delay value of 0x96 at bit positions 16-23. See register description of CTRL_CORE_PCIE_PCS in ARM572x TRM, SPRUHZ6, October 2014, section 18.5.2.2, table 18-1804.

This is needed to ensure Gen2 cards are enumerated consistently.

DRA72x silicon behaves same way as DRA74x rev 1.1 as far as this functionality is considered.

Test results on DRA74x and DRA72x EVMs:

Before patch
------------
DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to silicon errata)
DRA74x ES 1.1: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect programming of register

DRA72x: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect programming of register

After patch
-----------
DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to silicon errata)
DRA74x ES 1.1: Gen1 cards work, Gen2 cards work consistently.

DRA72x: Gen1 and Gen2 cards enumerate consistently.

---
 drivers/phy/phy-omap-control.c       |    7 +++----
 drivers/phy/phy-ti-pipe3.c           |   10 ++++++----
 include/linux/phy/omap_control_phy.h |    6 +++---
 3 files changed, 12 insertions(+), 11 deletions(-)

index c96e818..efe724f 100644
@@ -29,10 +29,9 @@
 /**
  * omap_control_pcie_pcs - set the PCS delay count
  * @dev: the control module device
- * @id: index of the pcie PHY (should be 1 or 2)
  * @delay: 8 bit delay value
  */
-void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
+void omap_control_pcie_pcs(struct device *dev, u8 delay)
 {
 	u32 val;
 	struct omap_control_phy	*control_phy;

@@ -55,8 +54,8 @@ void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
 
 	val = readl(control_phy->pcie_pcs);
 	val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
-		(id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
-	val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
+		OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
+	val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
 	writel(val, control_phy->pcie_pcs);
 }
 EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);

index 1387b4d..465de2c 100644
@@ -82,7 +82,6 @@ struct ti_pipe3 {
 	struct clk		*refclk;
 	struct clk		*div_clk;
 	struct pipe3_dpll_map	*dpll_map;
-	u8			id;
 };
 
 static struct pipe3_dpll_map dpll_map_usb[] = {

@@ -217,8 +216,13 @@ static int ti_pipe3_init(struct phy *x)
 	u32 val;
 	int ret = 0;
 
+	/*
+	 * Set pcie_pcs register to 0x96 for proper functioning of phy
+	 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
+	 * 18-1804.
+	 */
 	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
-		omap_control_pcie_pcs(phy->control_dev, phy->id, 0xF1);
+		omap_control_pcie_pcs(phy->control_dev, 0x96);
 		return 0;
 	}
 

@@ -347,8 +351,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	}
 
 	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
-		if (of_property_read_u8(node, "id", &phy->id) < 0)
-			phy->id = 1;
 
 		clk = devm_clk_get(phy->dev, "dpll_ref");
 		if (IS_ERR(clk)) {

index e9e6cfb..eb7d4a1 100644
@@ -66,7 +66,7 @@ enum omap_control_usb_mode {
 #define	OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF	0x0
 
 #define	OMAP_CTRL_PCIE_PCS_MASK			0xff
-#define	OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT	0x8
+#define	OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT	16
 
 #define OMAP_CTRL_USB2_PHY_PD		BIT(28)
 

@@ -79,7 +79,7 @@ enum omap_control_usb_mode {
 void omap_control_phy_power(struct device *dev, int on);
 void omap_control_usb_set_mode(struct device *dev,
 			       enum omap_control_usb_mode mode);
-void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay);
+void omap_control_pcie_pcs(struct device *dev, u8 delay);
 #else
 
 static inline void omap_control_phy_power(struct device *dev, int on)

@@ -91,7 +91,7 @@ static inline void omap_control_usb_set_mode(struct device *dev,
 {
 }
 
-static inline void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
+static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
 {
 }
 #endif

1.7.9.5

Hi Greg,

Can you pick this series for this -rc cyle?

Thanks
Kishon

Now pulled and pushed out.

thanks,

greg k-h