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spi: designware_spi: Fix detecting FIFO depth

PATCH New Axel Lin 3 participants 3 messages Jan 6, 2015 SPI

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Axel Lin

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PATCH 1/1 spi: designware_spi: Fix detecting FIFO depth

Current code tries to find the highest valid fifo depth by checking the value it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary to test fifo == 257. In the case fifo is 257, it means the latest valid setting is fifo = 256. So after the for loop iteration, we should check fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.
This patch fixes above issues.

Signed-off-by Axel Lin <[email protected]>

---
The same fix is already applied to linux-spi tree:
http://git.kernel.org/cgit/linux/kernel/git/broonie/spi.git/commit/?h=for-linus&id=d297933cc7fcfbaaf2d37570baac73287bf0357d

This patch replaces my previous patch:
http://lists.denx.de/pipermail/u-boot/2014-December/199228.html

 drivers/spi/designware_spi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/spi/designware_spi.c +2 -2
index 98c9f03..0210667 100644
@@ -164,13 +164,13 @@ static void spi_hw_init(struct dw_spi_priv *priv)
 	if (!priv->fifo_len) {
 		u32 fifo;
 
-		for (fifo = 2; fifo <= 257; fifo++) {
+		for (fifo = 2; fifo <= 256; fifo++) {
 			dw_writew(priv, DW_SPI_TXFLTR, fifo);
 			if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
 				break;
 		}
 
-		priv->fifo_len = (fifo == 257) ? 0 : fifo;
+		priv->fifo_len = (fifo == 2) ? 0 : fifo - 1;
 		dw_writew(priv, DW_SPI_TXFLTR, 0);
 	}
 	debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
Signature · 1 line
1.9.1
#1 lore raw

PATCH 1/1 spi: designware_spi: Fix detecting FIFO depth

Quoted 11 lines · Axel Lin

Current code tries to find the highest valid fifo depth by checking the value it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary

    to test fifo == 257. In the case fifo is 257, it means the latest valid
    setting is fifo = 256. So after the for loop iteration, we should check
    fifo == 2 case instead of fifo == 257 if detecting the FIFO depth fails.

This patch fixes above issues.

Signed-off-by Axel Lin <[email protected]>
Acked-by Stefan Roese <[email protected]>

Thanks,
Stefan

#2 lore raw

PATCH 1/1 spi: designware_spi: Fix detecting FIFO depth

Quoted 18 lines · Stefan Roese
Quoted 17 lines · Axel Lin

Current code tries to find the highest valid fifo depth by checking the value
it wrote to DW_SPI_TXFLTR. There are a few problems in current code:
1) There is an off-by-one in dws->fifo_len setting because it assumes the latest
register write fails so the latest valid value should be fifo - 1.
2) We know the depth could be from 2 to 256 from HW spec, so it is not necessary

    to test fifo == 257. In the case fifo is 257, it means the latest
valid
    setting is fifo = 256. So after the for loop iteration, we should
check
    fifo == 2 case instead of fifo == 257 if detecting the FIFO depth

fails.
This patch fixes above issues.

Quoted 4 lines
Quoted 1 line
Signed-off-by Axel Lin <[email protected]>
Acked-by Stefan Roese <[email protected]>

Applied to u-boot-spi/master

thanks!

Signature · 1 line
Jagan.