Minimal FAPLL clock support for dm816x

Hi all,

Here's a minimal support for the FAPLL (Flying Adder PLL) on dm816x which is a omap variant.

Regards,

Tony

Tony Lindgren (2):
clk: ti: Add support for FAPLL on dm816x
clk: ti: Initialize clocks for dm816x

 .../devicetree/bindings/clock/ti/fapll.txt         |  33 ++
 drivers/clk/ti/Makefile                            |   1 +
 drivers/clk/ti/clk-3xxx.c                          |   8 +-
 drivers/clk/ti/clk-816x.c                          |  53 +++
 drivers/clk/ti/fapll.c                             | 410 +++++++++++++++++++++
 5 files changed, 498 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/fapll.txt
 create mode 100644 drivers/clk/ti/clk-816x.c
 create mode 100644 drivers/clk/ti/fapll.c

2.1.4

On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL) that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could potentially have the PLL code generic. To do that, we would have to consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers into bypass mode. As the bypass rate can also be generated by the PLL in regular mode, there's no way for the child synthesizers to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child syntheriser.

Note that the clocks are currently still missing the set_rate implementation so things are still running based on the bootloader values. That's OK for now as most of the outputs have dividers and those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks, so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

---
 .../devicetree/bindings/clock/ti/fapll.txt         |  33 ++
 drivers/clk/ti/Makefile                            |   1 +
 drivers/clk/ti/fapll.c                             | 410 +++++++++++++++++++++
 3 files changed, 444 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti/fapll.txt
 create mode 100644 drivers/clk/ti/fapll.c

new file mode 100644
index 0000000..c19b3f2
@@ -0,0 +1,33 @@
+Binding for Texas Instruments FAPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped FAPLL with usually two selectable input clocks
+(reference clock and bypass clock), and one or more child
+syntesizers.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,dm816-fapll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the FAPLL.
+
+Examples:
+	main_fapll: main_fapll {
+		#clock-cells = <1>;
+		compatible = "ti,dm816-fapll-clock";
+		reg = <0x400 0x40>;
+		clocks = <&sys_clkin_ck &sys_clkin_ck>;
+		clock-indices = <1>, <2>, <3>, <4>, <5>,
+				<6>, <7>;
+		clock-output-names = "main_pll_clk1",
+				     "main_pll_clk2",
+				     "main_pll_clk3",
+				     "main_pll_clk4",
+				     "main_pll_clk5",
+				     "main_pll_clk6",
+				     "main_pll_clk7";
+	};

index ed4d0aa..e55438c 100644
@@ -3,6 +3,7 @@ obj-y					+= clk.o autoidle.o clockdomain.o
 clk-common				= dpll.o composite.o divider.o gate.o \
 					  fixed-factor.o mux.o apll.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o
+obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= $(clk-common) interface.o clk-3xxx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o

2.1.4

The clocks on ti81xx are not compatible with omap3. On dm816x the clock source is a FAPLL (Flying Adder PLL), and on dm814x there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the FAPLL support. As we already have a dummy ti81xx_dt_clk_init() in place, let's use that for now to avoid adding a dependency to the omap patches.

Later on if somebody adds dm814x support we can split the ti81xx_dt_clk_init() clock init function as needed.

---
 drivers/clk/ti/Makefile   |  2 +-
 drivers/clk/ti/clk-3xxx.c |  8 +------
 drivers/clk/ti/clk-816x.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 8 deletions(-)
 create mode 100644 drivers/clk/ti/clk-816x.c

index e55438c..36acc7d 100644
@@ -3,7 +3,7 @@ obj-y					+= clk.o autoidle.o clockdomain.o
 clk-common				= dpll.o composite.o divider.o gate.o \
 					  fixed-factor.o mux.o apll.o
 obj-$(CONFIG_SOC_AM33XX)		+= $(clk-common) clk-33xx.o
-obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o
+obj-$(CONFIG_SOC_TI81XX)		+= $(clk-common) fapll.o clk-816x.o
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clk-common) interface.o clk-2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= $(clk-common) interface.o clk-3xxx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clk-common) clk-44xx.o

index 0d1750a..383a06e 100644
@@ -327,7 +327,6 @@ enum {
 	OMAP3_SOC_OMAP3430_ES1,
 	OMAP3_SOC_OMAP3430_ES2_PLUS,
 	OMAP3_SOC_OMAP3630,
-	OMAP3_SOC_TI81XX,
 };
 
 static int __init omap3xxx_dt_clk_init(int soc_type)

@@ -370,7 +369,7 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
 		(clk_get_rate(clk_get_sys(NULL, "core_ck")) / 1000000),
 		(clk_get_rate(clk_get_sys(NULL, "arm_fck")) / 1000000));
 
-	if (soc_type != OMAP3_SOC_TI81XX && soc_type != OMAP3_SOC_OMAP3430_ES1)
+	if (soc_type != OMAP3_SOC_OMAP3430_ES1)
 		omap3_clk_lock_dpll5();
 
 	return 0;

@@ -390,8 +389,3 @@ int __init am35xx_dt_clk_init(void)
 {
 	return omap3xxx_dt_clk_init(OMAP3_SOC_AM35XX);
 }
-
-int __init ti81xx_dt_clk_init(void)
-{
-	return omap3xxx_dt_clk_init(OMAP3_SOC_TI81XX);
-}

2.1.4

Quoting Tony Lindgren (2015-01-13 14:51:26)

Tony,

Patches look fine to me. I'll give it a few days for Paul or Tero to comment if they have any concerns.

Also, "flying adder pll" is a pretty badass pll name.

Regards,
Mike

Quoting Mike Turquette (2015-01-14 14:06:49)

Applied to clk-next.

Regards,
Mike