sunxi: display: Make lcd display clk phase configurable

PATCH New Hans de Goede 4 participants 9 messages Jan 13, 2015 – Jan 20, 2015

Subsystems (3)

Arm (32-bit) Framebuffer layer Arm/Allwinner sunXi SoC support

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Hans de Goede

author

2015-01-13 12:33 UTC #0 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup.

This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.

This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.

The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional.

Signed-off-by Hans de Goede <[email protected]>

---
 arch/arm/include/asm/arch-sunxi/display.h | 4 +---
 board/sunxi/Kconfig                       | 7 +++++++
 configs/Ippo_q8h_v1_2_defconfig           | 1 +
 configs/Ippo_q8h_v5_defconfig             | 1 +
 configs/MSI_Primo73_defconfig             | 1 +
 drivers/video/sunxi_display.c             | 7 +------
 6 files changed, 12 insertions(+), 9 deletions(-)

arch/arm/include/asm/arch-sunxi/display.h +1 -3

index 2ac8a87..ff92a10 100644
@@ -249,9 +249,7 @@ struct sunxi_tve_reg {
 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0	(0 << 28)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60	(1 << 28)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120	(2 << 28)
+#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
 #define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)

board/sunxi/Kconfig +7 -0

index 8d897c9..847a86f 100644
@@ -342,6 +342,13 @@ config VIDEO_LCD_MODE
 	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
 	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 
+config VIDEO_LCD_DCLK_PHASE
+	int "LCD panel display clock phase"
+	depends on VIDEO
+	default 1
+	---help---
+	Select LCD panel display clock phase shift, range 0-3.
+
 config VIDEO_LCD_POWER
 	string "LCD panel power enable pin"
 	depends on VIDEO

configs/Ippo_q8h_v1_2_defconfig +1 -0

index 3e6d3cc..192a461 100644
@@ -4,6 +4,7 @@ CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
 CONFIG_USB_MUSB_SUNXI=y
 CONFIG_USB0_VBUS_PIN="axp_drivebus"
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH7"
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"

configs/Ippo_q8h_v5_defconfig +1 -0

index b96985e..c894948 100644
@@ -4,6 +4,7 @@ CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
 CONFIG_USB_MUSB_SUNXI=y
 CONFIG_USB0_VBUS_PIN="axp_drivebus"
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH7"
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"

configs/MSI_Primo73_defconfig +1 -0

index ef1adc5..d731053 100644
@@ -2,6 +2,7 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
 CONFIG_FDTFILE="sun7i-a20-primo73.dtb"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH8"
 CONFIG_VIDEO_LCD_BL_EN="PH7"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"

drivers/video/sunxi_display.c +1 -6

index 8da45a5..46025ea 100644
@@ -592,12 +592,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
 		       &lcdc->tcon0_frm_ctrl);
 	}
 
-#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
-	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0;
-#endif
-#ifdef CONFIG_VIDEO_LCD_IF_LVDS
-	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60;
-#endif
+	val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
 	if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
 		val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 	if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))

Signature · 1 line

2.1.0

Ian Campbell

2015-01-17 23:05 UTC #1 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

Quoted 8 lines · Hans de Goede

While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.

Quoted 8 lines

This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional.
Signed-off-by Hans de Goede <[email protected]>

Could've sworn I replied to this one, but apparently not:

Acked-by Ian Campbell <[email protected]>

Simon Glass

2015-01-18 03:12 UTC #2 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

In reply to Hans de Goede

Hi Hans,

Quoted 16 lines · Hans de Goede

While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional.
Signed-off-by Hans de Goede <[email protected]>

Quoted 8 lines

---
 arch/arm/include/asm/arch-sunxi/display.h | 4 +---
 board/sunxi/Kconfig                       | 7 +++++++
 configs/Ippo_q8h_v1_2_defconfig           | 1 +
 configs/Ippo_q8h_v5_defconfig             | 1 +
 configs/MSI_Primo73_defconfig             | 1 +
 drivers/video/sunxi_display.c             | 7 +------
 6 files changed, 12 insertions(+), 9 deletions(-)

Are you planning to move this to device tree at some point?

Regards,
Simon

Hans de Goede

author

2015-01-19 19:06 UTC #3 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

Hi,

Quoted 28 lines · Simon Glass

Hi Hans,
Quoted 16 lines · Hans de Goede
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional.
Signed-off-by Hans de Goede <[email protected]>
Quoted 8 lines
---
  arch/arm/include/asm/arch-sunxi/display.h | 4 +---
  board/sunxi/Kconfig                       | 7 +++++++
  configs/Ippo_q8h_v1_2_defconfig           | 1 +
  configs/Ippo_q8h_v5_defconfig             | 1 +
  configs/MSI_Primo73_defconfig             | 1 +
  drivers/video/sunxi_display.c             | 7 +------
  6 files changed, 12 insertions(+), 9 deletions(-)

Quoted 1 line

Are you planning to move this to device tree at some point?

Yes, one of the free-electrons guys is working on a kms driver, once we've that and thus stable devicetree bindings for the display blocks I want to move all this over to devicetree.

Regards,

Hans

Simon Glass

2015-01-19 19:46 UTC #4 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

Hi Hans,

Quoted 40 lines · Hans de Goede

Hi,
Quoted 36 lines · Simon Glass
Hi Hans,
Quoted 30 lines · Hans de Goede
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by Hans de Goede <[email protected]>
---
  arch/arm/include/asm/arch-sunxi/display.h | 4 +---
  board/sunxi/Kconfig                       | 7 +++++++
  configs/Ippo_q8h_v1_2_defconfig           | 1 +
  configs/Ippo_q8h_v5_defconfig             | 1 +
  configs/MSI_Primo73_defconfig             | 1 +
  drivers/video/sunxi_display.c             | 7 +------
  6 files changed, 12 insertions(+), 9 deletions(-)

Quoted 8 lines

Quoted 1 line
Are you planning to move this to device tree at some point?
Yes, one of the free-electrons guys is working on a kms driver, once we've that
and thus stable devicetree bindings for the display blocks I want to move all
this over to devicetree.

OK thanks. More generally for sunxi I am wondering how common the board code can be. Already you have managed to support all sun7i boards in essentially a single config, for example. I wonder if we might support all sun7i boards with just different device trees? Not sure about other variants?

Regards,
Simon

Hans de Goede

author

2015-01-19 20:10 UTC #5 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

Hi,

Quoted 52 lines · Simon Glass

Hi Hans,
Quoted 40 lines · Hans de Goede
Hi,
Quoted 36 lines · Simon Glass
Hi Hans,
Quoted 30 lines · Hans de Goede
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by Hans de Goede <[email protected]>
---
   arch/arm/include/asm/arch-sunxi/display.h | 4 +---
   board/sunxi/Kconfig                       | 7 +++++++
   configs/Ippo_q8h_v1_2_defconfig           | 1 +
   configs/Ippo_q8h_v5_defconfig             | 1 +
   configs/MSI_Primo73_defconfig             | 1 +
   drivers/video/sunxi_display.c             | 7 +------
   6 files changed, 12 insertions(+), 9 deletions(-)
Quoted 8 lines
Quoted 1 line
Are you planning to move this to device tree at some point?
Yes, one of the free-electrons guys is working on a kms driver, once we've that
and thus stable devicetree bindings for the display blocks I want to move all
this over to devicetree.

Quoted 5 lines

OK thanks. More generally for sunxi I am wondering how common the board code can be. Already you have managed to support all sun7i boards in essentially a single config, for example. I wonder if we might support all sun7i boards with just different device trees? Not sure about other variants?

My long term vision is along the lines of having one u-boot binary each for sun4i, sun5i, sun6i, etc. and then be able to append a dtb to that u-boot binary, combine it with the right spl, and presto we've u-boot ready for the specific board as described by the dtb.

The tricky bit is making the spl board agnostic, as we only have 32k sram to work with, some of which is used by the BROM. We can overwrite it when booting from mmc, but not when FEL booting (sunxi BROM usb gadget mode boot), and we also need to put the initial stack there, so dtb parsing is sort of out of the question since the dtb itself would likely already be larger then the space we've. So the spl side will likely end up using some linker magic to put a struct with config parameters (like dram parameters) at a fixed offset and then use some utility to extract those from a dtb and patch them into the spl or some such.

Note this is where I would like to be, currently thinks like supporting newer sunxi SoCs has higher priority though, but if you want to help us getting there that would be great :)

Regards,

Hans

Simon Glass

2015-01-20 03:26 UTC #6 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

Hi Hans,

Quoted 74 lines · Hans de Goede

Hi,
Quoted 63 lines · Simon Glass
Hi Hans,
Quoted 51 lines · Hans de Goede
Hi,
Quoted 42 lines · Simon Glass
Hi Hans,
Quoted 26 lines · Hans de Goede
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that
we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.
This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.
Signed-off-by Hans de Goede <[email protected]>
Quoted 8 lines
---
   arch/arm/include/asm/arch-sunxi/display.h | 4 +---
   board/sunxi/Kconfig                       | 7 +++++++
   configs/Ippo_q8h_v1_2_defconfig           | 1 +
   configs/Ippo_q8h_v5_defconfig             | 1 +
   configs/MSI_Primo73_defconfig             | 1 +
   drivers/video/sunxi_display.c             | 7 +------
   6 files changed, 12 insertions(+), 9 deletions(-)
Quoted 1 line
Are you planning to move this to device tree at some point?
Quoted 6 lines
Yes, one of the free-electrons guys is working on a kms driver, once we've
that
and thus stable devicetree bindings for the display blocks I want to move all
this over to devicetree.
Quoted 5 lines
OK thanks. More generally for sunxi I am wondering how common the board code can be. Already you have managed to support all sun7i boards in essentially a single config, for example. I wonder if we might support all sun7i boards with just different device trees? Not sure about other variants?

Quoted 4 lines

My long term vision is along the lines of having one u-boot binary each for sun4i, sun5i, sun6i, etc. and then be able to append a dtb to that u-boot binary, combine it with the right spl, and presto we've u-boot ready for the specific board as described by the dtb.

Sounds good.

Quoted 11 lines

The tricky bit is making the spl board agnostic, as we only have 32k sram to work with, some of which is used by the BROM. We can overwrite it when booting from mmc, but not when FEL booting (sunxi BROM usb gadget mode boot), and we also need to put the initial stack there, so dtb parsing is sort of out of the question since the dtb itself would likely already be larger then the space we've. So the spl side will likely end up using some linker magic to put a struct with config parameters (like dram parameters) at a fixed offset and then use some utility to extract those from a dtb and patch them into the spl or some such.

I did write an fdtgrep tool to cut down a device tree to only selected nodes, etc. So it might be possible, and the simplest option. If you do the linker magic idea, we should try to unify it across all SoCs. Exynos already has a binary table - in Chrome OS we have a tool which converts the device tree to the binary table. It's best avoided though.

Quoted 4 lines

Note this is where I would like to be, currently thinks like supporting newer sunxi SoCs has higher priority though, but if you want to help us getting there that would be great :)

I think it would make sense to support newer devices with driver model and device tree, at least. I have already helped a little, I have my hands full for quite a while on various things at present.

Regards,
Simon

Siarhei Siamashka

2015-01-18 11:33 UTC #7 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

In reply to Hans de Goede

Quoted 7 lines · On Tue, 13 Jan 2015 13:33:32 +0100 Hans de Goede <[email protected]> wrote:

While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup.
This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.

What is the name of this option in fex files?

Quoted 6 lines

This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit.
The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional.

[...]

Signature · 2 lines

Best regards,
Siarhei Siamashka

Hans de Goede

author

2015-01-18 12:21 UTC #8 lore raw

PATCH 1/1 sunxi: display: Make lcd display clk phase configurable

Hi,

Quoted 7 lines · Siarhei Siamashka

Quoted 4 lines · On Tue, 13 Jan 2015 13:33:32 +0100 Hans de Goede <[email protected]> wrote:
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup.

Quoted 5 lines

Quoted 3 lines
This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value.
What is the name of this option in fex files?

Good question on sun4i / sun5i / sun7i it is stored in lcd_io_cfg0 but as a raw register value, rather then the clk phase value, so you need to shift right by 28 to get the actual value, e.g.:

lcd_io_cfg0 = 268435456

Means (0x10000000 >> 28) == 1

On sun6i / sun8i it is not clear, the allwinner kernel code uses lcd_hv_clk_phase which gets converted to an actual register value in a complicated method unfortunately, see the allwinner kernel sources.

Where as the fex files seem to use lcd_io_phase which is not used by the kernel AFAICT ...

Looking at the register values used under android it just seems to end up being 0 on sun6i / sun8i.

Regards,

Hans