Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas
PATCH v3 1/2 Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas
This patch adds basic constructs in the ARMv8 u-boot code to handle and apply Cortex-A57 specific erratas.
As and example, the framework showcases how erratas 833069, 826974 and 828024 can be handled and applied.
Later on this framework can be extended to include other erratas.
---
Changes from v2:
- Addressed comments regarding incorrect handling of bl and ret sequences.
- Reorganized the code to be more readable.
Changes from v1:
- Addressed Yorks' comments about x29 corruption.
arch/arm/cpu/armv8/start.S | 46 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/macro.h | 21 +++++++++++++++++++ 2 files changed, 67 insertions(+)
arch/arm/cpu/armv8/start.S +46 -0
@@ -67,6 +67,9 @@ reset: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: + /* Apply ARM core specific erratas */ + bl apply_core_errata + /* * Cache/BPB/TLB Invalidate * i-cache is invalidated before enabled in icache_enable()
@@ -97,6 +100,49 @@ master_cpu: /*-----------------------------------------------------------------------*/ +WEAK(apply_core_errata) + + mov x29, lr /* Save LR */ + /* For now, we support Cortex-A57 specific errata only */ + + /* Check if we are running on a Cortex-A57 core */ + branch_if_a57_core x0, apply_a57_core_errata + b 0f + +apply_a57_core_errata: + +#ifdef CONFIG_ARM_ERRATA_828024 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable non-allocate hint of w-b-n-a memory type */ + mov x0, #0x1 << 49 + /* Disable write streaming no L1-allocate threshold */ + mov x0, #0x3 << 25 + /* Disable write streaming no-allocate threshold */ + mov x0, #0x3 << 27 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_826974 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable speculative load execution ahead of a DMB */ + mov x0, #0x1 << 59 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_833069 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Enable Invalidates of BTB bit */ + and x0, x0, #0xE + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif +0: + mov lr, x29 /* Restore LR */ + + ret +ENDPROC(apply_core_errata) + +/*-----------------------------------------------------------------------*/ + WEAK(lowlevel_init) mov x29, lr /* Save LR */
arch/arm/include/asm/macro.h +21 -0
@@ -74,6 +74,27 @@ lr .req x30 .endm /* + * Branch if current processor is a Cortex-A57 core. + */ +.macro branch_if_a57_core, xreg, a57_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + and \xreg, \xreg, #0x00000FFF + cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */ + b.eq \a57_label +.endm + +/* +* Branch if current processor is a Cortex-A53 core. +*/ +.macro branch_if_a53_core, xreg, a53_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */ + b.eq \a53_label +.endm + +/* * Branch if current processor is a slave, * choose processor with all zero affinity value as the master. */
Signature · 1 line
1.7.9.5
PATCH v3 2/2 configs/ls2085a: Add support for Cortex-A57 erratas
This patch adds support for handling 828024 and 826974 erratas for Cortex-A57 cores present on LS2085A SoC.
--- include/configs/ls2085a_common.h | 4 ++++ 1 file changed, 4 insertions(+)
include/configs/ls2085a_common.h +4 -0
@@ -14,6 +14,10 @@#define CONFIG_LS2085A #define CONFIG_GICV3 +/* Errata fixes */ +#define CONFIG_ARM_ERRATA_828024 +#define CONFIG_ARM_ERRATA_826974 +/* Link Definitions */ #define CONFIG_SYS_TEXT_BASE 0x30001000
Signature · 1 line
1.7.9.5
PATCH v3 1/2 Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas
In reply to Bhupesh Sharmaarch/arm/cpu/armv8/start.S master_cpu: · line 110
Quoted 8 lines · Bhupesh Sharma
arch/arm/cpu/armv8/start.S +8
-0+WEAK(apply_core_errata) + + mov x29, lr /* Save LR */ + /* For now, we support Cortex-A57 specific errata only */ + + /* Check if we are running on a Cortex-A57 core */ + branch_if_a57_core x0, apply_a57_core_errata + b 0f
Instead of branching forward here, have the a57 code branch back at the end.
Quoted 10 lines
/*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macrobranch_if_a57_core, xreg,a57_labelarch/arm/include/asm/macro.h +6
-0+ mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + and \xreg, \xreg, #0x00000FFF + cmp \xreg, #0xD07 /* Cortex-A57 MPCore processor. */ + b.eq \a57_label +.endm
arch/arm/include/asm/macro.h lr .req x30 · line 95
Quoted 10 lines
arch/arm/include/asm/macro.h +10
-0+ +/* +* Branch if current processor is a Cortex-A53 core. +*/ +.macro branch_if_a53_core, xreg, a53_label + mrs \xreg, midr_el1 + lsr \xreg, \xreg, #4 + cmp \xreg, #0xD03 /* Cortex-A53 MPCore processor. */ + b.eq \a53_label +.endm
Why do you AND with 0xfff for a57 but not a53?
Where else do you expect to use these macros?
-Scott