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ARM: DRA7: hwmod_data: Fix hwmod data for pcie

PATCH New Kishon Vijay Abraham I 5 participants 16 messages Feb 20, 2015 – Mar 26, 2015

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Kishon Vijay Abraham I

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#0 lore raw

PATCH 1/2 ARM: DRA7: hwmod_data: Fix hwmod data for pcie

Fixed hwmod data for pcie by having the correct module mode offset. Previously this module mode offset was part of pcie PHY which was wrong. Now this module mode offset was moved to pcie hwmod and removed the hwmod data for pcie phy. While at that renamed pcie_hwmod to pciess_hwmod in order to match with the name given in TRM.

This helps to get rid of the following warning
"omap_hwmod: pcie1: _wait_target_disable failed"

[Grygorii.Strashko at linaro.org: Found the issue that actually caused
"omap_hwmod: pcie1: _wait_target_disable failed"]

Signed-off-by Grygorii Strashko <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c |  103 +++++++----------------------
 1 file changed, 24 insertions(+), 79 deletions(-)
arch/arm/mach-omap2/omap_hwmod_7xx_data.c +24 -79
index e8692e7..16fe7a1 100644
@@ -1466,55 +1466,18 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
  *
  */
 
-static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
 	.name	= "pcie",
 };
 
 /* pcie1 */
-static struct omap_hwmod dra7xx_pcie1_hwmod = {
+static struct omap_hwmod dra7xx_pciess1_hwmod = {
 	.name		= "pcie1",
-	.class		= &dra7xx_pcie_hwmod_class,
+	.class		= &dra7xx_pciess_hwmod_class,
 	.clkdm_name	= "pcie_clkdm",
 	.main_clk	= "l4_root_clk_div",
 	.prcm = {
 		.omap4 = {
-			.clkctrl_offs	= DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
-			.modulemode	= MODULEMODE_SWCTRL,
-		},
-	},
-};
-
-/* pcie2 */
-static struct omap_hwmod dra7xx_pcie2_hwmod = {
-	.name		= "pcie2",
-	.class		= &dra7xx_pcie_hwmod_class,
-	.clkdm_name	= "pcie_clkdm",
-	.main_clk	= "l4_root_clk_div",
-	.prcm = {
-		.omap4 = {
-			.clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
-			.modulemode   = MODULEMODE_SWCTRL,
-		},
-	},
-};
-
-/*
- * 'PCIE PHY' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
-	.name	= "pcie-phy",
-};
-
-/* pcie1 phy */
-static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
-	.name		= "pcie1-phy",
-	.class		= &dra7xx_pcie_phy_hwmod_class,
-	.clkdm_name	= "l3init_clkdm",
-	.main_clk	= "l4_root_clk_div",
-	.prcm = {
-		.omap4 = {
 			.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
 			.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
 			.modulemode   = MODULEMODE_SWCTRL,

@@ -1522,11 +1485,11 @@ static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
 	},
 };
 
-/* pcie2 phy */
-static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
-	.name		= "pcie2-phy",
-	.class		= &dra7xx_pcie_phy_hwmod_class,
-	.clkdm_name	= "l3init_clkdm",
+/* pcie2 */
+static struct omap_hwmod dra7xx_pciess2_hwmod = {
+	.name		= "pcie2",
+	.class		= &dra7xx_pciess_hwmod_class,
+	.clkdm_name	= "pcie_clkdm",
 	.main_clk	= "l4_root_clk_div",
 	.prcm = {
 		.omap4 = {

@@ -2877,50 +2840,34 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3_main_1 -> pcie1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+/* l3_main_1 -> pciess1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
 	.master		= &dra7xx_l3_main_1_hwmod,
-	.slave		= &dra7xx_pcie1_hwmod,
+	.slave		= &dra7xx_pciess1_hwmod,
 	.clk		= "l3_iclk_div",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_cfg -> pcie1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+/* l4_cfg -> pciess1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
 	.master		= &dra7xx_l4_cfg_hwmod,
-	.slave		= &dra7xx_pcie1_hwmod,
+	.slave		= &dra7xx_pciess1_hwmod,
 	.clk		= "l4_root_clk_div",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3_main_1 -> pcie2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+/* l3_main_1 -> pciess2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
 	.master		= &dra7xx_l3_main_1_hwmod,
-	.slave		= &dra7xx_pcie2_hwmod,
+	.slave		= &dra7xx_pciess2_hwmod,
 	.clk		= "l3_iclk_div",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_cfg -> pcie2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
-	.master		= &dra7xx_l4_cfg_hwmod,
-	.slave		= &dra7xx_pcie2_hwmod,
-	.clk		= "l4_root_clk_div",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> pcie1 phy */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
-	.master		= &dra7xx_l4_cfg_hwmod,
-	.slave		= &dra7xx_pcie1_phy_hwmod,
-	.clk		= "l4_root_clk_div",
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> pcie2 phy */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+/* l4_cfg -> pciess2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
 	.master		= &dra7xx_l4_cfg_hwmod,
-	.slave		= &dra7xx_pcie2_phy_hwmod,
+	.slave		= &dra7xx_pciess2_hwmod,
 	.clk		= "l4_root_clk_div",
 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 };

@@ -3327,12 +3274,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_cfg__mpu,
 	&dra7xx_l4_cfg__ocp2scp1,
 	&dra7xx_l4_cfg__ocp2scp3,
-	&dra7xx_l3_main_1__pcie1,
-	&dra7xx_l4_cfg__pcie1,
-	&dra7xx_l3_main_1__pcie2,
-	&dra7xx_l4_cfg__pcie2,
-	&dra7xx_l4_cfg__pcie1_phy,
-	&dra7xx_l4_cfg__pcie2_phy,
+	&dra7xx_l3_main_1__pciess1,
+	&dra7xx_l4_cfg__pciess1,
+	&dra7xx_l3_main_1__pciess2,
+	&dra7xx_l4_cfg__pciess2,
 	&dra7xx_l3_main_1__qspi,
 	&dra7xx_l4_per3__rtcss,
 	&dra7xx_l4_cfg__sata,
Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Now that we don't have hwmod entry for pcie PHY remove the ti,hwmod property from PCIE PHY's

Signed-off-by Kishon Vijay Abraham I <[email protected]>
---
 arch/arm/boot/dts/dra7.dtsi |    2 --
 1 file changed, 2 deletions(-)
arch/arm/boot/dts/dra7.dtsi +0 -2
index 5827fed..18a904d 100644
@@ -1111,7 +1111,6 @@
 					      "wkupclk", "refclk",
 					      "div-clk", "phy-div";
 				#phy-cells = <0>;
-				ti,hwmods = "pcie1-phy";
 			};
 
 			pcie2_phy: pciephy at 4a095000 {

@@ -1130,7 +1129,6 @@
 					      "wkupclk", "refclk",
 					      "div-clk", "phy-div";
 				#phy-cells = <0>;
-				ti,hwmods = "pcie2-phy";
 				status = "disabled";
 			};
 		};
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Hi Tony,

As I can see Patch 1 from this series was merged in 4.0-rc4,
but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
Quoted 29 lines · Kishon Vijay Abraham I

Now that we don't have hwmod entry for pcie PHY remove the ti,hwmod property from PCIE PHY's

Signed-off-by Kishon Vijay Abraham I <[email protected]>
---
  arch/arm/boot/dts/dra7.dtsi |    2 --
  1 file changed, 2 deletions(-)
arch/arm/boot/dts/dra7.dtsi +0 -2
index 5827fed..18a904d 100644
@@ -1111,7 +1111,6 @@
  					      "wkupclk", "refclk",
  					      "div-clk", "phy-div";
  				#phy-cells = <0>;
-				ti,hwmods = "pcie1-phy";
  			};
 
  			pcie2_phy: pciephy at 4a095000 {

@@ -1130,7 +1129,6 @@
  					      "wkupclk", "refclk",
  					      "div-clk", "phy-div";
  				#phy-cells = <0>;
-				ti,hwmods = "pcie2-phy";
  				status = "disabled";
  			};
  		};
maintainer
#3 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 6 lines · Grygorii Strashko

Hi Tony,

As I can see Patch 1 from this series was merged in 4.0-rc4,
but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

Regards,

Tony

Quoted 31 lines · Kishon Vijay Abraham I
Quoted 29 lines

Now that we don't have hwmod entry for pcie PHY remove the ti,hwmod property from PCIE PHY's

Signed-off-by Kishon Vijay Abraham I <[email protected]>
---
  arch/arm/boot/dts/dra7.dtsi |    2 --
  1 file changed, 2 deletions(-)
arch/arm/boot/dts/dra7.dtsi +0 -2
index 5827fed..18a904d 100644
@@ -1111,7 +1111,6 @@
  					      "wkupclk", "refclk",
  					      "div-clk", "phy-div";
  				#phy-cells = <0>;
-				ti,hwmods = "pcie1-phy";
  			};
 
  			pcie2_phy: pciephy at 4a095000 {

@@ -1130,7 +1129,6 @@
  					      "wkupclk", "refclk",
  					      "div-clk", "phy-div";
  				#phy-cells = <0>;
-				ti,hwmods = "pcie2-phy";
  				status = "disabled";
  			};
  		};
#4 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 8 lines · Tony Lindgren
Quoted 4 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4,
but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Quoted 31 lines
Quoted 31 lines · Kishon Vijay Abraham I
Quoted 29 lines

Now that we don't have hwmod entry for pcie PHY remove the ti,hwmod property from PCIE PHY's

Signed-off-by Kishon Vijay Abraham I <[email protected]>
---
   arch/arm/boot/dts/dra7.dtsi |    2 --
   1 file changed, 2 deletions(-)
arch/arm/boot/dts/dra7.dtsi +0 -2
index 5827fed..18a904d 100644
@@ -1111,7 +1111,6 @@
   					      "wkupclk", "refclk",
   					      "div-clk", "phy-div";
   				#phy-cells = <0>;
-				ti,hwmods = "pcie1-phy";
   			};
 
   			pcie2_phy: pciephy at 4a095000 {

@@ -1130,7 +1129,6 @@
   					      "wkupclk", "refclk",
   					      "div-clk", "phy-div";
   				#phy-cells = <0>;
-				ti,hwmods = "pcie2-phy";
   				status = "disabled";
   			};
   		};
Signature · 2 lines
regards,
-grygorii
maintainer
#5 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 5 lines · Grygorii.Strashko at linaro.org
Quoted 4 lines · Tony Lindgren
Quoted 3 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4,
but this patch wasn't. As result, I can see below warning all the time during boot now:

Quoted 7 lines
Quoted 4 lines
Quoted 1 line
[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

OK applying into omap-for-v4.0/fixes thanks.

Tony

Quoted 36 lines
Quoted 31 lines
Quoted 31 lines · Kishon Vijay Abraham I
Quoted 29 lines

Now that we don't have hwmod entry for pcie PHY remove the ti,hwmod property from PCIE PHY's

Signed-off-by Kishon Vijay Abraham I <[email protected]>
---
   arch/arm/boot/dts/dra7.dtsi |    2 --
   1 file changed, 2 deletions(-)
arch/arm/boot/dts/dra7.dtsi +0 -2
index 5827fed..18a904d 100644
@@ -1111,7 +1111,6 @@
   					      "wkupclk", "refclk",
   					      "div-clk", "phy-div";
   				#phy-cells = <0>;
-				ti,hwmods = "pcie1-phy";
   			};
 
   			pcie2_phy: pciephy at 4a095000 {

@@ -1130,7 +1129,6 @@
   					      "wkupclk", "refclk",
   					      "div-clk", "phy-div";
   				#phy-cells = <0>;
-				ti,hwmods = "pcie2-phy";
   				status = "disabled";
   			};
   		};
Signature · 2 lines
regards,
-grygorii
maintainer
#6 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

In reply to [email protected]
Quoted 5 lines · Grygorii.Strashko at linaro.org
Quoted 4 lines · Tony Lindgren
Quoted 3 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4,
but this patch wasn't. As result, I can see below warning all the time during boot now:

Quoted 7 lines
Quoted 4 lines
Quoted 1 line
[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Does the warning result in a functional problem, or is it just a warning?

- Paul

#7 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 9 lines · Paul Walmsley
Quoted 7 lines · Grygorii.Strashko at linaro.org
Quoted 6 lines · Tony Lindgren
Quoted 4 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4,
but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

Signature · 2 lines
regards,
-grygorii
maintainer
#8 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 15 lines · Grygorii.Strashko at linaro.org
Quoted 14 lines · Paul Walmsley
Quoted 12 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

Quoted 7 lines
Quoted 5 lines
Quoted 2 lines

I think, Yes. These two patches should go all together, because they are interrelated.

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

- Paul

maintainer
#9 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 20 lines · Paul Walmsley
Quoted 18 lines · Grygorii.Strashko at linaro.org
Quoted 17 lines · Paul Walmsley
Quoted 14 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

It seems it should be just a warning fix if the pciephy hwmod entries are now gone?

Anyways, I'm planning to send a pull request for omap-for-v4.0/fixes today. Please let me know ASAP if the $subject patch should be dropped, otherwise I'll send it as it fixes a boot time warning and is already applied.

Regards,

Tony

maintainer
#10 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 28 lines · Tony Lindgren
Quoted 20 lines · Paul Walmsley
Quoted 18 lines · Grygorii.Strashko at linaro.org
Quoted 17 lines · Paul Walmsley
Quoted 14 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

Quoted 7 lines

It seems it should be just a warning fix if the pciephy hwmod entries are now gone?

Anyways, I'm planning to send a pull request for omap-for-v4.0/fixes today. Please let me know ASAP if the $subject patch should be dropped, otherwise I'll send it as it fixes a boot time warning and is already applied.

If you want to send it up as a fix, that's fine with me. But I don't see how that second patch will cause any changes in device registration, as stated.

- Paul

#11 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

In reply to Paul Walmsley
Quoted 20 lines · Paul Walmsley
Quoted 18 lines · Grygorii.Strashko at linaro.org
Quoted 17 lines · Paul Walmsley
Quoted 14 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

I've re-checked it - sorry for disinfo.

PHY devices are created, but omap_device_fail_pm_domain is assigned to them. As result Runtime PM is not working any more.

[    0.592501] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
[    0.597510] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
[    0.602794] ti-pipe3 4a094000.pciephy: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info

When ti,hwmods is not present PCI PHY will be added as regular Platform device and Runtime PM will work again.

Signature · 2 lines
regards,
-grygorii
maintainer
#12 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 34 lines · Grygorii.Strashko at linaro.org
Quoted 20 lines · Paul Walmsley
Quoted 18 lines · Grygorii.Strashko at linaro.org
Quoted 17 lines · Paul Walmsley
Quoted 14 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

I've re-checked it - sorry for disinfo.

PHY devices are created, but omap_device_fail_pm_domain is assigned to them. As result Runtime PM is not working any more.

Quoted 6 lines
[    0.592501] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
[    0.597510] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
[    0.602794] ti-pipe3 4a094000.pciephy: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info

When ti,hwmods is not present PCI PHY will be added as regular Platform device and Runtime PM will work again.

OK then it should definitely go up as a fix.

Kishon, for future references, those two patches should have been combined into a single patch. As it stands now, if someone bisects down to that first patch, it sounds like PM will be at least partially broken. Too bad I don't have a DRA7xx board where things like this can be tested before being sent upstream.

- Paul

author
#13 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Hi,

Quoted 43 lines · Paul Walmsley
Quoted 34 lines · Grygorii.Strashko at linaro.org
Quoted 20 lines · Paul Walmsley
Quoted 18 lines · Grygorii.Strashko at linaro.org
Quoted 17 lines · Paul Walmsley
Quoted 14 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

I think, Yes. These two patches should go all together, because they are interrelated.

Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

I've re-checked it - sorry for disinfo.

PHY devices are created, but omap_device_fail_pm_domain is assigned to them. As result Runtime PM is not working any more.

Quoted 6 lines
[    0.592501] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
[    0.597510] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
[    0.602794] ti-pipe3 4a094000.pciephy: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info

When ti,hwmods is not present PCI PHY will be added as regular Platform device and Runtime PM will work again.

Quoted 7 lines

OK then it should definitely go up as a fix.

Kishon, for future references, those two patches should have been combined into a single patch. As it stands now, if someone bisects down to that first patch, it sounds like PM will be at least partially broken. Too bad I don't have a DRA7xx board where things like this can be tested before being sent upstream.

huh.. was under the assumption that patches for device tree and the kernel patches should be separate. And PCIE for DRA7xx was broken in mainline for quite sometime now because of reset framework support not added for DRA7xx.

Thanks
Kishon

maintainer
#14 lore raw

PATCH 2/2 ARM: dts: dra7: remove ti,hwmod property from pcie phy

Quoted 42 lines · Kishon Vijay Abraham I
Quoted 41 lines · Paul Walmsley
Quoted 31 lines · Grygorii.Strashko at linaro.org
Quoted 15 lines · Paul Walmsley
Quoted 14 lines · Grygorii.Strashko at linaro.org
Quoted 13 lines · Paul Walmsley
Quoted 12 lines · Grygorii.Strashko at linaro.org
Quoted 10 lines · Tony Lindgren
Quoted 6 lines · Grygorii Strashko

As I can see Patch 1 from this series was merged in 4.0-rc4, but this patch wasn't. As result, I can see below warning all the time during boot now:

[    0.594591] platform 4a094000.pciephy: Cannot lookup hwmod

'pcie1-phy'

OK. Is this needed as a fix for the v4.0-rc series, or can this wait for v4.1?

Quoted 8 lines
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines

I think, Yes. These two patches should go all together, because they are interrelated.

Does the warning result in a functional problem, or is it just a warning?

PCE1 PHY device is not registered any more.

How does the second patch fix that?

I've re-checked it - sorry for disinfo.

PHY devices are created, but omap_device_fail_pm_domain is assigned to them. As result Runtime PM is not working any more.

Quoted 6 lines
[    0.592501] platform 4a094000.pciephy: Cannot lookup hwmod 'pcie1-phy'
[    0.597510] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
[    0.602794] ti-pipe3 4a094000.pciephy: _od_fail_runtime_resume: FIXME: missing hwmod/omap_dev info

When ti,hwmods is not present PCI PHY will be added as regular Platform device and Runtime PM will work again.

OK then it should definitely go up as a fix.

Quoted 8 lines
Quoted 5 lines

Kishon, for future references, those two patches should have been combined into a single patch. As it stands now, if someone bisects down to that first patch, it sounds like PM will be at least partially broken. Too bad I don't have a DRA7xx board where things like this can be tested before being sent upstream.

huh.. was under the assumption that patches for device tree and the kernel patches should be separate.

Generally that's true, _unless_ separating them will break something between the two patches. That appears to be the case here. The important thing is to make sure every single commit builds and functions at least as well as the previous commit - i.e., there should be no regressions.

- Paul

maintainer
#15 lore raw

PATCH 1/2 ARM: DRA7: hwmod_data: Fix hwmod data for pcie

In reply to Kishon Vijay Abraham I
Quoted 6 lines · Kishon Vijay Abraham I

Fixed hwmod data for pcie by having the correct module mode offset. Previously this module mode offset was part of pcie PHY which was wrong. Now this module mode offset was moved to pcie hwmod and removed the hwmod data for pcie phy. While at that renamed pcie_hwmod to pciess_hwmod in order to match with the name given in TRM.

Quoted 7 lines

This helps to get rid of the following warning
"omap_hwmod: pcie1: _wait_target_disable failed"

[Grygorii.Strashko at linaro.org: Found the issue that actually caused
"omap_hwmod: pcie1: _wait_target_disable failed"]

Signed-off-by Grygorii Strashko <[email protected]>
Signed-off-by Kishon Vijay Abraham I <[email protected]>

Thanks sent this for v4.0-rc fixes. Unfortunately I don't have a DRA7xx board so can't test.

- Paul