Skip to contentSkip to conversation

ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

PATCH Superseded Nishanth Menon 1 participant 7 messages Feb 24, 2015

Subsystems (2)
Arm (32-bit) Arm/actions semi architecture

v2 of 6 Superseded Latest is v6 →

lore
Share & tools
lore

Nishanth Menon

author
#0 lore raw

v2 cover ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements

Hi,

V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174

V2 of this series is a culmination of
a) bunch of refactoring to ensure common code in generic logic - cpuid mostly
b) split the arm generic patch (patch #4 out.. to allow independent review)
c) Saw a chance to incorporate OMAP3 into the same framework, and in fact can exactly allow exynos also do the job: https://patchwork.ozlabs.org/patch/440852/A
https://patchwork.ozlabs.org/patch/442646/
https://patchwork.ozlabs.org/patch/442297/
(obviously the code has changed since the original omap3 implementation)

Carrying on the blurb as posted previously :)

Triggered by a user report, it was seen that recommended errata workaround and performance trade-offs as recommended by TI architects for ARM configuration was not being followed in OMAP5+ ARM A15 platforms in u-boot configuration. Note OMAP5, DRA7 all share the same cortex A15 revision (ID=0x412fc0f2) and the workarounds and improvement configurations apply equally.

Certain errata workaround done in this series obviously have the controversy potential considering that each of the SoCs implement workaround based on secure monitor calls, but both the service requested and the parameters of secure monitor calls can be widely variant. Examples:
OMAP family of processors have quite the family of SMC calls:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-omap2/omap-smc.S
meanwhile Exynos has a much simpler invocation:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/mach-exynos/exynos-smc.S

To maintain some resemblance of symmetry the following series introduces a arch/machine dependent errata macro which must be enabled prior to any of such workarounds can be implemented.

I am open to better ways of doing this which might benefit others in ARM community with similar needs. Lets discuss.

These patches are based on: v2015.04-rc1 but also apply on latest master.

Note:(OMAP3 is just build tested.. as I stated previously)
./MAKEALL -s omap3
v2015.04-rc1: http://pastebin.ubuntu.com/10397352/
v2015.04-rc1+ this series: http://pastebin.ubuntu.com/10397267/
(same sets of failures of build - no regressions introduced that I could see).

Angela Stegmaier (1):
configs: ti_omap5_common: Enable workaround for ARM errata 798870

Nishanth Menon (7):
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs
ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with
omap_smc1
ARM: Provide a mechanism to invoke SoC specific errata WA for CP15
ARM: OMAP3: Introduce OMAP3 Cortex-A8 revision specific errata
configs: ti_omap3_common: Enable workaround for ARM errata 454179,

    430973, 621766

ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended
configuration

Praveen Rao (1):
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

 README                                             |    9 ++++
 arch/arm/cpu/armv7/omap-common/Makefile            |    2 +-
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S     |   15 ++++--
 arch/arm/cpu/armv7/omap3/board.c                   |   24 ++--------
 arch/arm/cpu/armv7/omap3/lowlevel_init.S           |   48 +++++++++++++++-----
 arch/arm/cpu/armv7/omap4/hwinit.c                  |    4 +-
 arch/arm/cpu/armv7/omap5/Makefile                  |    1 +
 arch/arm/cpu/armv7/omap5/hwinit.c                  |   16 +++++++
 arch/arm/cpu/armv7/omap5/lowlevel_init.S           |   46 +++++++++++++++++++
 arch/arm/cpu/armv7/start.S                         |   14 ++++++
 .../arm/include/asm/arch-omap3/{omap3.h => omap.h} |    0
 arch/arm/include/asm/arch-omap3/sys_proto.h        |    3 +-
 arch/arm/include/asm/arch-omap4/sys_proto.h        |    5 +-
 arch/arm/include/asm/arch-omap5/sys_proto.h        |    4 ++
 include/configs/am3517_crane.h                     |    2 +-
 include/configs/am3517_evm.h                       |    2 +-
 include/configs/cm_t35.h                           |    2 +-
 include/configs/cm_t3517.h                         |    2 +-
 include/configs/dig297.h                           |    2 +-
 include/configs/mcx.h                              |    2 +-
 include/configs/nokia_rx51.h                       |    2 +-
 include/configs/omap3_evm.h                        |    2 +-
 include/configs/omap3_evm_quick_mmc.h              |    2 +-
 include/configs/omap3_evm_quick_nand.h             |    2 +-
 include/configs/omap3_logic.h                      |    2 +-
 include/configs/omap3_mvblx.h                      |    2 +-
 include/configs/omap3_pandora.h                    |    2 +-
 include/configs/omap3_sdp3430.h                    |    2 +-
 include/configs/omap3_zoom1.h                      |    2 +-
 include/configs/tam3517-common.h                   |    2 +-
 include/configs/tao3530.h                          |    2 +-
 include/configs/ti_omap3_common.h                  |    8 +++-
 include/configs/ti_omap5_common.h                  |    4 ++
 include/configs/tricorder.h                        |    2 +-
 34 files changed, 178 insertions(+), 61 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S
 rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)

Regards,
Nishanth Menon

Signature · 1 line
1.7.9.5
author
#1 lore raw

PATCH v2 1/9 ARM: OMAP: Change set_pl310_ctrl_reg to be generic

set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.

So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.

Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   13 ++++++++-----
 arch/arm/cpu/armv7/omap4/hwinit.c              |    4 ++--
 arch/arm/include/asm/arch-omap4/sys_proto.h    |    5 ++++-
 3 files changed, 14 insertions(+), 8 deletions(-)
arch/arm/cpu/armv7/omap-common/lowlevel_init.S +8 -5
index 86c0e4217478..9b24369e4dc1 100644
@@ -22,11 +22,14 @@ ENTRY(save_boot_params)
 	bx	lr
 ENDPROC(save_boot_params)
 
-ENTRY(set_pl310_ctrl_reg)
-	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
+ENTRY(omap_smc1)
+	PUSH	{r4-r12, lr}	@ save registers - ROM code may pollute
 				@ our registers
-	LDR	r12, =0x102	@ Set PL310 control register - value in R0
+	MOV	r12, r0		@ Service
+	MOV	r0, r1		@ Argument
+	DSB
+	DMB
 	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
 				@ call ROM Code API to set control register
-	POP	{r4-r11, pc}
-ENDPROC(set_pl310_ctrl_reg)
+	POP	{r4-r12, pc}
+ENDPROC(omap_smc1)
arch/arm/cpu/armv7/omap4/hwinit.c +2 -2
index db16548fac49..9792761d40a0 100644
@@ -159,11 +159,11 @@ void init_omap_revision(void)
 #ifndef CONFIG_SYS_L2CACHE_OFF
 void v7_outer_cache_enable(void)
 {
-	set_pl310_ctrl_reg(1);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 }
 
 void v7_outer_cache_disable(void)
 {
-	set_pl310_ctrl_reg(0);
+	omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 }
 #endif /* !CONFIG_SYS_L2CACHE_OFF */
arch/arm/include/asm/arch-omap4/sys_proto.h +4 -1
index e19975efaf50..f425e3af54f5 100644
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void set_pl310_ctrl_reg(u32 val);
+void omap_smc1(u32 service, u32 val);
 void setup_clocks_for_console(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);

@@ -57,4 +57,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET	0x102
+
 #endif
Signature · 1 line
1.7.9.5
author
#2 lore raw

PATCH v2 2/9 ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs

In reply to Nishanth Menon

This is in preperation of using generic cross OMAP code.

Signed-off-by Nishanth Menon <[email protected]>
---
 .../arm/include/asm/arch-omap3/{omap3.h => omap.h} |    0
 include/configs/am3517_crane.h                     |    2 +-
 include/configs/am3517_evm.h                       |    2 +-
 include/configs/cm_t35.h                           |    2 +-
 include/configs/cm_t3517.h                         |    2 +-
 include/configs/dig297.h                           |    2 +-
 include/configs/mcx.h                              |    2 +-
 include/configs/nokia_rx51.h                       |    2 +-
 include/configs/omap3_evm.h                        |    2 +-
 include/configs/omap3_evm_quick_mmc.h              |    2 +-
 include/configs/omap3_evm_quick_nand.h             |    2 +-
 include/configs/omap3_logic.h                      |    2 +-
 include/configs/omap3_mvblx.h                      |    2 +-
 include/configs/omap3_pandora.h                    |    2 +-
 include/configs/omap3_sdp3430.h                    |    2 +-
 include/configs/omap3_zoom1.h                      |    2 +-
 include/configs/tam3517-common.h                   |    2 +-
 include/configs/tao3530.h                          |    2 +-
 include/configs/ti_omap3_common.h                  |    2 +-
 include/configs/tricorder.h                        |    2 +-
 20 files changed, 19 insertions(+), 19 deletions(-)
 rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
arch/arm/include/asm/arch-omap3/omap.h renamed from arch/arm/include/asm/arch-omap3/omap3.h +0 -0
similarity index 100%
rename from arch/arm/include/asm/arch-omap3/omap3.h
rename to arch/arm/include/asm/arch-omap3/omap.h
include/configs/am3517_crane.h +1 -1
index 09ee10c0590b..a4128773ddb2 100644
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/am3517_evm.h +1 -1
index 190ef0e71bfb..94398c625eb0 100644
@@ -23,7 +23,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/cm_t35.h +1 -1
index 9767512a5cf0..56a5506f5c78 100644
@@ -30,7 +30,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/cm_t3517.h +1 -1
index 918032bd753a..ee1b7a0cb5a7 100644
@@ -30,7 +30,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/dig297.h +1 -1
index c8739ed29490..8791199fc61d 100644
@@ -36,7 +36,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/mcx.h +1 -1
index 26eb2203540f..2cf66c40d6fe 100644
@@ -26,7 +26,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_FIT
include/configs/nokia_rx51.h +1 -1
index 46fc91e5e197..442e16ae686b 100644
@@ -42,7 +42,7 @@
 #define CONFIG_SDRC			/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 #include <asm/arch/mem.h>
 #include <linux/stringify.h>
include/configs/omap3_evm.h +1 -1
index 8bdc08f5864c..4e587e10ffd3 100644
@@ -18,7 +18,7 @@
 #define __OMAP3EVM_CONFIG_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands
include/configs/omap3_evm_quick_mmc.h +1 -1
index 1185f425501f..a7acc1becbeb 100644
@@ -13,7 +13,7 @@
 #define __OMAP3_EVM_QUICK_MMC_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands
include/configs/omap3_evm_quick_nand.h +1 -1
index 4427e88b7e4b..c6cad9388961 100644
@@ -13,7 +13,7 @@
 #define __OMAP3_EVM_QUICK_NAND_H
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /* ----------------------------------------------------------------------------
  * Supported U-boot commands
include/configs/omap3_logic.h +1 -1
index aeb385f5ff6b..fcef46735835 100644
@@ -24,7 +24,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/omap3_mvblx.h +1 -1
index bf1d34dedb4d..20ec3ad15439 100644
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/omap3_pandora.h +1 -1
index 45feeb577320..b92d67abccf9 100644
@@ -21,7 +21,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/omap3_sdp3430.h +1 -1
index ac307eb45629..bf5c7a8faf77 100644
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * NOTE:  these #defines presume standard SDP jumper settings.
include/configs/omap3_zoom1.h +1 -1
index c5d742c2bd80..611cd5e1a350 100644
@@ -22,7 +22,7 @@
 #define CONFIG_NAND
 #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 #include <configs/ti_omap3_common.h>
 
 /* Remove SPL boot option - we do not support that on LDP yet */
include/configs/tam3517-common.h +1 -1
index 9fbe68a8a2f2..bff9687b3c9c 100644
@@ -25,7 +25,7 @@
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/tao3530.h +1 -1
index 7d2c0d2fa75c..4dfd5cb9fbb7 100644
@@ -27,7 +27,7 @@
 #define CONFIG_SDRC			/* Has an SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 /*
  * Display CPU and Board information
include/configs/ti_omap3_common.h +1 -1
index 3c634ee680d0..f909f6b94a18 100644
@@ -16,7 +16,7 @@
 
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_DM
include/configs/tricorder.h +1 -1
index 36621a553cdf..f27cd1b9b061 100644
@@ -32,7 +32,7 @@
 #define CONFIG_SDRC			/* The chip has SDRC controller */
 
 #include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
 
 #define CONFIG_SYS_GENERIC_BOARD
Signature · 1 line
1.7.9.5
author
#3 lore raw

PATCH v2 4/9 ARM: Provide a mechanism to invoke SoC specific errata WA for CP15

In reply to Nishanth Menon

Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an ARCH specific macro is introduced to implement SoC specific errata workaround implementations.

Signed-off-by Nishanth Menon <[email protected]>
---
 README                     |    5 +++++
 arch/arm/cpu/armv7/start.S |   14 ++++++++++++++
 2 files changed, 19 insertions(+)
README +5 -0
index a28ff133ee05..2e53e0c5757d 100644
@@ -621,6 +621,11 @@ The following options need to be configured:
 		exists, unlike the similar options in the Linux kernel. Do not
 		set these options unless they apply!
 
+		NOTE: The following are machine specific errata that are enabled
+		with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an
+		SoC specific implementation of the erratum workaround to
+		function.
+
 - Driver Model
 		Driver model is a new framework for devices in U-Boot
 		introduced in early 2014. U-Boot is being progressively
arch/arm/cpu/armv7/start.S +14 -0
index 70048c10aee6..3b814d8f42d3 100644
@@ -163,6 +163,20 @@ ENTRY(cpu_init_cp15)
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
 
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
+	mrc p15, 0, r0, c0, c0, 0	@ r0 has Read Main ID Register (MIDR)
+	mov r1, r0, lsr #20		@ get variant field
+	and r1, r1, #0xf		@ r1 has CPU variant
+	and r2, r0, #0xf                @ r2 has CPU revision
+	mov r3, r1, lsl #4		@ shift variant field for combined value
+	orr r3, r2, r3                  @ r3 has combined CPU variant + revision
+	/* C Prototype:
+	 * void arch_cp15_errata_workaround(u32 midr, u32 variant,
+	 *				    u32 rev, u32 comb);
+	 */
+	b arch_cp15_errata_workaround @ Do Machine specific errata WAs
+#endif
+
 	mov	pc, lr			@ back to my caller
 ENDPROC(cpu_init_cp15)
Signature · 1 line
1.7.9.5
author
#4 lore raw

PATCH v2 5/9 ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870

In reply to Nishanth Menon

From: Praveen Rao <[email protected]>

This patch adds workaround for ARM errata 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."

An implementation for OMAP5 and DRA7 is introduced here as well. Obviously, implementations for other SoC families such as Exynos etc will be widely different.

Signed-off-by Praveen Rao <[email protected]>
Signed-off-by Angela Stegmaier <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 README                                      |    1 +
 arch/arm/cpu/armv7/omap5/Makefile           |    1 +
 arch/arm/cpu/armv7/omap5/lowlevel_init.S    |   46 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h |    1 +
 4 files changed, 49 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/omap5/lowlevel_init.S
README +1 -0
index 2e53e0c5757d..d76cdc68d406 100644
@@ -625,6 +625,7 @@ The following options need to be configured:
 		with CONFIG_ARM_ARCH_CP15_ERRATA define. These need to have an
 		SoC specific implementation of the erratum workaround to
 		function.
+		CONFIG_ARM_ERRATA_798870
 
 - Driver Model
 		Driver model is a new framework for devices in U-Boot
arch/arm/cpu/armv7/omap5/Makefile +1 -0
index 64c68791f18e..b645dd4f58b7 100644
@@ -11,3 +11,4 @@ obj-y	+= sdram.o
 obj-y	+= prcm-regs.o
 obj-y	+= hw_data.o
 obj-y	+= abb.o
+obj-y	+= lowlevel_init.o
arch/arm/cpu/armv7/omap5/lowlevel_init.S new file +46 -0

46 lines not on this page · raw message

arch/arm/include/asm/arch-omap5/sys_proto.h +1 -0
index 103830319a41..0a7a52d138df 100644
@@ -56,6 +56,7 @@ void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
 void setup_warmreset_time(void);
+void omap_smc1(u32 service, u32 val);
 
 static inline u32 div_round_up(u32 num, u32 den)
 {
Signature · 1 line
1.7.9.5
author
#5 lore raw

PATCH v2 6/9 configs: ti_omap5_common: Enable workaround for ARM errata 798870

In reply to Nishanth Menon

From: Angela Stegmaier <[email protected]>

Enable the workaround for ARM errata 798870 for OMAP5 and DRA7xx since they are Coretx-A15 r2.

Signed-off-by Angela Stegmaier <[email protected]>
Signed-off-by Nishanth Menon <[email protected]>
---
 include/configs/ti_omap5_common.h |    4 ++++
 1 file changed, 4 insertions(+)
include/configs/ti_omap5_common.h +4 -0
index 925cb42dd38d..bce9a505cbb3 100644
@@ -21,6 +21,10 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_ARCH_CPU_INIT
 
+/* Common ARM Erratas */
+#define CONFIG_ARM_ARCH_CP15_ERRATA
+#define CONFIG_ARM_ERRATA_798870
+
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 /* Use General purpose timer 1 */
Signature · 1 line
1.7.9.5
author
#6 lore raw

PATCH v2 8/9 configs: ti_omap3_common: Enable workaround for ARM errata 454179, 430973, 621766

In reply to Nishanth Menon

Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.

Signed-off-by Nishanth Menon <[email protected]>
---
 arch/arm/cpu/armv7/omap3/board.c  |   16 ----------------
 include/configs/ti_omap3_common.h |    6 ++++++
 2 files changed, 6 insertions(+), 16 deletions(-)
arch/arm/cpu/armv7/omap3/board.c +0 -16
index 7ce30949a6c6..cc3a43341335 100644
@@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
-static void omap3_setup_aux_cr(void);
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
 #endif

@@ -246,9 +245,6 @@ void s_init(void)
 
 	try_unlock_memory();
 
-	/* Errata workarounds */
-	omap3_setup_aux_cr();
-
 #ifndef CONFIG_SYS_L2CACHE_OFF
 	/* Invalidate L2-cache from secure mode */
 	omap3_invalidate_l2_cache_secure();

@@ -428,18 +424,6 @@ void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 	}
 }
 
-static void omap3_setup_aux_cr(void)
-{
-	/* Workaround for Cortex-A8 errata: #454179 #430973
-	 *	Set "IBE" bit
-	 *	Set "Disable Branch Size Mispredicts" bit
-	 * Workaround for erratum #621766
-	 *	Enable L1NEON bit
-	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
-	 */
-	omap3_update_aux_cr_secure(0xE0, 0);
-}
-
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 {
include/configs/ti_omap3_common.h +6 -0
index f909f6b94a18..db15c12ddf53 100644
@@ -27,6 +27,12 @@
 # define CONFIG_SYS_MALLOC_F_LEN	(1 << 10)
 #endif
 
+/* Common ARM Erratas */
+#define CONFIG_ARM_ARCH_CP15_ERRATA
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
+
 /* The chip has SDRC controller */
 #define CONFIG_SDRC
Signature · 1 line
1.7.9.5