drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz
Subsystems (3)
PATCH 1/1 drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz
From: Ville Syrjälä <[email protected]>
The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work.
4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays.
--- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_display.c +1 -1
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {* them would make no difference. */ .dot = { .min = 25000 * 5, .max = 540000 * 5}, - .vco = { .min = 4860000, .max = 6700000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, .m2 = { .min = 24 << 22, .max = 175 << 22 },
Signature · 6 lines
2.0.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Task id: 5845 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 282/282 282/282
ILK -1 308/308 307/308
SNB 326/326 326/326 IVB 379/379 379/379 BYT 294/294 294/294 HSW -1 387/387 386/387 BDW -1 316/316 315/316 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible PASS(4) DMESG_WARN(1)PASS(1) *HSW igt_gem_storedw_batches_loop_normal PASS(4) DMESG_WARN(1)PASS(1) *BDW igt_gem_gtt_hog PASS(15) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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Quoted 23 lines · On 2/27/2015 12:31 AM, [email protected] wrote:
From: Ville Syrjälä <[email protected]>
The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work.
4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays.
Signed-off-by Ville Syrjälä <[email protected]>--- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/gpu/drm/i915/intel_display.c +0
-0
drivers/gpu/drm/i915/intel_display.c static const intel_limit_t intel_limits_chv = { · line 396
Quoted 8 lines
drivers/gpu/drm/i915/intel_display.c +1
-1@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {* them would make no difference. */ .dot = { .min = 25000 * 5, .max = 540000 * 5}, - .vco = { .min = 4860000, .max = 6700000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, .m2 = { .min = 24 << 22, .max = 175 << 22 },
Minor nitpick: typo in patch title
Thanks,
Vijay
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Quoted 19 lines · Vijay A
Quoted 18 lines · On 2/27/2015 12:31 AM, [email protected] wrote:
From: Ville Syrjälä <[email protected]>
The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work.
4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays.
Signed-off-by Ville Syrjälä <[email protected]>--- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Quoted 15 lines
drivers/gpu/drm/i915/intel_display.c static const intel_limit_t intel_limits_chv = { · line 396
Quoted 13 lines
drivers/gpu/drm/i915/intel_display.c +1
-1@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {* them would make no difference. */ .dot = { .min = 25000 * 5, .max = 540000 * 5}, - .vco = { .min = 4860000, .max = 6700000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, .m2 = { .min = 24 << 22, .max = 175 << 22 },Minor nitpick: typo in patch title
Dang. I already fixed a typo there before sending this out, but turns out I only managed to cchange it into a different typo :( Maybe I need to invest in a spell checker...
Quoted 9 lines
Reviewed-by Vijay Purushothaman <[email protected]>Thanks,
Vijay
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Signature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoted 36 lines · Ville Syrjälä
Quoted 19 lines · Vijay A
Quoted 18 lines · On 2/27/2015 12:31 AM, [email protected] wrote:
From: Ville Syrjälä <[email protected]>
The current minimum vco frequency leaves us with a gap in our supported frequencies at 233-243 MHz. Your typical 2560x1440@60 display wants a pixel clock of 241.5 MHz, which is just withing that gap. Reduce the allowed vco min frequency to 4.8GHz to reduce the gap to 233-240 MHz, and thus allow such displays to work.
4.8 GHz is actually the documented (at least in some docs) limit of the PLL, and we just picked 4.86 GHz originally because that was the lowest value produced by the PLL spreadsheet, which obviously didn't consider 2560x1440 displays.
Signed-off-by Ville Syrjälä <[email protected]>--- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)Quoted 15 lines
drivers/gpu/drm/i915/intel_display.c static const intel_limit_t intel_limits_chv = { · line 396
Quoted 13 lines
drivers/gpu/drm/i915/intel_display.c +1
-1@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {* them would make no difference. */ .dot = { .min = 25000 * 5, .max = 540000 * 5}, - .vco = { .min = 4860000, .max = 6700000 }, + .vco = { .min = 4800000, .max = 6700000 }, .n = { .min = 1, .max = 1 }, .m1 = { .min = 2, .max = 2 }, .m2 = { .min = 24 << 22, .max = 175 << 22 },Minor nitpick: typo in patch title
Quoted 3 lines
Dang. I already fixed a typo there before sending this out, but turns out I only managed to cchange it into a different typo :( Maybe I need to invest in a spell checker...
Fixed and applied, thanks.
-Daniel
Quoted 18 lines
Quoted 10 lines
Reviewed-by Vijay Purushothaman <[email protected]>Thanks,
Vijay
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http://lists.freedesktop.org/mailman/listinfo/intel-gfxSignature · 6 lines
Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Signature · 7 lines
Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Jani Nikula
maintainercheckpatch spell checking (was: Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz)
In reply to Ville SyrjäläQuoted 6 lines · Ville Syrjälä
Quoted 1 line · Vijay A
Minor nitpick: typo in patch title
Dang. I already fixed a typo there before sending this out, but turns out I only managed to cchange it into a different typo :( Maybe I need to invest in a spell checker...
These days checkpatch.pl does some of this for you (see scripts/spelling.txt). However your "reudce" isn't there, and, more importantly, AFAICT checkpatch.pl does not look at the patch subject anyway.
Joe, Andy, hint, hint. ;)
BR,
Jani.
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Joe Perches
maintainerRe: checkpatch spell checking (was: Re: [Intel-gfx] [PATCH] drm/i915: Reudce CHV DPLL min vco frequency to 4.8 GHz)
Quoted 8 lines · Jani Nikula
Quoted 6 lines · Ville Syrjälä
Quoted 1 line · Vijay A
Minor nitpick: typo in patch title
Dang. I already fixed a typo there before sending this out, but turns out I only managed to cchange it into a different typo :( Maybe I need to invest in a spell checker...
Quoted 6 lines
These days checkpatch.pl does some of this for you (see
scripts/spelling.txt). However your "reudce" isn't there, and, more importantly, AFAICT checkpatch.pl does not look at the patch subject anyway.Joe, Andy, hint, hint. ;)
Patches happily accepted, (hint back..:)
(adding Kees Cook too)
Joe Perches
maintainerPATCH 1/1 checkpatch: Add spell checking of email subject line
In reply to Jani NikulaOnly commit log and patch additions are checked for typos and spelling errors currently. Add a check of the email subject line too.
--- scripts/checkpatch.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
scripts/checkpatch.pl +2 -1
@@ -2303,7 +2303,8 @@ sub process { } # Check for various typo / spelling mistakes - if (defined($misspellings) && ($in_commit_log || $line =~ /^\+/)) { + if (defined($misspellings) && + ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) { while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:$|[^a-z@])/gi) { my $typo = $1; my $typo_fix = $spelling_fix{lc($typo)};
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Re: [PATCH] checkpatch: Add spell checking of email subject line
Quoted 6 lines · Joe Perches
Only commit log and patch additions are checked for typos and spelling errors currently. Add a check of the email subject line too.
Suggested-by Jani Nikula <[email protected]>Signed-off-by Joe Perches <[email protected]>
Thanks Joe.
FWIW,
Quoted 20 lines
--- scripts/checkpatch.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)scripts/checkpatch.pl +2
-1@@ -2303,7 +2303,8 @@ sub process { } # Check for various typo / spelling mistakes - if (defined($misspellings) && ($in_commit_log || $line =~ /^\+/)) { + if (defined($misspellings) && + ($in_commit_log || $line =~ /^(?:\+|Subject:)/i)) { while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:$|[^a-z@])/gi) { my $typo = $1; my $typo_fix = $spelling_fix{lc($typo)};
Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
PATCH 1/1 checkpatch: spell check reudce
In reply to Joe PerchesReferences: http://mid.gmane.org/[email protected]
--- scripts/spelling.txt | 1 + 1 file changed, 1 insertion(+)
scripts/spelling.txt +1 -0
@@ -825,6 +825,7 @@ retreived||retrieved retreive||retrieve retrive||retrieve retuned||returned +reudce||reduce reuest||request reuqest||request reutnred||returned
Signature · 6 lines
2.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [PATCH] checkpatch: spell check reudce
Task id: 5903 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -2 275/275 273/275
ILK 307/307 307/307 SNB 284/284 284/284 IVB 375/375 375/375 BYT 294/294 294/294 HSW 385/385 385/385 BDW -1 314/314 313/314 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied PNV igt_gen3_render_tiledx_blits FAIL(1)PASS(3) FAIL(2) PNV igt_gen3_render_tiledy_blits FAIL(1)PASS(1) FAIL(2) *BDW igt_gem_gtt_hog PASS(2) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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