Fix PMU interrupt affinity for Juno*

Hi all,

This is version three of the patches previously posted here:

v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/322251.html
v2: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-February/326570.html

Changes since v2 include:

- Split the binding docs out into a separate patch
- Fixed failure path when we fail to find the logical CPU for an IRQ
- Fixed of_node reference leak
- Tidied up strings in error messages

Feedback welcome,

Will

--->8

Will Deacon (4):
dt: pmu: extend ARM PMU binding to allow for explicit interrupt
affinity
ARM: pmu: add support for interrupt-affinity property
arm64: pmu: add support for interrupt-affinity property
arm64: dts: add interrupt-affinity property to pmu node for juno

 Documentation/devicetree/bindings/arm/pmu.txt |  7 +++
 arch/arm/include/asm/pmu.h                    |  1 +
 arch/arm/kernel/perf_event_cpu.c              | 69 ++++++++++++++++++++++++---
 arch/arm64/boot/dts/arm/juno.dts              | 14 ++++--
 arch/arm64/include/asm/pmu.h                  |  1 +
 arch/arm64/kernel/perf_event.c                | 57 ++++++++++++++++++++--
 6 files changed, 134 insertions(+), 15 deletions(-)

2.1.4

The current ARM PMU binding relies on the PMU interrupts being listed in CPU logical order, which the device-tree author simply cannot know anything about.

This patch introduces a new "interrupt-affinity" property, which makes the relationship between the PMU interrupts and their corresponding CPU explicit.

---
 Documentation/devicetree/bindings/arm/pmu.txt | 7 +++++++
 1 file changed, 7 insertions(+)

index 75ef91d08f3b..f52d05660dc9 100644
@@ -24,6 +24,13 @@ Required properties:
 
 Optional properties:
 
+- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
+                       to CPU nodes corresponding directly to the affinity of
+		       the SPIs listed in the interrupts property.
+
+		       This property should be present when there is more than
+		       a single SPI.
+
 - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
                      events.
 

2.1.4

Historically, the PMU devicetree bindings have expected SPIs to be listed in order of *logical* CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree.

This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property.

---
 arch/arm/include/asm/pmu.h       |  1 +
 arch/arm/kernel/perf_event_cpu.c | 69 ++++++++++++++++++++++++++++++++++++----
 2 files changed, 63 insertions(+), 7 deletions(-)

index b1596bd59129..675e4ab79f68 100644
@@ -92,6 +92,7 @@ struct pmu_hw_events {
 struct arm_pmu {
 	struct pmu	pmu;
 	cpumask_t	active_irqs;
+	int		*irq_affinity;
 	char		*name;
 	irqreturn_t	(*handle_irq)(int irq_num, void *dev);
 	void		(*enable)(struct perf_event *event);

2.1.4

Historically, the PMU devicetree bindings have expected SPIs to be listed in order of *logical* CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree.

This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property.

---
 arch/arm64/include/asm/pmu.h   |  1 +
 arch/arm64/kernel/perf_event.c | 57 +++++++++++++++++++++++++++++++++++++++---
 2 files changed, 54 insertions(+), 4 deletions(-)

index e6f087806aaf..b7710a59672c 100644
@@ -44,6 +44,7 @@ struct pmu_hw_events {
 struct arm_pmu {
 	struct pmu		pmu;
 	cpumask_t		active_irqs;
+	int			*irq_affinity;
 	const char		*name;
 	irqreturn_t		(*handle_irq)(int irq_num, void *dev);
 	void			(*enable)(struct hw_perf_event *evt, int idx);

2.1.4

Make the Juno .dts robust against potential reordering of the CPU nodes by adding an explicit interrupt-affinity property to the PMU node. While we're at it, fix the PMU interrupts numbers too.

---
 arch/arm64/boot/dts/arm/juno.dts | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

index 133ee59de2d7..5e9110a3353d 100644
@@ -120,12 +120,18 @@
 
 	pmu {
 		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&A57_0>,
+				     <&A57_1>,
+				     <&A53_0>,
+				     <&A53_1>,
+				     <&A53_2>,
+				     <&A53_3>;
 	};
 
 	/include/ "juno-clocks.dtsi"

2.1.4

[adding arm-soc folks]

Hi Arnd, Olof,

Could you take this Juno .dts patch via arm-soc for 4.1 please? I'll queue the perf code to make use of the new binding, but there's not a strict dependency (the interrupt-affinity property will be ignored by older kernels).

Cheers,

Will

Gentle ping, although I guess most people were tied up with ELC/ACPI this week.

Happy to resend the patch if necessary.

Will

Yeah, please resend. Getting just a comment on the thread to arm at kernel.org works to get our attention, but it's awkward to apply patches that way. Resend and I'll be happy to apply.

-Olof